2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/iommu.h>
13 #include <linux/reset.h>
15 #include <soc/tegra/pmc.h>
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_plane_helper.h>
25 struct tegra_dc_soc_info {
26 bool supports_border_color;
27 bool supports_interlacing;
29 bool supports_block_linear;
30 unsigned int pitch_align;
35 struct drm_plane base;
39 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
41 return container_of(plane, struct tegra_plane, base);
44 struct tegra_dc_state {
45 struct drm_crtc_state base;
54 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
57 return container_of(state, struct tegra_dc_state, base);
62 struct tegra_plane_state {
63 struct drm_plane_state base;
65 struct tegra_bo_tiling tiling;
70 static inline struct tegra_plane_state *
71 to_tegra_plane_state(struct drm_plane_state *state)
74 return container_of(state, struct tegra_plane_state, base);
79 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
88 * Reads the active copy of a register. This takes the dc->lock spinlock to
89 * prevent races with the VBLANK processing which also needs access to the
90 * active copy of some registers.
92 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
97 spin_lock_irqsave(&dc->lock, flags);
99 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
100 value = tegra_dc_readl(dc, offset);
101 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
103 spin_unlock_irqrestore(&dc->lock, flags);
108 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
109 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
110 * Latching happens mmediately if the display controller is in STOP mode or
111 * on the next frame boundary otherwise.
113 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
114 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
115 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
116 * into the ACTIVE copy, either immediately if the display controller is in
117 * STOP mode, or at the next frame boundary otherwise.
119 void tegra_dc_commit(struct tegra_dc *dc)
121 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
122 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
125 static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
127 /* assume no swapping of fetched data */
129 *swap = BYTE_SWAP_NOSWAP;
132 case DRM_FORMAT_XBGR8888:
133 *format = WIN_COLOR_DEPTH_R8G8B8A8;
136 case DRM_FORMAT_XRGB8888:
137 *format = WIN_COLOR_DEPTH_B8G8R8A8;
140 case DRM_FORMAT_RGB565:
141 *format = WIN_COLOR_DEPTH_B5G6R5;
144 case DRM_FORMAT_UYVY:
145 *format = WIN_COLOR_DEPTH_YCbCr422;
148 case DRM_FORMAT_YUYV:
150 *swap = BYTE_SWAP_SWAP2;
152 *format = WIN_COLOR_DEPTH_YCbCr422;
155 case DRM_FORMAT_YUV420:
156 *format = WIN_COLOR_DEPTH_YCbCr420P;
159 case DRM_FORMAT_YUV422:
160 *format = WIN_COLOR_DEPTH_YCbCr422P;
170 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
173 case WIN_COLOR_DEPTH_YCbCr422:
174 case WIN_COLOR_DEPTH_YUV422:
180 case WIN_COLOR_DEPTH_YCbCr420P:
181 case WIN_COLOR_DEPTH_YUV420P:
182 case WIN_COLOR_DEPTH_YCbCr422P:
183 case WIN_COLOR_DEPTH_YUV422P:
184 case WIN_COLOR_DEPTH_YCbCr422R:
185 case WIN_COLOR_DEPTH_YUV422R:
186 case WIN_COLOR_DEPTH_YCbCr422RA:
187 case WIN_COLOR_DEPTH_YUV422RA:
200 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
203 fixed20_12 outf = dfixed_init(out);
204 fixed20_12 inf = dfixed_init(in);
225 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
226 inf.full -= dfixed_const(1);
228 dda_inc = dfixed_div(inf, outf);
229 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
234 static inline u32 compute_initial_dda(unsigned int in)
236 fixed20_12 inf = dfixed_init(in);
237 return dfixed_frac(inf);
240 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
241 const struct tegra_dc_window *window)
243 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
244 unsigned long value, flags;
248 * For YUV planar modes, the number of bytes per pixel takes into
249 * account only the luma component and therefore is 1.
251 yuv = tegra_dc_format_is_yuv(window->format, &planar);
253 bpp = window->bits_per_pixel / 8;
255 bpp = planar ? 1 : 2;
257 spin_lock_irqsave(&dc->lock, flags);
259 value = WINDOW_A_SELECT << index;
260 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
262 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
263 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
265 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
266 tegra_dc_writel(dc, value, DC_WIN_POSITION);
268 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
269 tegra_dc_writel(dc, value, DC_WIN_SIZE);
271 h_offset = window->src.x * bpp;
272 v_offset = window->src.y;
273 h_size = window->src.w * bpp;
274 v_size = window->src.h;
276 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
277 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
280 * For DDA computations the number of bytes per pixel for YUV planar
281 * modes needs to take into account all Y, U and V components.
286 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
287 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
289 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
290 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
292 h_dda = compute_initial_dda(window->src.x);
293 v_dda = compute_initial_dda(window->src.y);
295 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
296 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
298 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
299 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
301 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
304 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
305 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
306 value = window->stride[1] << 16 | window->stride[0];
307 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
309 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
312 if (window->bottom_up)
313 v_offset += window->src.h - 1;
315 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
316 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
318 if (dc->soc->supports_block_linear) {
319 unsigned long height = window->tiling.value;
321 switch (window->tiling.mode) {
322 case TEGRA_BO_TILING_MODE_PITCH:
323 value = DC_WINBUF_SURFACE_KIND_PITCH;
326 case TEGRA_BO_TILING_MODE_TILED:
327 value = DC_WINBUF_SURFACE_KIND_TILED;
330 case TEGRA_BO_TILING_MODE_BLOCK:
331 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
332 DC_WINBUF_SURFACE_KIND_BLOCK;
336 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
338 switch (window->tiling.mode) {
339 case TEGRA_BO_TILING_MODE_PITCH:
340 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
341 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
344 case TEGRA_BO_TILING_MODE_TILED:
345 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
346 DC_WIN_BUFFER_ADDR_MODE_TILE;
349 case TEGRA_BO_TILING_MODE_BLOCK:
351 * No need to handle this here because ->atomic_check
352 * will already have filtered it out.
357 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
363 /* setup default colorspace conversion coefficients */
364 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
365 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
366 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
367 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
368 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
369 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
370 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
371 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
374 } else if (window->bits_per_pixel < 24) {
375 value |= COLOR_EXPAND;
378 if (window->bottom_up)
379 value |= V_DIRECTION;
381 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
384 * Disable blending and assume Window A is the bottom-most window,
385 * Window C is the top-most window and Window B is in the middle.
387 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
388 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
394 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
399 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
400 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
404 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
405 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
406 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
410 spin_unlock_irqrestore(&dc->lock, flags);
413 static void tegra_plane_destroy(struct drm_plane *plane)
415 struct tegra_plane *p = to_tegra_plane(plane);
417 drm_plane_cleanup(plane);
421 static const u32 tegra_primary_plane_formats[] = {
427 static void tegra_primary_plane_destroy(struct drm_plane *plane)
429 tegra_plane_destroy(plane);
432 static void tegra_plane_reset(struct drm_plane *plane)
434 struct tegra_plane_state *state;
437 __drm_atomic_helper_plane_destroy_state(plane->state);
442 state = kzalloc(sizeof(*state), GFP_KERNEL);
444 plane->state = &state->base;
445 plane->state->plane = plane;
449 static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
451 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
452 struct tegra_plane_state *copy;
454 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
458 __drm_atomic_helper_plane_duplicate_state(plane, ©->base);
459 copy->tiling = state->tiling;
460 copy->format = state->format;
461 copy->swap = state->swap;
466 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
467 struct drm_plane_state *state)
469 __drm_atomic_helper_plane_destroy_state(state);
473 static const struct drm_plane_funcs tegra_primary_plane_funcs = {
474 .update_plane = drm_atomic_helper_update_plane,
475 .disable_plane = drm_atomic_helper_disable_plane,
476 .destroy = tegra_primary_plane_destroy,
477 .reset = tegra_plane_reset,
478 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
479 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
482 static int tegra_plane_prepare_fb(struct drm_plane *plane,
483 const struct drm_plane_state *new_state)
488 static void tegra_plane_cleanup_fb(struct drm_plane *plane,
489 const struct drm_plane_state *old_fb)
493 static int tegra_plane_state_add(struct tegra_plane *plane,
494 struct drm_plane_state *state)
496 struct drm_crtc_state *crtc_state;
497 struct tegra_dc_state *tegra;
499 /* Propagate errors from allocation or locking failures. */
500 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
501 if (IS_ERR(crtc_state))
502 return PTR_ERR(crtc_state);
504 tegra = to_dc_state(crtc_state);
506 tegra->planes |= WIN_A_ACT_REQ << plane->index;
511 static int tegra_plane_atomic_check(struct drm_plane *plane,
512 struct drm_plane_state *state)
514 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
515 struct tegra_bo_tiling *tiling = &plane_state->tiling;
516 struct tegra_plane *tegra = to_tegra_plane(plane);
517 struct tegra_dc *dc = to_tegra_dc(state->crtc);
520 /* no need for further checks if the plane is being disabled */
524 err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
529 err = tegra_fb_get_tiling(state->fb, tiling);
533 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
534 !dc->soc->supports_block_linear) {
535 DRM_ERROR("hardware doesn't support block linear mode\n");
540 * Tegra doesn't support different strides for U and V planes so we
541 * error out if the user tries to display a framebuffer with such a
544 if (drm_format_num_planes(state->fb->pixel_format) > 2) {
545 if (state->fb->pitches[2] != state->fb->pitches[1]) {
546 DRM_ERROR("unsupported UV-plane configuration\n");
551 err = tegra_plane_state_add(tegra, state);
558 static void tegra_plane_atomic_update(struct drm_plane *plane,
559 struct drm_plane_state *old_state)
561 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
562 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
563 struct drm_framebuffer *fb = plane->state->fb;
564 struct tegra_plane *p = to_tegra_plane(plane);
565 struct tegra_dc_window window;
568 /* rien ne va plus */
569 if (!plane->state->crtc || !plane->state->fb)
572 memset(&window, 0, sizeof(window));
573 window.src.x = plane->state->src_x >> 16;
574 window.src.y = plane->state->src_y >> 16;
575 window.src.w = plane->state->src_w >> 16;
576 window.src.h = plane->state->src_h >> 16;
577 window.dst.x = plane->state->crtc_x;
578 window.dst.y = plane->state->crtc_y;
579 window.dst.w = plane->state->crtc_w;
580 window.dst.h = plane->state->crtc_h;
581 window.bits_per_pixel = fb->bits_per_pixel;
582 window.bottom_up = tegra_fb_is_bottom_up(fb);
584 /* copy from state */
585 window.tiling = state->tiling;
586 window.format = state->format;
587 window.swap = state->swap;
589 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
590 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
592 window.base[i] = bo->paddr + fb->offsets[i];
593 window.stride[i] = fb->pitches[i];
596 tegra_dc_setup_window(dc, p->index, &window);
599 static void tegra_plane_atomic_disable(struct drm_plane *plane,
600 struct drm_plane_state *old_state)
602 struct tegra_plane *p = to_tegra_plane(plane);
607 /* rien ne va plus */
608 if (!old_state || !old_state->crtc)
611 dc = to_tegra_dc(old_state->crtc);
613 spin_lock_irqsave(&dc->lock, flags);
615 value = WINDOW_A_SELECT << p->index;
616 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
618 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
619 value &= ~WIN_ENABLE;
620 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
622 spin_unlock_irqrestore(&dc->lock, flags);
625 static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
626 .prepare_fb = tegra_plane_prepare_fb,
627 .cleanup_fb = tegra_plane_cleanup_fb,
628 .atomic_check = tegra_plane_atomic_check,
629 .atomic_update = tegra_plane_atomic_update,
630 .atomic_disable = tegra_plane_atomic_disable,
633 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
637 * Ideally this would use drm_crtc_mask(), but that would require the
638 * CRTC to already be in the mode_config's list of CRTCs. However, it
639 * will only be added to that list in the drm_crtc_init_with_planes()
640 * (in tegra_dc_init()), which in turn requires registration of these
641 * planes. So we have ourselves a nice little chicken and egg problem
644 * We work around this by manually creating the mask from the number
645 * of CRTCs that have been registered, and should therefore always be
646 * the same as drm_crtc_index() after registration.
648 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
649 struct tegra_plane *plane;
650 unsigned int num_formats;
654 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
656 return ERR_PTR(-ENOMEM);
658 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
659 formats = tegra_primary_plane_formats;
661 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
662 &tegra_primary_plane_funcs, formats,
663 num_formats, DRM_PLANE_TYPE_PRIMARY,
670 drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
675 static const u32 tegra_cursor_plane_formats[] = {
679 static int tegra_cursor_atomic_check(struct drm_plane *plane,
680 struct drm_plane_state *state)
682 struct tegra_plane *tegra = to_tegra_plane(plane);
685 /* no need for further checks if the plane is being disabled */
689 /* scaling not supported for cursor */
690 if ((state->src_w >> 16 != state->crtc_w) ||
691 (state->src_h >> 16 != state->crtc_h))
694 /* only square cursors supported */
695 if (state->src_w != state->src_h)
698 if (state->crtc_w != 32 && state->crtc_w != 64 &&
699 state->crtc_w != 128 && state->crtc_w != 256)
702 err = tegra_plane_state_add(tegra, state);
709 static void tegra_cursor_atomic_update(struct drm_plane *plane,
710 struct drm_plane_state *old_state)
712 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
713 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
714 struct drm_plane_state *state = plane->state;
715 u32 value = CURSOR_CLIP_DISPLAY;
717 /* rien ne va plus */
718 if (!plane->state->crtc || !plane->state->fb)
721 switch (state->crtc_w) {
723 value |= CURSOR_SIZE_32x32;
727 value |= CURSOR_SIZE_64x64;
731 value |= CURSOR_SIZE_128x128;
735 value |= CURSOR_SIZE_256x256;
739 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
744 value |= (bo->paddr >> 10) & 0x3fffff;
745 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
747 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
748 value = (bo->paddr >> 32) & 0x3;
749 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
752 /* enable cursor and set blend mode */
753 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
754 value |= CURSOR_ENABLE;
755 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
757 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
758 value &= ~CURSOR_DST_BLEND_MASK;
759 value &= ~CURSOR_SRC_BLEND_MASK;
760 value |= CURSOR_MODE_NORMAL;
761 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
762 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
763 value |= CURSOR_ALPHA;
764 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
766 /* position the cursor */
767 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
768 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
771 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
772 struct drm_plane_state *old_state)
777 /* rien ne va plus */
778 if (!old_state || !old_state->crtc)
781 dc = to_tegra_dc(old_state->crtc);
783 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
784 value &= ~CURSOR_ENABLE;
785 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
788 static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
789 .update_plane = drm_atomic_helper_update_plane,
790 .disable_plane = drm_atomic_helper_disable_plane,
791 .destroy = tegra_plane_destroy,
792 .reset = tegra_plane_reset,
793 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
794 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
797 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
798 .prepare_fb = tegra_plane_prepare_fb,
799 .cleanup_fb = tegra_plane_cleanup_fb,
800 .atomic_check = tegra_cursor_atomic_check,
801 .atomic_update = tegra_cursor_atomic_update,
802 .atomic_disable = tegra_cursor_atomic_disable,
805 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
808 struct tegra_plane *plane;
809 unsigned int num_formats;
813 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
815 return ERR_PTR(-ENOMEM);
818 * This index is kind of fake. The cursor isn't a regular plane, but
819 * its update and activation request bits in DC_CMD_STATE_CONTROL do
820 * use the same programming. Setting this fake index here allows the
821 * code in tegra_add_plane_state() to do the right thing without the
822 * need to special-casing the cursor plane.
826 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
827 formats = tegra_cursor_plane_formats;
829 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
830 &tegra_cursor_plane_funcs, formats,
831 num_formats, DRM_PLANE_TYPE_CURSOR,
838 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
843 static void tegra_overlay_plane_destroy(struct drm_plane *plane)
845 tegra_plane_destroy(plane);
848 static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
849 .update_plane = drm_atomic_helper_update_plane,
850 .disable_plane = drm_atomic_helper_disable_plane,
851 .destroy = tegra_overlay_plane_destroy,
852 .reset = tegra_plane_reset,
853 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
854 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
857 static const uint32_t tegra_overlay_plane_formats[] = {
867 static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
868 .prepare_fb = tegra_plane_prepare_fb,
869 .cleanup_fb = tegra_plane_cleanup_fb,
870 .atomic_check = tegra_plane_atomic_check,
871 .atomic_update = tegra_plane_atomic_update,
872 .atomic_disable = tegra_plane_atomic_disable,
875 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
879 struct tegra_plane *plane;
880 unsigned int num_formats;
884 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
886 return ERR_PTR(-ENOMEM);
888 plane->index = index;
890 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
891 formats = tegra_overlay_plane_formats;
893 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
894 &tegra_overlay_plane_funcs, formats,
895 num_formats, DRM_PLANE_TYPE_OVERLAY,
902 drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
907 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
909 struct drm_plane *plane;
912 for (i = 0; i < 2; i++) {
913 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
915 return PTR_ERR(plane);
921 u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
924 return host1x_syncpt_read(dc->syncpt);
926 /* fallback to software emulated VBLANK counter */
927 return drm_crtc_vblank_count(&dc->base);
930 void tegra_dc_enable_vblank(struct tegra_dc *dc)
932 unsigned long value, flags;
934 spin_lock_irqsave(&dc->lock, flags);
936 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
938 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
940 spin_unlock_irqrestore(&dc->lock, flags);
943 void tegra_dc_disable_vblank(struct tegra_dc *dc)
945 unsigned long value, flags;
947 spin_lock_irqsave(&dc->lock, flags);
949 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
950 value &= ~VBLANK_INT;
951 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
953 spin_unlock_irqrestore(&dc->lock, flags);
956 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
958 struct drm_device *drm = dc->base.dev;
959 struct drm_crtc *crtc = &dc->base;
960 unsigned long flags, base;
963 spin_lock_irqsave(&drm->event_lock, flags);
966 spin_unlock_irqrestore(&drm->event_lock, flags);
970 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
972 spin_lock(&dc->lock);
974 /* check if new start address has been latched */
975 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
976 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
977 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
978 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
980 spin_unlock(&dc->lock);
982 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
983 drm_crtc_send_vblank_event(crtc, dc->event);
984 drm_crtc_vblank_put(crtc);
988 spin_unlock_irqrestore(&drm->event_lock, flags);
991 static void tegra_dc_destroy(struct drm_crtc *crtc)
993 drm_crtc_cleanup(crtc);
996 static void tegra_crtc_reset(struct drm_crtc *crtc)
998 struct tegra_dc_state *state;
1001 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1006 state = kzalloc(sizeof(*state), GFP_KERNEL);
1008 crtc->state = &state->base;
1009 crtc->state->crtc = crtc;
1012 drm_crtc_vblank_reset(crtc);
1015 static struct drm_crtc_state *
1016 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1018 struct tegra_dc_state *state = to_dc_state(crtc->state);
1019 struct tegra_dc_state *copy;
1021 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1025 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1026 copy->clk = state->clk;
1027 copy->pclk = state->pclk;
1028 copy->div = state->div;
1029 copy->planes = state->planes;
1034 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1035 struct drm_crtc_state *state)
1037 __drm_atomic_helper_crtc_destroy_state(state);
1041 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1042 .page_flip = drm_atomic_helper_page_flip,
1043 .set_config = drm_atomic_helper_set_config,
1044 .destroy = tegra_dc_destroy,
1045 .reset = tegra_crtc_reset,
1046 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1047 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1050 static int tegra_dc_set_timings(struct tegra_dc *dc,
1051 struct drm_display_mode *mode)
1053 unsigned int h_ref_to_sync = 1;
1054 unsigned int v_ref_to_sync = 1;
1055 unsigned long value;
1057 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1059 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1060 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1062 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1063 ((mode->hsync_end - mode->hsync_start) << 0);
1064 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1066 value = ((mode->vtotal - mode->vsync_end) << 16) |
1067 ((mode->htotal - mode->hsync_end) << 0);
1068 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1070 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1071 ((mode->hsync_start - mode->hdisplay) << 0);
1072 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1074 value = (mode->vdisplay << 16) | mode->hdisplay;
1075 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1081 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1083 * @dc: display controller
1084 * @crtc_state: CRTC atomic state
1085 * @clk: parent clock for display controller
1086 * @pclk: pixel clock
1087 * @div: shift clock divider
1090 * 0 on success or a negative error-code on failure.
1092 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1093 struct drm_crtc_state *crtc_state,
1094 struct clk *clk, unsigned long pclk,
1097 struct tegra_dc_state *state = to_dc_state(crtc_state);
1099 if (!clk_has_parent(dc->clk, clk))
1109 static void tegra_dc_commit_state(struct tegra_dc *dc,
1110 struct tegra_dc_state *state)
1115 err = clk_set_parent(dc->clk, state->clk);
1117 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1120 * Outputs may not want to change the parent clock rate. This is only
1121 * relevant to Tegra20 where only a single display PLL is available.
1122 * Since that PLL would typically be used for HDMI, an internal LVDS
1123 * panel would need to be driven by some other clock such as PLL_P
1124 * which is shared with other peripherals. Changing the clock rate
1125 * should therefore be avoided.
1127 if (state->pclk > 0) {
1128 err = clk_set_rate(state->clk, state->pclk);
1131 "failed to set clock rate to %lu Hz\n",
1135 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1137 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1139 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1140 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1143 static void tegra_dc_stop(struct tegra_dc *dc)
1147 /* stop the display controller */
1148 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1149 value &= ~DISP_CTRL_MODE_MASK;
1150 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1152 tegra_dc_commit(dc);
1155 static bool tegra_dc_idle(struct tegra_dc *dc)
1159 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1161 return (value & DISP_CTRL_MODE_MASK) == 0;
1164 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1166 timeout = jiffies + msecs_to_jiffies(timeout);
1168 while (time_before(jiffies, timeout)) {
1169 if (tegra_dc_idle(dc))
1172 usleep_range(1000, 2000);
1175 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1179 static void tegra_crtc_disable(struct drm_crtc *crtc)
1181 struct tegra_dc *dc = to_tegra_dc(crtc);
1184 if (!tegra_dc_idle(dc)) {
1188 * Ignore the return value, there isn't anything useful to do
1189 * in case this fails.
1191 tegra_dc_wait_idle(dc, 100);
1195 * This should really be part of the RGB encoder driver, but clearing
1196 * these bits has the side-effect of stopping the display controller.
1197 * When that happens no VBLANK interrupts will be raised. At the same
1198 * time the encoder is disabled before the display controller, so the
1199 * above code is always going to timeout waiting for the controller
1202 * Given the close coupling between the RGB encoder and the display
1203 * controller doing it here is still kind of okay. None of the other
1204 * encoder drivers require these bits to be cleared.
1206 * XXX: Perhaps given that the display controller is switched off at
1207 * this point anyway maybe clearing these bits isn't even useful for
1211 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1212 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1213 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1214 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1217 tegra_dc_stats_reset(&dc->stats);
1218 drm_crtc_vblank_off(crtc);
1221 static void tegra_crtc_enable(struct drm_crtc *crtc)
1223 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1224 struct tegra_dc_state *state = to_dc_state(crtc->state);
1225 struct tegra_dc *dc = to_tegra_dc(crtc);
1228 tegra_dc_commit_state(dc, state);
1230 /* program display mode */
1231 tegra_dc_set_timings(dc, mode);
1233 /* interlacing isn't supported yet, so disable it */
1234 if (dc->soc->supports_interlacing) {
1235 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1236 value &= ~INTERLACE_ENABLE;
1237 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1240 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1241 value &= ~DISP_CTRL_MODE_MASK;
1242 value |= DISP_CTRL_MODE_C_DISPLAY;
1243 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1245 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1246 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1247 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1248 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1250 tegra_dc_commit(dc);
1252 drm_crtc_vblank_on(crtc);
1255 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1256 struct drm_crtc_state *state)
1261 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1262 struct drm_crtc_state *old_crtc_state)
1264 struct tegra_dc *dc = to_tegra_dc(crtc);
1266 if (crtc->state->event) {
1267 crtc->state->event->pipe = drm_crtc_index(crtc);
1269 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1271 dc->event = crtc->state->event;
1272 crtc->state->event = NULL;
1276 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1277 struct drm_crtc_state *old_crtc_state)
1279 struct tegra_dc_state *state = to_dc_state(crtc->state);
1280 struct tegra_dc *dc = to_tegra_dc(crtc);
1282 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1283 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1286 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1287 .disable = tegra_crtc_disable,
1288 .enable = tegra_crtc_enable,
1289 .atomic_check = tegra_crtc_atomic_check,
1290 .atomic_begin = tegra_crtc_atomic_begin,
1291 .atomic_flush = tegra_crtc_atomic_flush,
1294 static irqreturn_t tegra_dc_irq(int irq, void *data)
1296 struct tegra_dc *dc = data;
1297 unsigned long status;
1299 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1300 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1302 if (status & FRAME_END_INT) {
1304 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1309 if (status & VBLANK_INT) {
1311 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1313 drm_crtc_handle_vblank(&dc->base);
1314 tegra_dc_finish_page_flip(dc);
1318 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1320 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1322 dc->stats.underflow++;
1325 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1327 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1329 dc->stats.overflow++;
1335 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1337 struct drm_info_node *node = s->private;
1338 struct tegra_dc *dc = node->info_ent->data;
1341 drm_modeset_lock_crtc(&dc->base, NULL);
1343 if (!dc->base.state->active) {
1348 #define DUMP_REG(name) \
1349 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1350 tegra_dc_readl(dc, name))
1352 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1353 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1354 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1355 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1356 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1357 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1358 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1359 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1360 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1361 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1362 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1363 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1364 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1365 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1366 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1367 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1368 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1369 DUMP_REG(DC_CMD_INT_STATUS);
1370 DUMP_REG(DC_CMD_INT_MASK);
1371 DUMP_REG(DC_CMD_INT_ENABLE);
1372 DUMP_REG(DC_CMD_INT_TYPE);
1373 DUMP_REG(DC_CMD_INT_POLARITY);
1374 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1375 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1376 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1377 DUMP_REG(DC_CMD_STATE_ACCESS);
1378 DUMP_REG(DC_CMD_STATE_CONTROL);
1379 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1380 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1381 DUMP_REG(DC_COM_CRC_CONTROL);
1382 DUMP_REG(DC_COM_CRC_CHECKSUM);
1383 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1384 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1385 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1386 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1387 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1388 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1389 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1390 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1391 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1392 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1393 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1394 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1395 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1396 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1397 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1398 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1399 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1400 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1401 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1402 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1403 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1404 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1405 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1406 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1407 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1408 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1409 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1410 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1411 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1412 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1413 DUMP_REG(DC_COM_SPI_CONTROL);
1414 DUMP_REG(DC_COM_SPI_START_BYTE);
1415 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1416 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1417 DUMP_REG(DC_COM_HSPI_CS_DC);
1418 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1419 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1420 DUMP_REG(DC_COM_GPIO_CTRL);
1421 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1422 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1423 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1424 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1425 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1426 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1427 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1428 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1429 DUMP_REG(DC_DISP_REF_TO_SYNC);
1430 DUMP_REG(DC_DISP_SYNC_WIDTH);
1431 DUMP_REG(DC_DISP_BACK_PORCH);
1432 DUMP_REG(DC_DISP_ACTIVE);
1433 DUMP_REG(DC_DISP_FRONT_PORCH);
1434 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1435 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1436 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1437 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1438 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1439 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1440 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1441 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1442 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1443 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1444 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1445 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1446 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1447 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1448 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1449 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1450 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1451 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1452 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1453 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1454 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1455 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1456 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1457 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1458 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1459 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1460 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1461 DUMP_REG(DC_DISP_M0_CONTROL);
1462 DUMP_REG(DC_DISP_M1_CONTROL);
1463 DUMP_REG(DC_DISP_DI_CONTROL);
1464 DUMP_REG(DC_DISP_PP_CONTROL);
1465 DUMP_REG(DC_DISP_PP_SELECT_A);
1466 DUMP_REG(DC_DISP_PP_SELECT_B);
1467 DUMP_REG(DC_DISP_PP_SELECT_C);
1468 DUMP_REG(DC_DISP_PP_SELECT_D);
1469 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1470 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1471 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1472 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1473 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1474 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1475 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1476 DUMP_REG(DC_DISP_BORDER_COLOR);
1477 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1478 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1479 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1480 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1481 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1482 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1483 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1484 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1485 DUMP_REG(DC_DISP_CURSOR_POSITION);
1486 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1487 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1488 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1489 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1490 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1491 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1492 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1493 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1494 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1495 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1496 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1497 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1498 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1499 DUMP_REG(DC_DISP_SD_CONTROL);
1500 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1501 DUMP_REG(DC_DISP_SD_LUT(0));
1502 DUMP_REG(DC_DISP_SD_LUT(1));
1503 DUMP_REG(DC_DISP_SD_LUT(2));
1504 DUMP_REG(DC_DISP_SD_LUT(3));
1505 DUMP_REG(DC_DISP_SD_LUT(4));
1506 DUMP_REG(DC_DISP_SD_LUT(5));
1507 DUMP_REG(DC_DISP_SD_LUT(6));
1508 DUMP_REG(DC_DISP_SD_LUT(7));
1509 DUMP_REG(DC_DISP_SD_LUT(8));
1510 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1511 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1512 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1513 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1514 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1515 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1516 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1517 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1518 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1519 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1520 DUMP_REG(DC_DISP_SD_BL_TF(0));
1521 DUMP_REG(DC_DISP_SD_BL_TF(1));
1522 DUMP_REG(DC_DISP_SD_BL_TF(2));
1523 DUMP_REG(DC_DISP_SD_BL_TF(3));
1524 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1525 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1526 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1527 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1528 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1529 DUMP_REG(DC_WIN_WIN_OPTIONS);
1530 DUMP_REG(DC_WIN_BYTE_SWAP);
1531 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1532 DUMP_REG(DC_WIN_COLOR_DEPTH);
1533 DUMP_REG(DC_WIN_POSITION);
1534 DUMP_REG(DC_WIN_SIZE);
1535 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1536 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1537 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1538 DUMP_REG(DC_WIN_DDA_INC);
1539 DUMP_REG(DC_WIN_LINE_STRIDE);
1540 DUMP_REG(DC_WIN_BUF_STRIDE);
1541 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1542 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1543 DUMP_REG(DC_WIN_DV_CONTROL);
1544 DUMP_REG(DC_WIN_BLEND_NOKEY);
1545 DUMP_REG(DC_WIN_BLEND_1WIN);
1546 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1547 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1548 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1549 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1550 DUMP_REG(DC_WINBUF_START_ADDR);
1551 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1552 DUMP_REG(DC_WINBUF_START_ADDR_U);
1553 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1554 DUMP_REG(DC_WINBUF_START_ADDR_V);
1555 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1556 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1557 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1558 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1559 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1560 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1561 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1562 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1563 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1568 drm_modeset_unlock_crtc(&dc->base);
1572 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1574 struct drm_info_node *node = s->private;
1575 struct tegra_dc *dc = node->info_ent->data;
1579 drm_modeset_lock_crtc(&dc->base, NULL);
1581 if (!dc->base.state->active) {
1586 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1587 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1588 tegra_dc_commit(dc);
1590 drm_crtc_wait_one_vblank(&dc->base);
1591 drm_crtc_wait_one_vblank(&dc->base);
1593 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1594 seq_printf(s, "%08x\n", value);
1596 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1599 drm_modeset_unlock_crtc(&dc->base);
1603 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1605 struct drm_info_node *node = s->private;
1606 struct tegra_dc *dc = node->info_ent->data;
1608 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1609 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1610 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1611 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1616 static struct drm_info_list debugfs_files[] = {
1617 { "regs", tegra_dc_show_regs, 0, NULL },
1618 { "crc", tegra_dc_show_crc, 0, NULL },
1619 { "stats", tegra_dc_show_stats, 0, NULL },
1622 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1628 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1629 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1635 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1637 if (!dc->debugfs_files) {
1642 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1643 dc->debugfs_files[i].data = dc;
1645 err = drm_debugfs_create_files(dc->debugfs_files,
1646 ARRAY_SIZE(debugfs_files),
1647 dc->debugfs, minor);
1656 kfree(dc->debugfs_files);
1657 dc->debugfs_files = NULL;
1659 debugfs_remove(dc->debugfs);
1665 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1667 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1671 kfree(dc->debugfs_files);
1672 dc->debugfs_files = NULL;
1674 debugfs_remove(dc->debugfs);
1680 static int tegra_dc_init(struct host1x_client *client)
1682 struct drm_device *drm = dev_get_drvdata(client->parent);
1683 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1684 struct tegra_dc *dc = host1x_client_to_dc(client);
1685 struct tegra_drm *tegra = drm->dev_private;
1686 struct drm_plane *primary = NULL;
1687 struct drm_plane *cursor = NULL;
1691 dc->syncpt = host1x_syncpt_request(dc->dev, flags);
1693 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1695 if (tegra->domain) {
1696 err = iommu_attach_device(tegra->domain, dc->dev);
1698 dev_err(dc->dev, "failed to attach to domain: %d\n",
1703 dc->domain = tegra->domain;
1706 primary = tegra_dc_primary_plane_create(drm, dc);
1707 if (IS_ERR(primary)) {
1708 err = PTR_ERR(primary);
1712 if (dc->soc->supports_cursor) {
1713 cursor = tegra_dc_cursor_plane_create(drm, dc);
1714 if (IS_ERR(cursor)) {
1715 err = PTR_ERR(cursor);
1720 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1721 &tegra_crtc_funcs, NULL);
1725 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1728 * Keep track of the minimum pitch alignment across all display
1731 if (dc->soc->pitch_align > tegra->pitch_align)
1732 tegra->pitch_align = dc->soc->pitch_align;
1734 err = tegra_dc_rgb_init(drm, dc);
1735 if (err < 0 && err != -ENODEV) {
1736 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1740 err = tegra_dc_add_planes(drm, dc);
1744 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1745 err = tegra_dc_debugfs_init(dc, drm->primary);
1747 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1750 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1751 dev_name(dc->dev), dc);
1753 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1758 /* initialize display controller */
1760 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1762 value = SYNCPT_CNTRL_NO_STALL;
1763 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1765 value = SYNCPT_VSYNC_ENABLE | syncpt;
1766 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1769 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1770 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1771 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1773 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1774 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1775 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1777 /* initialize timer */
1778 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1779 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1780 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1782 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1783 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1784 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1786 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1787 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1788 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1790 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1791 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1792 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1794 if (dc->soc->supports_border_color)
1795 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1797 tegra_dc_stats_reset(&dc->stats);
1803 drm_plane_cleanup(cursor);
1806 drm_plane_cleanup(primary);
1808 if (tegra->domain) {
1809 iommu_detach_device(tegra->domain, dc->dev);
1816 static int tegra_dc_exit(struct host1x_client *client)
1818 struct tegra_dc *dc = host1x_client_to_dc(client);
1821 devm_free_irq(dc->dev, dc->irq, dc);
1823 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1824 err = tegra_dc_debugfs_exit(dc);
1826 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1829 err = tegra_dc_rgb_exit(dc);
1831 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1836 iommu_detach_device(dc->domain, dc->dev);
1840 host1x_syncpt_free(dc->syncpt);
1845 static const struct host1x_client_ops dc_client_ops = {
1846 .init = tegra_dc_init,
1847 .exit = tegra_dc_exit,
1850 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1851 .supports_border_color = true,
1852 .supports_interlacing = false,
1853 .supports_cursor = false,
1854 .supports_block_linear = false,
1856 .has_powergate = false,
1859 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1860 .supports_border_color = true,
1861 .supports_interlacing = false,
1862 .supports_cursor = false,
1863 .supports_block_linear = false,
1865 .has_powergate = false,
1868 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1869 .supports_border_color = true,
1870 .supports_interlacing = false,
1871 .supports_cursor = false,
1872 .supports_block_linear = false,
1874 .has_powergate = true,
1877 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1878 .supports_border_color = false,
1879 .supports_interlacing = true,
1880 .supports_cursor = true,
1881 .supports_block_linear = true,
1883 .has_powergate = true,
1886 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1887 .supports_border_color = false,
1888 .supports_interlacing = true,
1889 .supports_cursor = true,
1890 .supports_block_linear = true,
1892 .has_powergate = true,
1895 static const struct of_device_id tegra_dc_of_match[] = {
1897 .compatible = "nvidia,tegra210-dc",
1898 .data = &tegra210_dc_soc_info,
1900 .compatible = "nvidia,tegra124-dc",
1901 .data = &tegra124_dc_soc_info,
1903 .compatible = "nvidia,tegra114-dc",
1904 .data = &tegra114_dc_soc_info,
1906 .compatible = "nvidia,tegra30-dc",
1907 .data = &tegra30_dc_soc_info,
1909 .compatible = "nvidia,tegra20-dc",
1910 .data = &tegra20_dc_soc_info,
1915 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1917 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1919 struct device_node *np;
1923 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1925 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1928 * If the nvidia,head property isn't present, try to find the
1929 * correct head number by looking up the position of this
1930 * display controller's node within the device tree. Assuming
1931 * that the nodes are ordered properly in the DTS file and
1932 * that the translation into a flattened device tree blob
1933 * preserves that ordering this will actually yield the right
1936 * If those assumptions don't hold, this will still work for
1937 * cases where only a single display controller is used.
1939 for_each_matching_node(np, tegra_dc_of_match) {
1940 if (np == dc->dev->of_node) {
1954 static int tegra_dc_probe(struct platform_device *pdev)
1956 const struct of_device_id *id;
1957 struct resource *regs;
1958 struct tegra_dc *dc;
1961 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1965 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1969 spin_lock_init(&dc->lock);
1970 INIT_LIST_HEAD(&dc->list);
1971 dc->dev = &pdev->dev;
1974 err = tegra_dc_parse_dt(dc);
1978 dc->clk = devm_clk_get(&pdev->dev, NULL);
1979 if (IS_ERR(dc->clk)) {
1980 dev_err(&pdev->dev, "failed to get clock\n");
1981 return PTR_ERR(dc->clk);
1984 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1985 if (IS_ERR(dc->rst)) {
1986 dev_err(&pdev->dev, "failed to get reset\n");
1987 return PTR_ERR(dc->rst);
1990 if (dc->soc->has_powergate) {
1992 dc->powergate = TEGRA_POWERGATE_DIS;
1994 dc->powergate = TEGRA_POWERGATE_DISB;
1996 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1999 dev_err(&pdev->dev, "failed to power partition: %d\n",
2004 err = clk_prepare_enable(dc->clk);
2006 dev_err(&pdev->dev, "failed to enable clock: %d\n",
2011 err = reset_control_deassert(dc->rst);
2013 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
2019 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2020 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2021 if (IS_ERR(dc->regs))
2022 return PTR_ERR(dc->regs);
2024 dc->irq = platform_get_irq(pdev, 0);
2026 dev_err(&pdev->dev, "failed to get IRQ\n");
2030 INIT_LIST_HEAD(&dc->client.list);
2031 dc->client.ops = &dc_client_ops;
2032 dc->client.dev = &pdev->dev;
2034 err = tegra_dc_rgb_probe(dc);
2035 if (err < 0 && err != -ENODEV) {
2036 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2040 err = host1x_client_register(&dc->client);
2042 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2047 platform_set_drvdata(pdev, dc);
2052 static int tegra_dc_remove(struct platform_device *pdev)
2054 struct tegra_dc *dc = platform_get_drvdata(pdev);
2057 err = host1x_client_unregister(&dc->client);
2059 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2064 err = tegra_dc_rgb_remove(dc);
2066 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2070 reset_control_assert(dc->rst);
2072 if (dc->soc->has_powergate)
2073 tegra_powergate_power_off(dc->powergate);
2075 clk_disable_unprepare(dc->clk);
2080 struct platform_driver tegra_dc_driver = {
2083 .of_match_table = tegra_dc_of_match,
2085 .probe = tegra_dc_probe,
2086 .remove = tegra_dc_remove,