2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/delay.h>
11 #include <linux/gpio.h>
12 #include <linux/interrupt.h>
14 #include <linux/of_gpio.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17 #include <linux/regulator/consumer.h>
19 #include <drm/drm_dp_helper.h>
20 #include <drm/drm_panel.h>
25 static DEFINE_MUTEX(dpaux_lock);
26 static LIST_HEAD(dpaux_list);
29 struct drm_dp_aux aux;
35 struct tegra_output *output;
37 struct reset_control *rst;
38 struct clk *clk_parent;
41 struct regulator *vdd;
43 struct completion complete;
44 struct list_head list;
47 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
49 return container_of(aux, struct tegra_dpaux, aux);
52 static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux,
55 return readl(dpaux->regs + (offset << 2));
58 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
62 writel(value, dpaux->regs + (offset << 2));
65 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
68 unsigned long offset = DPAUX_DP_AUXDATA_WRITE(0);
71 for (i = 0; i < size; i += 4) {
72 size_t num = min_t(size_t, size - i, 4);
73 unsigned long value = 0;
75 for (j = 0; j < num; j++)
76 value |= buffer[i + j] << (j * 8);
78 tegra_dpaux_writel(dpaux, value, offset++);
82 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
85 unsigned long offset = DPAUX_DP_AUXDATA_READ(0);
88 for (i = 0; i < size; i += 4) {
89 size_t num = min_t(size_t, size - i, 4);
92 value = tegra_dpaux_readl(dpaux, offset++);
94 for (j = 0; j < num; j++)
95 buffer[i + j] = value >> (j * 8);
99 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
100 struct drm_dp_aux_msg *msg)
102 unsigned long value = DPAUX_DP_AUXCTL_TRANSACTREQ;
103 unsigned long timeout = msecs_to_jiffies(250);
104 struct tegra_dpaux *dpaux = to_dpaux(aux);
105 unsigned long status;
108 if (msg->size < 1 || msg->size > 16)
111 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
113 switch (msg->request & ~DP_AUX_I2C_MOT) {
114 case DP_AUX_I2C_WRITE:
115 if (msg->request & DP_AUX_I2C_MOT)
116 value = DPAUX_DP_AUXCTL_CMD_MOT_WR;
118 value = DPAUX_DP_AUXCTL_CMD_I2C_WR;
122 case DP_AUX_I2C_READ:
123 if (msg->request & DP_AUX_I2C_MOT)
124 value = DPAUX_DP_AUXCTL_CMD_MOT_RD;
126 value = DPAUX_DP_AUXCTL_CMD_I2C_RD;
130 case DP_AUX_I2C_STATUS:
131 if (msg->request & DP_AUX_I2C_MOT)
132 value = DPAUX_DP_AUXCTL_CMD_MOT_RQ;
134 value = DPAUX_DP_AUXCTL_CMD_I2C_RQ;
138 case DP_AUX_NATIVE_WRITE:
139 value = DPAUX_DP_AUXCTL_CMD_AUX_WR;
142 case DP_AUX_NATIVE_READ:
143 value = DPAUX_DP_AUXCTL_CMD_AUX_RD;
150 value |= DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
151 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
153 if ((msg->request & DP_AUX_I2C_READ) == 0) {
154 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
158 /* start transaction */
159 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
160 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
161 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
163 status = wait_for_completion_timeout(&dpaux->complete, timeout);
167 /* read status and clear errors */
168 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
169 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
171 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
174 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
175 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
176 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
179 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
181 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
185 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
189 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
193 msg->reply = DP_AUX_I2C_REPLY_NACK;
197 msg->reply = DP_AUX_I2C_REPLY_DEFER;
201 if (msg->reply == DP_AUX_NATIVE_REPLY_ACK) {
202 if (msg->request & DP_AUX_I2C_READ) {
203 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
205 if (WARN_ON(count != msg->size))
206 count = min_t(size_t, count, msg->size);
208 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
216 static irqreturn_t tegra_dpaux_irq(int irq, void *data)
218 struct tegra_dpaux *dpaux = data;
219 irqreturn_t ret = IRQ_HANDLED;
222 /* clear interrupts */
223 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
224 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
226 if (value & DPAUX_INTR_PLUG_EVENT) {
228 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
232 if (value & DPAUX_INTR_UNPLUG_EVENT) {
234 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
237 if (value & DPAUX_INTR_IRQ_EVENT) {
238 /* TODO: handle this */
241 if (value & DPAUX_INTR_AUX_DONE)
242 complete(&dpaux->complete);
247 static int tegra_dpaux_probe(struct platform_device *pdev)
249 struct tegra_dpaux *dpaux;
250 struct resource *regs;
254 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
258 init_completion(&dpaux->complete);
259 INIT_LIST_HEAD(&dpaux->list);
260 dpaux->dev = &pdev->dev;
262 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
263 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
264 if (IS_ERR(dpaux->regs))
265 return PTR_ERR(dpaux->regs);
267 dpaux->irq = platform_get_irq(pdev, 0);
268 if (dpaux->irq < 0) {
269 dev_err(&pdev->dev, "failed to get IRQ\n");
273 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
274 if (IS_ERR(dpaux->rst))
275 return PTR_ERR(dpaux->rst);
277 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
278 if (IS_ERR(dpaux->clk))
279 return PTR_ERR(dpaux->clk);
281 err = clk_prepare_enable(dpaux->clk);
285 reset_control_deassert(dpaux->rst);
287 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
288 if (IS_ERR(dpaux->clk_parent))
289 return PTR_ERR(dpaux->clk_parent);
291 err = clk_prepare_enable(dpaux->clk_parent);
295 err = clk_set_rate(dpaux->clk_parent, 270000000);
297 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
302 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
303 if (IS_ERR(dpaux->vdd))
304 return PTR_ERR(dpaux->vdd);
306 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
307 dev_name(dpaux->dev), dpaux);
309 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
314 dpaux->aux.transfer = tegra_dpaux_transfer;
315 dpaux->aux.dev = &pdev->dev;
317 err = drm_dp_aux_register_i2c_bus(&dpaux->aux);
321 /* enable and clear all interrupts */
322 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
323 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
324 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
325 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
327 mutex_lock(&dpaux_lock);
328 list_add_tail(&dpaux->list, &dpaux_list);
329 mutex_unlock(&dpaux_lock);
331 platform_set_drvdata(pdev, dpaux);
336 static int tegra_dpaux_remove(struct platform_device *pdev)
338 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
340 drm_dp_aux_unregister_i2c_bus(&dpaux->aux);
342 mutex_lock(&dpaux_lock);
343 list_del(&dpaux->list);
344 mutex_unlock(&dpaux_lock);
346 clk_disable_unprepare(dpaux->clk_parent);
347 reset_control_assert(dpaux->rst);
348 clk_disable_unprepare(dpaux->clk);
353 static const struct of_device_id tegra_dpaux_of_match[] = {
354 { .compatible = "nvidia,tegra124-dpaux", },
358 struct platform_driver tegra_dpaux_driver = {
360 .name = "tegra-dpaux",
361 .of_match_table = tegra_dpaux_of_match,
363 .probe = tegra_dpaux_probe,
364 .remove = tegra_dpaux_remove,
367 struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np)
369 struct tegra_dpaux *dpaux;
371 mutex_lock(&dpaux_lock);
373 list_for_each_entry(dpaux, &dpaux_list, list)
374 if (np == dpaux->dev->of_node) {
375 mutex_unlock(&dpaux_lock);
379 mutex_unlock(&dpaux_lock);
384 int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
386 unsigned long timeout;
389 dpaux->output = output;
391 err = regulator_enable(dpaux->vdd);
395 timeout = jiffies + msecs_to_jiffies(250);
397 while (time_before(jiffies, timeout)) {
398 enum drm_connector_status status;
400 status = tegra_dpaux_detect(dpaux);
401 if (status == connector_status_connected)
404 usleep_range(1000, 2000);
410 int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
412 unsigned long timeout;
415 err = regulator_disable(dpaux->vdd);
419 timeout = jiffies + msecs_to_jiffies(250);
421 while (time_before(jiffies, timeout)) {
422 enum drm_connector_status status;
424 status = tegra_dpaux_detect(dpaux);
425 if (status == connector_status_disconnected) {
426 dpaux->output = NULL;
430 usleep_range(1000, 2000);
436 enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
440 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
442 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
443 return connector_status_connected;
445 return connector_status_disconnected;
448 int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
452 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
453 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
454 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
455 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
456 DPAUX_HYBRID_PADCTL_MODE_AUX;
457 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
459 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
460 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
461 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
466 int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
470 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
471 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
472 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
477 int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding)
481 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
489 int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
492 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
493 u8 status[DP_LINK_STATUS_SIZE], values[4];
497 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern);
501 if (tp == DP_TRAINING_PATTERN_DISABLE)
504 for (i = 0; i < link->num_lanes; i++)
505 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
506 DP_TRAIN_PRE_EMPHASIS_0 |
507 DP_TRAIN_MAX_SWING_REACHED |
508 DP_TRAIN_VOLTAGE_SWING_400;
510 err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
515 usleep_range(500, 1000);
517 err = drm_dp_dpcd_read_link_status(&dpaux->aux, status);
522 case DP_TRAINING_PATTERN_1:
523 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
528 case DP_TRAINING_PATTERN_2:
529 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
535 dev_err(dpaux->dev, "unsupported training pattern %u\n", tp);
539 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0);