2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/bitops.h>
11 #include <linux/host1x.h>
12 #include <linux/idr.h>
13 #include <linux/iommu.h>
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_atomic_helper.h>
21 #define DRIVER_NAME "tegra"
22 #define DRIVER_DESC "NVIDIA Tegra graphics"
23 #define DRIVER_DATE "20120330"
24 #define DRIVER_MAJOR 0
25 #define DRIVER_MINOR 0
26 #define DRIVER_PATCHLEVEL 0
28 #define CARVEOUT_SZ SZ_64M
30 struct tegra_drm_file {
35 static void tegra_atomic_schedule(struct tegra_drm *tegra,
36 struct drm_atomic_state *state)
38 tegra->commit.state = state;
39 schedule_work(&tegra->commit.work);
42 static void tegra_atomic_complete(struct tegra_drm *tegra,
43 struct drm_atomic_state *state)
45 struct drm_device *drm = tegra->drm;
48 * Everything below can be run asynchronously without the need to grab
49 * any modeset locks at all under one condition: It must be guaranteed
50 * that the asynchronous work has either been cancelled (if the driver
51 * supports it, which at least requires that the framebuffers get
52 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
53 * before the new state gets committed on the software side with
54 * drm_atomic_helper_swap_state().
56 * This scheme allows new atomic state updates to be prepared and
57 * checked in parallel to the asynchronous completion of the previous
58 * update. Which is important since compositors need to figure out the
59 * composition of the next frame right after having submitted the
63 drm_atomic_helper_commit_modeset_disables(drm, state);
64 drm_atomic_helper_commit_modeset_enables(drm, state);
65 drm_atomic_helper_commit_planes(drm, state,
66 DRM_PLANE_COMMIT_ACTIVE_ONLY);
68 drm_atomic_helper_wait_for_vblanks(drm, state);
70 drm_atomic_helper_cleanup_planes(drm, state);
71 drm_atomic_state_put(state);
74 static void tegra_atomic_work(struct work_struct *work)
76 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
79 tegra_atomic_complete(tegra, tegra->commit.state);
82 static int tegra_atomic_commit(struct drm_device *drm,
83 struct drm_atomic_state *state, bool nonblock)
85 struct tegra_drm *tegra = drm->dev_private;
88 err = drm_atomic_helper_prepare_planes(drm, state);
92 /* serialize outstanding nonblocking commits */
93 mutex_lock(&tegra->commit.lock);
94 flush_work(&tegra->commit.work);
97 * This is the point of no return - everything below never fails except
98 * when the hw goes bonghits. Which means we can commit the new state on
99 * the software side now.
102 drm_atomic_helper_swap_state(state, true);
104 drm_atomic_state_get(state);
106 tegra_atomic_schedule(tegra, state);
108 tegra_atomic_complete(tegra, state);
110 mutex_unlock(&tegra->commit.lock);
114 static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
115 .fb_create = tegra_fb_create,
116 #ifdef CONFIG_DRM_FBDEV_EMULATION
117 .output_poll_changed = tegra_fb_output_poll_changed,
119 .atomic_check = drm_atomic_helper_check,
120 .atomic_commit = tegra_atomic_commit,
123 static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
125 struct host1x_device *device = to_host1x_device(drm->dev);
126 struct tegra_drm *tegra;
129 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
133 if (iommu_present(&platform_bus_type)) {
134 u64 carveout_start, carveout_end, gem_start, gem_end;
135 struct iommu_domain_geometry *geometry;
138 tegra->domain = iommu_domain_alloc(&platform_bus_type);
139 if (!tegra->domain) {
144 geometry = &tegra->domain->geometry;
145 gem_start = geometry->aperture_start;
146 gem_end = geometry->aperture_end - CARVEOUT_SZ;
147 carveout_start = gem_end + 1;
148 carveout_end = geometry->aperture_end;
150 order = __ffs(tegra->domain->pgsize_bitmap);
151 init_iova_domain(&tegra->carveout.domain, 1UL << order,
152 carveout_start >> order,
153 carveout_end >> order);
155 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
156 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
158 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
159 mutex_init(&tegra->mm_lock);
161 DRM_DEBUG("IOMMU apertures:\n");
162 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
163 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
167 mutex_init(&tegra->clients_lock);
168 INIT_LIST_HEAD(&tegra->clients);
170 mutex_init(&tegra->commit.lock);
171 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
173 drm->dev_private = tegra;
176 drm_mode_config_init(drm);
178 drm->mode_config.min_width = 0;
179 drm->mode_config.min_height = 0;
181 drm->mode_config.max_width = 4096;
182 drm->mode_config.max_height = 4096;
184 drm->mode_config.allow_fb_modifiers = true;
186 drm->mode_config.funcs = &tegra_drm_mode_funcs;
188 err = tegra_drm_fb_prepare(drm);
192 drm_kms_helper_poll_init(drm);
194 err = host1x_device_init(device);
199 * We don't use the drm_irq_install() helpers provided by the DRM
200 * core, so we need to set this manually in order to allow the
201 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
203 drm->irq_enabled = true;
205 /* syncpoints are used for full 32-bit hardware VBLANK counters */
206 drm->max_vblank_count = 0xffffffff;
208 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
212 drm_mode_config_reset(drm);
214 err = tegra_drm_fb_init(drm);
221 drm_vblank_cleanup(drm);
223 host1x_device_exit(device);
225 drm_kms_helper_poll_fini(drm);
226 tegra_drm_fb_free(drm);
228 drm_mode_config_cleanup(drm);
231 iommu_domain_free(tegra->domain);
232 drm_mm_takedown(&tegra->mm);
233 mutex_destroy(&tegra->mm_lock);
234 put_iova_domain(&tegra->carveout.domain);
241 static void tegra_drm_unload(struct drm_device *drm)
243 struct host1x_device *device = to_host1x_device(drm->dev);
244 struct tegra_drm *tegra = drm->dev_private;
247 drm_kms_helper_poll_fini(drm);
248 tegra_drm_fb_exit(drm);
249 drm_mode_config_cleanup(drm);
250 drm_vblank_cleanup(drm);
252 err = host1x_device_exit(device);
257 iommu_domain_free(tegra->domain);
258 drm_mm_takedown(&tegra->mm);
259 mutex_destroy(&tegra->mm_lock);
260 put_iova_domain(&tegra->carveout.domain);
266 static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
268 struct tegra_drm_file *fpriv;
270 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
274 idr_init(&fpriv->contexts);
275 mutex_init(&fpriv->lock);
276 filp->driver_priv = fpriv;
281 static void tegra_drm_context_free(struct tegra_drm_context *context)
283 context->client->ops->close_channel(context);
287 static void tegra_drm_lastclose(struct drm_device *drm)
289 #ifdef CONFIG_DRM_FBDEV_EMULATION
290 struct tegra_drm *tegra = drm->dev_private;
292 tegra_fbdev_restore_mode(tegra->fbdev);
296 static struct host1x_bo *
297 host1x_bo_lookup(struct drm_file *file, u32 handle)
299 struct drm_gem_object *gem;
302 gem = drm_gem_object_lookup(file, handle);
306 drm_gem_object_unreference_unlocked(gem);
308 bo = to_tegra_bo(gem);
312 static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
313 struct drm_tegra_reloc __user *src,
314 struct drm_device *drm,
315 struct drm_file *file)
320 err = get_user(cmdbuf, &src->cmdbuf.handle);
324 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
328 err = get_user(target, &src->target.handle);
332 err = get_user(dest->target.offset, &src->target.offset);
336 err = get_user(dest->shift, &src->shift);
340 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
341 if (!dest->cmdbuf.bo)
344 dest->target.bo = host1x_bo_lookup(file, target);
345 if (!dest->target.bo)
351 int tegra_drm_submit(struct tegra_drm_context *context,
352 struct drm_tegra_submit *args, struct drm_device *drm,
353 struct drm_file *file)
355 unsigned int num_cmdbufs = args->num_cmdbufs;
356 unsigned int num_relocs = args->num_relocs;
357 unsigned int num_waitchks = args->num_waitchks;
358 struct drm_tegra_cmdbuf __user *cmdbufs =
359 (void __user *)(uintptr_t)args->cmdbufs;
360 struct drm_tegra_reloc __user *relocs =
361 (void __user *)(uintptr_t)args->relocs;
362 struct drm_tegra_waitchk __user *waitchks =
363 (void __user *)(uintptr_t)args->waitchks;
364 struct drm_tegra_syncpt syncpt;
365 struct host1x_job *job;
368 /* We don't yet support other than one syncpt_incr struct per submit */
369 if (args->num_syncpts != 1)
372 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
373 args->num_relocs, args->num_waitchks);
377 job->num_relocs = args->num_relocs;
378 job->num_waitchk = args->num_waitchks;
379 job->client = (u32)args->context;
380 job->class = context->client->base.class;
381 job->serialize = true;
383 while (num_cmdbufs) {
384 struct drm_tegra_cmdbuf cmdbuf;
385 struct host1x_bo *bo;
387 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
392 bo = host1x_bo_lookup(file, cmdbuf.handle);
398 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
403 /* copy and resolve relocations from submit */
404 while (num_relocs--) {
405 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
406 &relocs[num_relocs], drm,
412 if (copy_from_user(job->waitchk, waitchks,
413 sizeof(*waitchks) * num_waitchks)) {
418 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
424 job->is_addr_reg = context->client->ops->is_addr_reg;
425 job->syncpt_incrs = syncpt.incrs;
426 job->syncpt_id = syncpt.id;
427 job->timeout = 10000;
429 if (args->timeout && args->timeout < 10000)
430 job->timeout = args->timeout;
432 err = host1x_job_pin(job, context->client->base.dev);
436 err = host1x_job_submit(job);
440 args->fence = job->syncpt_end;
446 host1x_job_unpin(job);
453 #ifdef CONFIG_DRM_TEGRA_STAGING
454 static struct tegra_drm_context *
455 tegra_drm_file_get_context(struct tegra_drm_file *file, u32 id)
457 struct tegra_drm_context *context;
459 mutex_lock(&file->lock);
460 context = idr_find(&file->contexts, id);
461 mutex_unlock(&file->lock);
466 static int tegra_gem_create(struct drm_device *drm, void *data,
467 struct drm_file *file)
469 struct drm_tegra_gem_create *args = data;
472 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
480 static int tegra_gem_mmap(struct drm_device *drm, void *data,
481 struct drm_file *file)
483 struct drm_tegra_gem_mmap *args = data;
484 struct drm_gem_object *gem;
487 gem = drm_gem_object_lookup(file, args->handle);
491 bo = to_tegra_bo(gem);
493 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
495 drm_gem_object_unreference_unlocked(gem);
500 static int tegra_syncpt_read(struct drm_device *drm, void *data,
501 struct drm_file *file)
503 struct host1x *host = dev_get_drvdata(drm->dev->parent);
504 struct drm_tegra_syncpt_read *args = data;
505 struct host1x_syncpt *sp;
507 sp = host1x_syncpt_get(host, args->id);
511 args->value = host1x_syncpt_read_min(sp);
515 static int tegra_syncpt_incr(struct drm_device *drm, void *data,
516 struct drm_file *file)
518 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
519 struct drm_tegra_syncpt_incr *args = data;
520 struct host1x_syncpt *sp;
522 sp = host1x_syncpt_get(host1x, args->id);
526 return host1x_syncpt_incr(sp);
529 static int tegra_syncpt_wait(struct drm_device *drm, void *data,
530 struct drm_file *file)
532 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
533 struct drm_tegra_syncpt_wait *args = data;
534 struct host1x_syncpt *sp;
536 sp = host1x_syncpt_get(host1x, args->id);
540 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
544 static int tegra_client_open(struct tegra_drm_file *fpriv,
545 struct tegra_drm_client *client,
546 struct tegra_drm_context *context)
550 err = client->ops->open_channel(client, context);
554 err = idr_alloc(&fpriv->contexts, context, 0, 0, GFP_KERNEL);
556 client->ops->close_channel(context);
560 context->client = client;
566 static int tegra_open_channel(struct drm_device *drm, void *data,
567 struct drm_file *file)
569 struct tegra_drm_file *fpriv = file->driver_priv;
570 struct tegra_drm *tegra = drm->dev_private;
571 struct drm_tegra_open_channel *args = data;
572 struct tegra_drm_context *context;
573 struct tegra_drm_client *client;
576 context = kzalloc(sizeof(*context), GFP_KERNEL);
580 mutex_lock(&fpriv->lock);
582 list_for_each_entry(client, &tegra->clients, list)
583 if (client->base.class == args->client) {
584 err = tegra_client_open(fpriv, client, context);
588 args->context = context->id;
595 mutex_unlock(&fpriv->lock);
599 static int tegra_close_channel(struct drm_device *drm, void *data,
600 struct drm_file *file)
602 struct tegra_drm_file *fpriv = file->driver_priv;
603 struct drm_tegra_close_channel *args = data;
604 struct tegra_drm_context *context;
607 mutex_lock(&fpriv->lock);
609 context = tegra_drm_file_get_context(fpriv, args->context);
615 idr_remove(&fpriv->contexts, context->id);
616 tegra_drm_context_free(context);
619 mutex_unlock(&fpriv->lock);
623 static int tegra_get_syncpt(struct drm_device *drm, void *data,
624 struct drm_file *file)
626 struct tegra_drm_file *fpriv = file->driver_priv;
627 struct drm_tegra_get_syncpt *args = data;
628 struct tegra_drm_context *context;
629 struct host1x_syncpt *syncpt;
632 mutex_lock(&fpriv->lock);
634 context = tegra_drm_file_get_context(fpriv, args->context);
640 if (args->index >= context->client->base.num_syncpts) {
645 syncpt = context->client->base.syncpts[args->index];
646 args->id = host1x_syncpt_id(syncpt);
649 mutex_unlock(&fpriv->lock);
653 static int tegra_submit(struct drm_device *drm, void *data,
654 struct drm_file *file)
656 struct tegra_drm_file *fpriv = file->driver_priv;
657 struct drm_tegra_submit *args = data;
658 struct tegra_drm_context *context;
661 mutex_lock(&fpriv->lock);
663 context = tegra_drm_file_get_context(fpriv, args->context);
669 err = context->client->ops->submit(context, args, drm, file);
672 mutex_unlock(&fpriv->lock);
676 static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
677 struct drm_file *file)
679 struct tegra_drm_file *fpriv = file->driver_priv;
680 struct drm_tegra_get_syncpt_base *args = data;
681 struct tegra_drm_context *context;
682 struct host1x_syncpt_base *base;
683 struct host1x_syncpt *syncpt;
686 mutex_lock(&fpriv->lock);
688 context = tegra_drm_file_get_context(fpriv, args->context);
694 if (args->syncpt >= context->client->base.num_syncpts) {
699 syncpt = context->client->base.syncpts[args->syncpt];
701 base = host1x_syncpt_get_base(syncpt);
707 args->id = host1x_syncpt_base_id(base);
710 mutex_unlock(&fpriv->lock);
714 static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
715 struct drm_file *file)
717 struct drm_tegra_gem_set_tiling *args = data;
718 enum tegra_bo_tiling_mode mode;
719 struct drm_gem_object *gem;
720 unsigned long value = 0;
723 switch (args->mode) {
724 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
725 mode = TEGRA_BO_TILING_MODE_PITCH;
727 if (args->value != 0)
732 case DRM_TEGRA_GEM_TILING_MODE_TILED:
733 mode = TEGRA_BO_TILING_MODE_TILED;
735 if (args->value != 0)
740 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
741 mode = TEGRA_BO_TILING_MODE_BLOCK;
753 gem = drm_gem_object_lookup(file, args->handle);
757 bo = to_tegra_bo(gem);
759 bo->tiling.mode = mode;
760 bo->tiling.value = value;
762 drm_gem_object_unreference_unlocked(gem);
767 static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
768 struct drm_file *file)
770 struct drm_tegra_gem_get_tiling *args = data;
771 struct drm_gem_object *gem;
775 gem = drm_gem_object_lookup(file, args->handle);
779 bo = to_tegra_bo(gem);
781 switch (bo->tiling.mode) {
782 case TEGRA_BO_TILING_MODE_PITCH:
783 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
787 case TEGRA_BO_TILING_MODE_TILED:
788 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
792 case TEGRA_BO_TILING_MODE_BLOCK:
793 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
794 args->value = bo->tiling.value;
802 drm_gem_object_unreference_unlocked(gem);
807 static int tegra_gem_set_flags(struct drm_device *drm, void *data,
808 struct drm_file *file)
810 struct drm_tegra_gem_set_flags *args = data;
811 struct drm_gem_object *gem;
814 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
817 gem = drm_gem_object_lookup(file, args->handle);
821 bo = to_tegra_bo(gem);
824 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
825 bo->flags |= TEGRA_BO_BOTTOM_UP;
827 drm_gem_object_unreference_unlocked(gem);
832 static int tegra_gem_get_flags(struct drm_device *drm, void *data,
833 struct drm_file *file)
835 struct drm_tegra_gem_get_flags *args = data;
836 struct drm_gem_object *gem;
839 gem = drm_gem_object_lookup(file, args->handle);
843 bo = to_tegra_bo(gem);
846 if (bo->flags & TEGRA_BO_BOTTOM_UP)
847 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
849 drm_gem_object_unreference_unlocked(gem);
855 static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
856 #ifdef CONFIG_DRM_TEGRA_STAGING
857 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0),
858 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0),
859 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0),
860 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0),
861 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0),
862 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0),
863 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0),
864 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0),
865 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0),
866 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0),
867 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0),
868 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0),
869 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0),
870 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0),
874 static const struct file_operations tegra_drm_fops = {
875 .owner = THIS_MODULE,
877 .release = drm_release,
878 .unlocked_ioctl = drm_ioctl,
879 .mmap = tegra_drm_mmap,
882 .compat_ioctl = drm_compat_ioctl,
883 .llseek = noop_llseek,
886 static int tegra_drm_context_cleanup(int id, void *p, void *data)
888 struct tegra_drm_context *context = p;
890 tegra_drm_context_free(context);
895 static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file)
897 struct tegra_drm_file *fpriv = file->driver_priv;
899 mutex_lock(&fpriv->lock);
900 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
901 mutex_unlock(&fpriv->lock);
903 idr_destroy(&fpriv->contexts);
904 mutex_destroy(&fpriv->lock);
908 #ifdef CONFIG_DEBUG_FS
909 static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
911 struct drm_info_node *node = (struct drm_info_node *)s->private;
912 struct drm_device *drm = node->minor->dev;
913 struct drm_framebuffer *fb;
915 mutex_lock(&drm->mode_config.fb_lock);
917 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
918 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
919 fb->base.id, fb->width, fb->height,
921 fb->format->cpp[0] * 8,
922 drm_framebuffer_read_refcount(fb));
925 mutex_unlock(&drm->mode_config.fb_lock);
930 static int tegra_debugfs_iova(struct seq_file *s, void *data)
932 struct drm_info_node *node = (struct drm_info_node *)s->private;
933 struct drm_device *drm = node->minor->dev;
934 struct tegra_drm *tegra = drm->dev_private;
935 struct drm_printer p = drm_seq_file_printer(s);
937 mutex_lock(&tegra->mm_lock);
938 drm_mm_print(&tegra->mm, &p);
939 mutex_unlock(&tegra->mm_lock);
944 static struct drm_info_list tegra_debugfs_list[] = {
945 { "framebuffers", tegra_debugfs_framebuffers, 0 },
946 { "iova", tegra_debugfs_iova, 0 },
949 static int tegra_debugfs_init(struct drm_minor *minor)
951 return drm_debugfs_create_files(tegra_debugfs_list,
952 ARRAY_SIZE(tegra_debugfs_list),
953 minor->debugfs_root, minor);
957 static struct drm_driver tegra_drm_driver = {
958 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
960 .load = tegra_drm_load,
961 .unload = tegra_drm_unload,
962 .open = tegra_drm_open,
963 .preclose = tegra_drm_preclose,
964 .lastclose = tegra_drm_lastclose,
966 #if defined(CONFIG_DEBUG_FS)
967 .debugfs_init = tegra_debugfs_init,
970 .gem_free_object_unlocked = tegra_bo_free_object,
971 .gem_vm_ops = &tegra_bo_vm_ops,
973 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
974 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
975 .gem_prime_export = tegra_gem_prime_export,
976 .gem_prime_import = tegra_gem_prime_import,
978 .dumb_create = tegra_bo_dumb_create,
979 .dumb_map_offset = tegra_bo_dumb_map_offset,
980 .dumb_destroy = drm_gem_dumb_destroy,
982 .ioctls = tegra_drm_ioctls,
983 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
984 .fops = &tegra_drm_fops,
989 .major = DRIVER_MAJOR,
990 .minor = DRIVER_MINOR,
991 .patchlevel = DRIVER_PATCHLEVEL,
994 int tegra_drm_register_client(struct tegra_drm *tegra,
995 struct tegra_drm_client *client)
997 mutex_lock(&tegra->clients_lock);
998 list_add_tail(&client->list, &tegra->clients);
999 mutex_unlock(&tegra->clients_lock);
1004 int tegra_drm_unregister_client(struct tegra_drm *tegra,
1005 struct tegra_drm_client *client)
1007 mutex_lock(&tegra->clients_lock);
1008 list_del_init(&client->list);
1009 mutex_unlock(&tegra->clients_lock);
1014 void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size,
1023 size = iova_align(&tegra->carveout.domain, size);
1025 size = PAGE_ALIGN(size);
1027 gfp = GFP_KERNEL | __GFP_ZERO;
1028 if (!tegra->domain) {
1030 * Many units only support 32-bit addresses, even on 64-bit
1031 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1032 * virtual address space, force allocations to be in the
1033 * lower 32-bit range.
1038 virt = (void *)__get_free_pages(gfp, get_order(size));
1040 return ERR_PTR(-ENOMEM);
1042 if (!tegra->domain) {
1044 * If IOMMU is disabled, devices address physical memory
1047 *dma = virt_to_phys(virt);
1051 alloc = alloc_iova(&tegra->carveout.domain,
1052 size >> tegra->carveout.shift,
1053 tegra->carveout.limit, true);
1059 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1060 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1061 size, IOMMU_READ | IOMMU_WRITE);
1068 __free_iova(&tegra->carveout.domain, alloc);
1070 free_pages((unsigned long)virt, get_order(size));
1072 return ERR_PTR(err);
1075 void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1079 size = iova_align(&tegra->carveout.domain, size);
1081 size = PAGE_ALIGN(size);
1083 if (tegra->domain) {
1084 iommu_unmap(tegra->domain, dma, size);
1085 free_iova(&tegra->carveout.domain,
1086 iova_pfn(&tegra->carveout.domain, dma));
1089 free_pages((unsigned long)virt, get_order(size));
1092 static int host1x_drm_probe(struct host1x_device *dev)
1094 struct drm_driver *driver = &tegra_drm_driver;
1095 struct drm_device *drm;
1098 drm = drm_dev_alloc(driver, &dev->dev);
1100 return PTR_ERR(drm);
1102 dev_set_drvdata(&dev->dev, drm);
1104 err = drm_dev_register(drm, 0);
1115 static int host1x_drm_remove(struct host1x_device *dev)
1117 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1119 drm_dev_unregister(drm);
1125 #ifdef CONFIG_PM_SLEEP
1126 static int host1x_drm_suspend(struct device *dev)
1128 struct drm_device *drm = dev_get_drvdata(dev);
1129 struct tegra_drm *tegra = drm->dev_private;
1131 drm_kms_helper_poll_disable(drm);
1132 tegra_drm_fb_suspend(drm);
1134 tegra->state = drm_atomic_helper_suspend(drm);
1135 if (IS_ERR(tegra->state)) {
1136 tegra_drm_fb_resume(drm);
1137 drm_kms_helper_poll_enable(drm);
1138 return PTR_ERR(tegra->state);
1144 static int host1x_drm_resume(struct device *dev)
1146 struct drm_device *drm = dev_get_drvdata(dev);
1147 struct tegra_drm *tegra = drm->dev_private;
1149 drm_atomic_helper_resume(drm, tegra->state);
1150 tegra_drm_fb_resume(drm);
1151 drm_kms_helper_poll_enable(drm);
1157 static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1160 static const struct of_device_id host1x_drm_subdevs[] = {
1161 { .compatible = "nvidia,tegra20-dc", },
1162 { .compatible = "nvidia,tegra20-hdmi", },
1163 { .compatible = "nvidia,tegra20-gr2d", },
1164 { .compatible = "nvidia,tegra20-gr3d", },
1165 { .compatible = "nvidia,tegra30-dc", },
1166 { .compatible = "nvidia,tegra30-hdmi", },
1167 { .compatible = "nvidia,tegra30-gr2d", },
1168 { .compatible = "nvidia,tegra30-gr3d", },
1169 { .compatible = "nvidia,tegra114-dsi", },
1170 { .compatible = "nvidia,tegra114-hdmi", },
1171 { .compatible = "nvidia,tegra114-gr3d", },
1172 { .compatible = "nvidia,tegra124-dc", },
1173 { .compatible = "nvidia,tegra124-sor", },
1174 { .compatible = "nvidia,tegra124-hdmi", },
1175 { .compatible = "nvidia,tegra124-dsi", },
1176 { .compatible = "nvidia,tegra124-vic", },
1177 { .compatible = "nvidia,tegra132-dsi", },
1178 { .compatible = "nvidia,tegra210-dc", },
1179 { .compatible = "nvidia,tegra210-dsi", },
1180 { .compatible = "nvidia,tegra210-sor", },
1181 { .compatible = "nvidia,tegra210-sor1", },
1182 { .compatible = "nvidia,tegra210-vic", },
1186 static struct host1x_driver host1x_drm_driver = {
1189 .pm = &host1x_drm_pm_ops,
1191 .probe = host1x_drm_probe,
1192 .remove = host1x_drm_remove,
1193 .subdevs = host1x_drm_subdevs,
1196 static struct platform_driver * const drivers[] = {
1200 &tegra_dpaux_driver,
1207 static int __init host1x_drm_init(void)
1211 err = host1x_driver_register(&host1x_drm_driver);
1215 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1217 goto unregister_host1x;
1222 host1x_driver_unregister(&host1x_drm_driver);
1225 module_init(host1x_drm_init);
1227 static void __exit host1x_drm_exit(void)
1229 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1230 host1x_driver_unregister(&host1x_drm_driver);
1232 module_exit(host1x_drm_exit);
1234 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1235 MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1236 MODULE_LICENSE("GPL v2");