2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
16 struct tegra_output output;
20 struct clk *clk_parent;
24 static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
26 return container_of(output, struct tegra_rgb, output);
34 static const struct reg_entry rgb_enable[] = {
35 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
36 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
37 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
38 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
40 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
41 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
43 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
44 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
51 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
52 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
53 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
56 static const struct reg_entry rgb_disable[] = {
57 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
58 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
59 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
60 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
64 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
65 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
66 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
67 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
68 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
69 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
70 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
71 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
72 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
73 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
74 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
75 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
78 static void tegra_dc_write_regs(struct tegra_dc *dc,
79 const struct reg_entry *table,
84 for (i = 0; i < num; i++)
85 tegra_dc_writel(dc, table[i].value, table[i].offset);
88 static int tegra_output_rgb_enable(struct tegra_output *output)
90 struct tegra_rgb *rgb = to_rgb(output);
96 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
98 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
99 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
101 /* XXX: parameterize? */
102 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
103 value &= ~LVS_OUTPUT_POLARITY_LOW;
104 value &= ~LHS_OUTPUT_POLARITY_LOW;
105 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
107 /* XXX: parameterize? */
108 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
110 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
112 /* XXX: parameterize? */
113 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
114 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
116 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND);
117 value &= ~DISP_CTRL_MODE_MASK;
118 value |= DISP_CTRL_MODE_C_DISPLAY;
119 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND);
121 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);
122 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
123 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
124 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
126 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
127 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
134 static int tegra_output_rgb_disable(struct tegra_output *output)
136 struct tegra_rgb *rgb = to_rgb(output);
142 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);
143 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
144 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
145 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
147 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND);
148 value &= ~DISP_CTRL_MODE_MASK;
149 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND);
151 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
152 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
154 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
156 rgb->enabled = false;
161 static int tegra_output_rgb_setup_clock(struct tegra_output *output,
162 struct clk *clk, unsigned long pclk)
164 struct tegra_rgb *rgb = to_rgb(output);
166 return clk_set_parent(clk, rgb->clk_parent);
169 static int tegra_output_rgb_check_mode(struct tegra_output *output,
170 struct drm_display_mode *mode,
171 enum drm_mode_status *status)
174 * FIXME: For now, always assume that the mode is okay. There are
175 * unresolved issues with clk_round_rate(), which doesn't always
176 * reliably report whether a frequency can be set or not.
184 static const struct tegra_output_ops rgb_ops = {
185 .enable = tegra_output_rgb_enable,
186 .disable = tegra_output_rgb_disable,
187 .setup_clock = tegra_output_rgb_setup_clock,
188 .check_mode = tegra_output_rgb_check_mode,
191 int tegra_dc_rgb_probe(struct tegra_dc *dc)
193 struct device_node *np;
194 struct tegra_rgb *rgb;
197 np = of_get_child_by_name(dc->dev->of_node, "rgb");
198 if (!np || !of_device_is_available(np))
201 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
205 rgb->output.dev = dc->dev;
206 rgb->output.of_node = np;
209 err = tegra_output_probe(&rgb->output);
213 rgb->clk = devm_clk_get(dc->dev, NULL);
214 if (IS_ERR(rgb->clk)) {
215 dev_err(dc->dev, "failed to get clock\n");
216 return PTR_ERR(rgb->clk);
219 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
220 if (IS_ERR(rgb->clk_parent)) {
221 dev_err(dc->dev, "failed to get parent clock\n");
222 return PTR_ERR(rgb->clk_parent);
225 err = clk_set_parent(rgb->clk, rgb->clk_parent);
227 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
231 dc->rgb = &rgb->output;
236 int tegra_dc_rgb_remove(struct tegra_dc *dc)
243 err = tegra_output_remove(dc->rgb);
250 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
252 struct tegra_rgb *rgb = to_rgb(dc->rgb);
258 rgb->output.type = TEGRA_OUTPUT_RGB;
259 rgb->output.ops = &rgb_ops;
261 err = tegra_output_init(dc->base.dev, &rgb->output);
263 dev_err(dc->dev, "output setup failed: %d\n", err);
268 * By default, outputs can be associated with each display controller.
269 * RGB outputs are an exception, so we make sure they can be attached
270 * to only their parent display controller.
272 rgb->output.encoder.possible_crtcs = drm_crtc_mask(&dc->base);
277 int tegra_dc_rgb_exit(struct tegra_dc *dc)
282 err = tegra_output_disable(dc->rgb);
284 dev_err(dc->dev, "output failed to disable: %d\n", err);
288 err = tegra_output_exit(dc->rgb);
290 dev_err(dc->dev, "output cleanup failed: %d\n", err);