2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 /* LCDC DRM driver, based on da8xx-fb */
20 #include <linux/component.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/suspend.h>
23 #include <drm/drm_atomic.h>
24 #include <drm/drm_atomic_helper.h>
26 #include "tilcdc_drv.h"
27 #include "tilcdc_regs.h"
28 #include "tilcdc_tfp410.h"
29 #include "tilcdc_panel.h"
30 #include "tilcdc_external.h"
32 #include "drm_fb_helper.h"
34 static LIST_HEAD(module_list);
36 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
38 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
40 DRM_FORMAT_XBGR8888 };
42 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
44 DRM_FORMAT_XRGB8888 };
46 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
48 DRM_FORMAT_XRGB8888 };
50 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
51 const struct tilcdc_module_ops *funcs)
55 INIT_LIST_HEAD(&mod->list);
56 list_add(&mod->list, &module_list);
59 void tilcdc_module_cleanup(struct tilcdc_module *mod)
64 static struct of_device_id tilcdc_of_match[];
66 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
67 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
69 return drm_fb_cma_create(dev, file_priv, mode_cmd);
72 static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
74 struct tilcdc_drm_private *priv = dev->dev_private;
75 drm_fbdev_cma_hotplug_event(priv->fbdev);
78 static int tilcdc_atomic_check(struct drm_device *dev,
79 struct drm_atomic_state *state)
83 ret = drm_atomic_helper_check_modeset(dev, state);
87 ret = drm_atomic_helper_check_planes(dev, state);
92 * tilcdc ->atomic_check can update ->mode_changed if pixel format
93 * changes, hence will we check modeset changes again.
95 ret = drm_atomic_helper_check_modeset(dev, state);
102 static int tilcdc_commit(struct drm_device *dev,
103 struct drm_atomic_state *state,
108 ret = drm_atomic_helper_prepare_planes(dev, state);
112 drm_atomic_helper_swap_state(state, true);
115 * Everything below can be run asynchronously without the need to grab
116 * any modeset locks at all under one condition: It must be guaranteed
117 * that the asynchronous work has either been cancelled (if the driver
118 * supports it, which at least requires that the framebuffers get
119 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
120 * before the new state gets committed on the software side with
121 * drm_atomic_helper_swap_state().
123 * This scheme allows new atomic state updates to be prepared and
124 * checked in parallel to the asynchronous completion of the previous
125 * update. Which is important since compositors need to figure out the
126 * composition of the next frame right after having submitted the
130 drm_atomic_helper_commit_modeset_disables(dev, state);
132 drm_atomic_helper_commit_planes(dev, state, 0);
134 drm_atomic_helper_commit_modeset_enables(dev, state);
136 drm_atomic_helper_wait_for_vblanks(dev, state);
138 drm_atomic_helper_cleanup_planes(dev, state);
143 static const struct drm_mode_config_funcs mode_config_funcs = {
144 .fb_create = tilcdc_fb_create,
145 .output_poll_changed = tilcdc_fb_output_poll_changed,
146 .atomic_check = tilcdc_atomic_check,
147 .atomic_commit = tilcdc_commit,
150 static void modeset_init(struct drm_device *dev)
152 struct tilcdc_drm_private *priv = dev->dev_private;
153 struct tilcdc_module *mod;
155 list_for_each_entry(mod, &module_list, list) {
156 DBG("loading module: %s", mod->name);
157 mod->funcs->modeset_init(mod, dev);
160 dev->mode_config.min_width = 0;
161 dev->mode_config.min_height = 0;
162 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
163 dev->mode_config.max_height = 2048;
164 dev->mode_config.funcs = &mode_config_funcs;
167 #ifdef CONFIG_CPU_FREQ
168 static int cpufreq_transition(struct notifier_block *nb,
169 unsigned long val, void *data)
171 struct tilcdc_drm_private *priv = container_of(nb,
172 struct tilcdc_drm_private, freq_transition);
174 if (val == CPUFREQ_POSTCHANGE)
175 tilcdc_crtc_update_clk(priv->crtc);
185 static void tilcdc_fini(struct drm_device *dev)
187 struct tilcdc_drm_private *priv = dev->dev_private;
190 tilcdc_crtc_shutdown(priv->crtc);
192 if (priv->is_registered)
193 drm_dev_unregister(dev);
195 drm_kms_helper_poll_fini(dev);
198 drm_fbdev_cma_fini(priv->fbdev);
200 drm_irq_uninstall(dev);
201 drm_mode_config_cleanup(dev);
202 tilcdc_remove_external_device(dev);
204 #ifdef CONFIG_CPU_FREQ
205 if (priv->freq_transition.notifier_call)
206 cpufreq_unregister_notifier(&priv->freq_transition,
207 CPUFREQ_TRANSITION_NOTIFIER);
217 flush_workqueue(priv->wq);
218 destroy_workqueue(priv->wq);
221 dev->dev_private = NULL;
223 pm_runtime_disable(dev->dev);
228 static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
230 struct drm_device *ddev;
231 struct platform_device *pdev = to_platform_device(dev);
232 struct device_node *node = dev->of_node;
233 struct tilcdc_drm_private *priv;
234 struct resource *res;
238 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
240 dev_err(dev, "failed to allocate private data\n");
244 ddev = drm_dev_alloc(ddrv, dev);
246 return PTR_ERR(ddev);
248 ddev->platformdev = pdev;
249 ddev->dev_private = priv;
250 platform_set_drvdata(pdev, ddev);
251 drm_mode_config_init(ddev);
253 priv->is_componentized =
254 tilcdc_get_external_components(dev, NULL) > 0;
256 priv->wq = alloc_ordered_workqueue("tilcdc", 0);
262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
264 dev_err(dev, "failed to get memory resource\n");
269 priv->mmio = ioremap_nocache(res->start, resource_size(res));
271 dev_err(dev, "failed to ioremap\n");
276 priv->clk = clk_get(dev, "fck");
277 if (IS_ERR(priv->clk)) {
278 dev_err(dev, "failed to get functional clock\n");
283 #ifdef CONFIG_CPU_FREQ
284 priv->freq_transition.notifier_call = cpufreq_transition;
285 ret = cpufreq_register_notifier(&priv->freq_transition,
286 CPUFREQ_TRANSITION_NOTIFIER);
288 dev_err(dev, "failed to register cpufreq notifier\n");
289 priv->freq_transition.notifier_call = NULL;
294 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
295 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
297 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
299 if (of_property_read_u32(node, "max-width", &priv->max_width))
300 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
302 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
304 if (of_property_read_u32(node, "max-pixelclock",
305 &priv->max_pixelclock))
306 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
308 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
310 pm_runtime_enable(dev);
312 /* Determine LCD IP Version */
313 pm_runtime_get_sync(dev);
314 switch (tilcdc_read(ddev, LCDC_PID_REG)) {
323 dev_warn(dev, "Unknown PID Reg value 0x%08x, "
324 "defaulting to LCD revision 1\n",
325 tilcdc_read(ddev, LCDC_PID_REG));
330 pm_runtime_put_sync(dev);
332 if (priv->rev == 1) {
333 DBG("Revision 1 LCDC supports only RGB565 format");
334 priv->pixelformats = tilcdc_rev1_formats;
335 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
338 const char *str = "\0";
340 of_property_read_string(node, "blue-and-red-wiring", &str);
341 if (0 == strcmp(str, "crossed")) {
342 DBG("Configured for crossed blue and red wires");
343 priv->pixelformats = tilcdc_crossed_formats;
344 priv->num_pixelformats =
345 ARRAY_SIZE(tilcdc_crossed_formats);
346 bpp = 32; /* Choose bpp with RGB support for fbdef */
347 } else if (0 == strcmp(str, "straight")) {
348 DBG("Configured for straight blue and red wires");
349 priv->pixelformats = tilcdc_straight_formats;
350 priv->num_pixelformats =
351 ARRAY_SIZE(tilcdc_straight_formats);
352 bpp = 16; /* Choose bpp with RGB support for fbdef */
354 DBG("Blue and red wiring '%s' unknown, use legacy mode",
356 priv->pixelformats = tilcdc_legacy_formats;
357 priv->num_pixelformats =
358 ARRAY_SIZE(tilcdc_legacy_formats);
359 bpp = 16; /* This is just a guess */
363 ret = tilcdc_crtc_create(ddev);
365 dev_err(dev, "failed to create crtc\n");
370 if (priv->is_componentized) {
371 ret = component_bind_all(dev, ddev);
375 ret = tilcdc_add_component_encoder(ddev);
379 ret = tilcdc_attach_external_device(ddev);
384 if (!priv->external_connector &&
385 ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
386 dev_err(dev, "no encoders/connectors found\n");
391 ret = drm_vblank_init(ddev, 1);
393 dev_err(dev, "failed to initialize vblank\n");
397 ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
399 dev_err(dev, "failed to install IRQ handler\n");
403 drm_mode_config_reset(ddev);
405 priv->fbdev = drm_fbdev_cma_init(ddev, bpp,
406 ddev->mode_config.num_connector);
407 if (IS_ERR(priv->fbdev)) {
408 ret = PTR_ERR(priv->fbdev);
412 drm_kms_helper_poll_init(ddev);
414 ret = drm_dev_register(ddev, 0);
418 priv->is_registered = true;
427 static void tilcdc_lastclose(struct drm_device *dev)
429 struct tilcdc_drm_private *priv = dev->dev_private;
430 drm_fbdev_cma_restore_mode(priv->fbdev);
433 static irqreturn_t tilcdc_irq(int irq, void *arg)
435 struct drm_device *dev = arg;
436 struct tilcdc_drm_private *priv = dev->dev_private;
437 return tilcdc_crtc_irq(priv->crtc);
440 static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
445 static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
450 #if defined(CONFIG_DEBUG_FS)
451 static const struct {
457 #define REG(rev, save, reg) { #reg, rev, save, reg }
458 /* exists in revision 1: */
459 REG(1, false, LCDC_PID_REG),
460 REG(1, true, LCDC_CTRL_REG),
461 REG(1, false, LCDC_STAT_REG),
462 REG(1, true, LCDC_RASTER_CTRL_REG),
463 REG(1, true, LCDC_RASTER_TIMING_0_REG),
464 REG(1, true, LCDC_RASTER_TIMING_1_REG),
465 REG(1, true, LCDC_RASTER_TIMING_2_REG),
466 REG(1, true, LCDC_DMA_CTRL_REG),
467 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
468 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
469 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
470 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
471 /* new in revision 2: */
472 REG(2, false, LCDC_RAW_STAT_REG),
473 REG(2, false, LCDC_MASKED_STAT_REG),
474 REG(2, true, LCDC_INT_ENABLE_SET_REG),
475 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
476 REG(2, false, LCDC_END_OF_INT_IND_REG),
477 REG(2, true, LCDC_CLK_ENABLE_REG),
483 #ifdef CONFIG_DEBUG_FS
484 static int tilcdc_regs_show(struct seq_file *m, void *arg)
486 struct drm_info_node *node = (struct drm_info_node *) m->private;
487 struct drm_device *dev = node->minor->dev;
488 struct tilcdc_drm_private *priv = dev->dev_private;
491 pm_runtime_get_sync(dev->dev);
493 seq_printf(m, "revision: %d\n", priv->rev);
495 for (i = 0; i < ARRAY_SIZE(registers); i++)
496 if (priv->rev >= registers[i].rev)
497 seq_printf(m, "%s:\t %08x\n", registers[i].name,
498 tilcdc_read(dev, registers[i].reg));
500 pm_runtime_put_sync(dev->dev);
505 static int tilcdc_mm_show(struct seq_file *m, void *arg)
507 struct drm_info_node *node = (struct drm_info_node *) m->private;
508 struct drm_device *dev = node->minor->dev;
509 struct drm_printer p = drm_seq_file_printer(m);
510 drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
514 static struct drm_info_list tilcdc_debugfs_list[] = {
515 { "regs", tilcdc_regs_show, 0 },
516 { "mm", tilcdc_mm_show, 0 },
517 { "fb", drm_fb_cma_debugfs_show, 0 },
520 static int tilcdc_debugfs_init(struct drm_minor *minor)
522 struct drm_device *dev = minor->dev;
523 struct tilcdc_module *mod;
526 ret = drm_debugfs_create_files(tilcdc_debugfs_list,
527 ARRAY_SIZE(tilcdc_debugfs_list),
528 minor->debugfs_root, minor);
530 list_for_each_entry(mod, &module_list, list)
531 if (mod->funcs->debugfs_init)
532 mod->funcs->debugfs_init(mod, minor);
535 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
543 static const struct file_operations fops = {
544 .owner = THIS_MODULE,
546 .release = drm_release,
547 .unlocked_ioctl = drm_ioctl,
548 .compat_ioctl = drm_compat_ioctl,
552 .mmap = drm_gem_cma_mmap,
555 static struct drm_driver tilcdc_driver = {
556 .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
557 DRIVER_PRIME | DRIVER_ATOMIC),
558 .lastclose = tilcdc_lastclose,
559 .irq_handler = tilcdc_irq,
560 .get_vblank_counter = drm_vblank_no_hw_counter,
561 .enable_vblank = tilcdc_enable_vblank,
562 .disable_vblank = tilcdc_disable_vblank,
563 .gem_free_object_unlocked = drm_gem_cma_free_object,
564 .gem_vm_ops = &drm_gem_cma_vm_ops,
565 .dumb_create = drm_gem_cma_dumb_create,
566 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
567 .dumb_destroy = drm_gem_dumb_destroy,
569 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
570 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
571 .gem_prime_import = drm_gem_prime_import,
572 .gem_prime_export = drm_gem_prime_export,
573 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
574 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
575 .gem_prime_vmap = drm_gem_cma_prime_vmap,
576 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
577 .gem_prime_mmap = drm_gem_cma_prime_mmap,
578 #ifdef CONFIG_DEBUG_FS
579 .debugfs_init = tilcdc_debugfs_init,
583 .desc = "TI LCD Controller DRM",
593 #ifdef CONFIG_PM_SLEEP
594 static int tilcdc_pm_suspend(struct device *dev)
596 struct drm_device *ddev = dev_get_drvdata(dev);
597 struct tilcdc_drm_private *priv = ddev->dev_private;
599 priv->saved_state = drm_atomic_helper_suspend(ddev);
601 /* Select sleep pin state */
602 pinctrl_pm_select_sleep_state(dev);
607 static int tilcdc_pm_resume(struct device *dev)
609 struct drm_device *ddev = dev_get_drvdata(dev);
610 struct tilcdc_drm_private *priv = ddev->dev_private;
613 /* Select default pin state */
614 pinctrl_pm_select_default_state(dev);
616 if (priv->saved_state)
617 ret = drm_atomic_helper_resume(ddev, priv->saved_state);
623 static const struct dev_pm_ops tilcdc_pm_ops = {
624 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
630 static int tilcdc_bind(struct device *dev)
632 return tilcdc_init(&tilcdc_driver, dev);
635 static void tilcdc_unbind(struct device *dev)
637 struct drm_device *ddev = dev_get_drvdata(dev);
639 /* Check if a subcomponent has already triggered the unloading. */
640 if (!ddev->dev_private)
643 tilcdc_fini(dev_get_drvdata(dev));
646 static const struct component_master_ops tilcdc_comp_ops = {
648 .unbind = tilcdc_unbind,
651 static int tilcdc_pdev_probe(struct platform_device *pdev)
653 struct component_match *match = NULL;
656 /* bail out early if no DT data: */
657 if (!pdev->dev.of_node) {
658 dev_err(&pdev->dev, "device-tree data is missing\n");
662 ret = tilcdc_get_external_components(&pdev->dev, &match);
666 return tilcdc_init(&tilcdc_driver, &pdev->dev);
668 return component_master_add_with_match(&pdev->dev,
673 static int tilcdc_pdev_remove(struct platform_device *pdev)
677 ret = tilcdc_get_external_components(&pdev->dev, NULL);
681 tilcdc_fini(platform_get_drvdata(pdev));
683 component_master_del(&pdev->dev, &tilcdc_comp_ops);
688 static struct of_device_id tilcdc_of_match[] = {
689 { .compatible = "ti,am33xx-tilcdc", },
690 { .compatible = "ti,da850-tilcdc", },
693 MODULE_DEVICE_TABLE(of, tilcdc_of_match);
695 static struct platform_driver tilcdc_platform_driver = {
696 .probe = tilcdc_pdev_probe,
697 .remove = tilcdc_pdev_remove,
700 .pm = &tilcdc_pm_ops,
701 .of_match_table = tilcdc_of_match,
705 static int __init tilcdc_drm_init(void)
708 tilcdc_tfp410_init();
710 return platform_driver_register(&tilcdc_platform_driver);
713 static void __exit tilcdc_drm_fini(void)
716 platform_driver_unregister(&tilcdc_platform_driver);
718 tilcdc_tfp410_fini();
721 module_init(tilcdc_drm_init);
722 module_exit(tilcdc_drm_fini);
724 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
725 MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
726 MODULE_LICENSE("GPL");