drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * output's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, this file also manages
  19  * setup of the VC4 HVS's display elements on the CRTC.
  20  *
  21  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  22  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  23  * image domain can feed either HDMI or the SDTV controller.  The
  24  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  25  * SDTV, etc.) according to which output type is chosen in the mux.
  26  *
  27  * For power management, the pixel valve's registers are all clocked
  28  * by the AXI clock, while the timings and FIFOs make use of the
  29  * output-specific clock.  Since the encoders also directly consume
  30  * the CPRMAN clocks, and know what timings they need, they are the
  31  * ones that set the clock.
  32  */
  33
  34 #include "drm_atomic.h"
  35 #include "drm_atomic_helper.h"
  36 #include "drm_crtc_helper.h"
  37 #include "linux/clk.h"
  38 #include "drm_fb_cma_helper.h"
  39 #include "linux/component.h"
  40 #include "linux/of_device.h"
  41 #include "vc4_drv.h"
  42 #include "vc4_regs.h"
  43
  44 struct vc4_crtc {
  45         struct drm_crtc base;
  46         const struct vc4_crtc_data *data;
  47         void __iomem *regs;
  48
  49         /* Timestamp at start of vblank irq - unaffected by lock delays. */
  50         ktime_t t_vblank;
  51
  52         /* Which HVS channel we're using for our CRTC. */
  53         int channel;
  54
  55         u8 lut_r[256];
  56         u8 lut_g[256];
  57         u8 lut_b[256];
  58         /* Size in pixels of the COB memory allocated to this CRTC. */
  59         u32 cob_size;
  60
  61         struct drm_pending_vblank_event *event;
  62 };
  63
  64 struct vc4_crtc_state {
  65         struct drm_crtc_state base;
  66         /* Dlist area for this CRTC configuration. */
  67         struct drm_mm_node mm;
  68 };
  69
  70 static inline struct vc4_crtc *
  71 to_vc4_crtc(struct drm_crtc *crtc)
  72 {
  73         return (struct vc4_crtc *)crtc;
  74 }
  75
  76 static inline struct vc4_crtc_state *
  77 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  78 {
  79         return (struct vc4_crtc_state *)crtc_state;
  80 }
  81
  82 struct vc4_crtc_data {
  83         /* Which channel of the HVS this pixelvalve sources from. */
  84         int hvs_channel;
  85
  86         enum vc4_encoder_type encoder_types[4];
  87 };
  88
  89 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  90 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  91
  92 #define CRTC_REG(reg) { reg, #reg }
  93 static const struct {
  94         u32 reg;
  95         const char *name;
  96 } crtc_regs[] = {
  97         CRTC_REG(PV_CONTROL),
  98         CRTC_REG(PV_V_CONTROL),
  99         CRTC_REG(PV_VSYNCD_EVEN),
 100         CRTC_REG(PV_HORZA),
 101         CRTC_REG(PV_HORZB),
 102         CRTC_REG(PV_VERTA),
 103         CRTC_REG(PV_VERTB),
 104         CRTC_REG(PV_VERTA_EVEN),
 105         CRTC_REG(PV_VERTB_EVEN),
 106         CRTC_REG(PV_INTEN),
 107         CRTC_REG(PV_INTSTAT),
 108         CRTC_REG(PV_STAT),
 109         CRTC_REG(PV_HACT_ACT),
 110 };
 111
 112 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
 113 {
 114         int i;
 115
 116         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 117                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 118                          crtc_regs[i].reg, crtc_regs[i].name,
 119                          CRTC_READ(crtc_regs[i].reg));
 120         }
 121 }
 122
 123 #ifdef CONFIG_DEBUG_FS
 124 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 125 {
 126         struct drm_info_node *node = (struct drm_info_node *)m->private;
 127         struct drm_device *dev = node->minor->dev;
 128         int crtc_index = (uintptr_t)node->info_ent->data;
 129         struct drm_crtc *crtc;
 130         struct vc4_crtc *vc4_crtc;
 131         int i;
 132
 133         i = 0;
 134         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 135                 if (i == crtc_index)
 136                         break;
 137                 i++;
 138         }
 139         if (!crtc)
 140                 return 0;
 141         vc4_crtc = to_vc4_crtc(crtc);
 142
 143         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 144                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 145                            crtc_regs[i].name, crtc_regs[i].reg,
 146                            CRTC_READ(crtc_regs[i].reg));
 147         }
 148
 149         return 0;
 150 }
 151 #endif
 152
 153 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 154                             unsigned int flags, int *vpos, int *hpos,
 155                             ktime_t *stime, ktime_t *etime,
 156                             const struct drm_display_mode *mode)
 157 {
 158         struct vc4_dev *vc4 = to_vc4_dev(dev);
 159         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 160         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 161         u32 val;
 162         int fifo_lines;
 163         int vblank_lines;
 164         int ret = 0;
 165
 166         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 167
 168         /* Get optional system timestamp before query. */
 169         if (stime)
 170                 *stime = ktime_get();
 171
 172         /*
 173          * Read vertical scanline which is currently composed for our
 174          * pixelvalve by the HVS, and also the scaler status.
 175          */
 176         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 177
 178         /* Get optional system timestamp after query. */
 179         if (etime)
 180                 *etime = ktime_get();
 181
 182         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 183
 184         /* Vertical position of hvs composed scanline. */
 185         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 186         *hpos = 0;
 187
 188         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 189                 *vpos /= 2;
 190
 191                 /* Use hpos to correct for field offset in interlaced mode. */
 192                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 193                         *hpos += mode->crtc_htotal / 2;
 194         }
 195
 196         /* This is the offset we need for translating hvs -> pv scanout pos. */
 197         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 198
 199         if (fifo_lines > 0)
 200                 ret |= DRM_SCANOUTPOS_VALID;
 201
 202         /* HVS more than fifo_lines into frame for compositing? */
 203         if (*vpos > fifo_lines) {
 204                 /*
 205                  * We are in active scanout and can get some meaningful results
 206                  * from HVS. The actual PV scanout can not trail behind more
 207                  * than fifo_lines as that is the fifo's capacity. Assume that
 208                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 209                  * refilling the fifo and PV consuming from the fifo, ie.
 210                  * whenever the PV consumes and frees up a scanline in the
 211                  * fifo, the HVS will immediately refill it, therefore
 212                  * incrementing vpos. Therefore we choose HVS read position -
 213                  * fifo size in scanlines as a estimate of the real scanout
 214                  * position of the PV.
 215                  */
 216                 *vpos -= fifo_lines + 1;
 217
 218                 ret |= DRM_SCANOUTPOS_ACCURATE;
 219                 return ret;
 220         }
 221
 222         /*
 223          * Less: This happens when we are in vblank and the HVS, after getting
 224          * the VSTART restart signal from the PV, just started refilling its
 225          * fifo with new lines from the top-most lines of the new framebuffers.
 226          * The PV does not scan out in vblank, so does not remove lines from
 227          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 228          * We can't get meaningful readings wrt. scanline position of the PV
 229          * and need to make things up in a approximative but consistent way.
 230          */
 231         ret |= DRM_SCANOUTPOS_IN_VBLANK;
 232         vblank_lines = mode->vtotal - mode->vdisplay;
 233
 234         if (flags & DRM_CALLED_FROM_VBLIRQ) {
 235                 /*
 236                  * Assume the irq handler got called close to first
 237                  * line of vblank, so PV has about a full vblank
 238                  * scanlines to go, and as a base timestamp use the
 239                  * one taken at entry into vblank irq handler, so it
 240                  * is not affected by random delays due to lock
 241                  * contention on event_lock or vblank_time lock in
 242                  * the core.
 243                  */
 244                 *vpos = -vblank_lines;
 245
 246                 if (stime)
 247                         *stime = vc4_crtc->t_vblank;
 248                 if (etime)
 249                         *etime = vc4_crtc->t_vblank;
 250
 251                 /*
 252                  * If the HVS fifo is not yet full then we know for certain
 253                  * we are at the very beginning of vblank, as the hvs just
 254                  * started refilling, and the stime and etime timestamps
 255                  * truly correspond to start of vblank.
 256                  */
 257                 if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL)
 258                         ret |= DRM_SCANOUTPOS_ACCURATE;
 259         } else {
 260                 /*
 261                  * No clue where we are inside vblank. Return a vpos of zero,
 262                  * which will cause calling code to just return the etime
 263                  * timestamp uncorrected. At least this is no worse than the
 264                  * standard fallback.
 265                  */
 266                 *vpos = 0;
 267         }
 268
 269         return ret;
 270 }
 271
 272 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
 273                                   int *max_error, struct timeval *vblank_time,
 274                                   unsigned flags)
 275 {
 276         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 277         struct drm_crtc_state *state = crtc->state;
 278
 279         /* Helper routine in DRM core does all the work: */
 280         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error,
 281                                                      vblank_time, flags,
 282                                                      &state->adjusted_mode);
 283 }
 284
 285 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 286 {
 287         drm_crtc_cleanup(crtc);
 288 }
 289
 290 static void
 291 vc4_crtc_lut_load(struct drm_crtc *crtc)
 292 {
 293         struct drm_device *dev = crtc->dev;
 294         struct vc4_dev *vc4 = to_vc4_dev(dev);
 295         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 296         u32 i;
 297
 298         /* The LUT memory is laid out with each HVS channel in order,
 299          * each of which takes 256 writes for R, 256 for G, then 256
 300          * for B.
 301          */
 302         HVS_WRITE(SCALER_GAMADDR,
 303                   SCALER_GAMADDR_AUTOINC |
 304                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 305
 306         for (i = 0; i < crtc->gamma_size; i++)
 307                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 308         for (i = 0; i < crtc->gamma_size; i++)
 309                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 310         for (i = 0; i < crtc->gamma_size; i++)
 311                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 312 }
 313
 314 static int
 315 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 316                    uint32_t size)
 317 {
 318         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 319         u32 i;
 320
 321         for (i = 0; i < size; i++) {
 322                 vc4_crtc->lut_r[i] = r[i] >> 8;
 323                 vc4_crtc->lut_g[i] = g[i] >> 8;
 324                 vc4_crtc->lut_b[i] = b[i] >> 8;
 325         }
 326
 327         vc4_crtc_lut_load(crtc);
 328
 329         return 0;
 330 }
 331
 332 static u32 vc4_get_fifo_full_level(u32 format)
 333 {
 334         static const u32 fifo_len_bytes = 64;
 335         static const u32 hvs_latency_pix = 6;
 336
 337         switch (format) {
 338         case PV_CONTROL_FORMAT_DSIV_16:
 339         case PV_CONTROL_FORMAT_DSIC_16:
 340                 return fifo_len_bytes - 2 * hvs_latency_pix;
 341         case PV_CONTROL_FORMAT_DSIV_18:
 342                 return fifo_len_bytes - 14;
 343         case PV_CONTROL_FORMAT_24:
 344         case PV_CONTROL_FORMAT_DSIV_24:
 345         default:
 346                 return fifo_len_bytes - 3 * hvs_latency_pix;
 347         }
 348 }
 349
 350 /*
 351  * Returns the encoder attached to the CRTC.
 352  *
 353  * VC4 can only scan out to one encoder at a time, while the DRM core
 354  * allows drivers to push pixels to more than one encoder from the
 355  * same CRTC.
 356  */
 357 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 358 {
 359         struct drm_connector *connector;
 360
 361         drm_for_each_connector(connector, crtc->dev) {
 362                 if (connector->state->crtc == crtc) {
 363                         return connector->encoder;
 364                 }
 365         }
 366
 367         return NULL;
 368 }
 369
 370 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 371 {
 372         struct drm_device *dev = crtc->dev;
 373         struct vc4_dev *vc4 = to_vc4_dev(dev);
 374         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 375         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 376         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 377         struct drm_crtc_state *state = crtc->state;
 378         struct drm_display_mode *mode = &state->adjusted_mode;
 379         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 380         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 381         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 382                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 383         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 384         bool debug_dump_regs = false;
 385
 386         if (debug_dump_regs) {
 387                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 388                 vc4_crtc_dump_regs(vc4_crtc);
 389         }
 390
 391         /* Reset the PV fifo. */
 392         CRTC_WRITE(PV_CONTROL, 0);
 393         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 394         CRTC_WRITE(PV_CONTROL, 0);
 395
 396         CRTC_WRITE(PV_HORZA,
 397                    VC4_SET_FIELD((mode->htotal -
 398                                   mode->hsync_end) * pixel_rep,
 399                                  PV_HORZA_HBP) |
 400                    VC4_SET_FIELD((mode->hsync_end -
 401                                   mode->hsync_start) * pixel_rep,
 402                                  PV_HORZA_HSYNC));
 403         CRTC_WRITE(PV_HORZB,
 404                    VC4_SET_FIELD((mode->hsync_start -
 405                                   mode->hdisplay) * pixel_rep,
 406                                  PV_HORZB_HFP) |
 407                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 408
 409         CRTC_WRITE(PV_VERTA,
 410                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 411                                  PV_VERTA_VBP) |
 412                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 413                                  PV_VERTA_VSYNC));
 414         CRTC_WRITE(PV_VERTB,
 415                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 416                                  PV_VERTB_VFP) |
 417                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 418
 419         if (interlace) {
 420                 CRTC_WRITE(PV_VERTA_EVEN,
 421                            VC4_SET_FIELD(mode->crtc_vtotal -
 422                                          mode->crtc_vsync_end - 1,
 423                                          PV_VERTA_VBP) |
 424                            VC4_SET_FIELD(mode->crtc_vsync_end -
 425                                          mode->crtc_vsync_start,
 426                                          PV_VERTA_VSYNC));
 427                 CRTC_WRITE(PV_VERTB_EVEN,
 428                            VC4_SET_FIELD(mode->crtc_vsync_start -
 429                                          mode->crtc_vdisplay,
 430                                          PV_VERTB_VFP) |
 431                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 432
 433                 /* We set up first field even mode for HDMI.  VEC's
 434                  * NTSC mode would want first field odd instead, once
 435                  * we support it (to do so, set ODD_FIRST and put the
 436                  * delay in VSYNCD_EVEN instead).
 437                  */
 438                 CRTC_WRITE(PV_V_CONTROL,
 439                            PV_VCONTROL_CONTINUOUS |
 440                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 441                            PV_VCONTROL_INTERLACE |
 442                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 443                                          PV_VCONTROL_ODD_DELAY));
 444                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 445         } else {
 446                 CRTC_WRITE(PV_V_CONTROL,
 447                            PV_VCONTROL_CONTINUOUS |
 448                            (is_dsi ? PV_VCONTROL_DSI : 0));
 449         }
 450
 451         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 452
 453         CRTC_WRITE(PV_CONTROL,
 454                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 455                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 456                                  PV_CONTROL_FIFO_LEVEL) |
 457                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 458                    PV_CONTROL_CLR_AT_START |
 459                    PV_CONTROL_TRIGGER_UNDERFLOW |
 460                    PV_CONTROL_WAIT_HSTART |
 461                    VC4_SET_FIELD(vc4_encoder->clock_select,
 462                                  PV_CONTROL_CLK_SELECT) |
 463                    PV_CONTROL_FIFO_CLR |
 464                    PV_CONTROL_EN);
 465
 466         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 467                   SCALER_DISPBKGND_AUTOHS |
 468                   SCALER_DISPBKGND_GAMMA |
 469                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 470
 471         /* Reload the LUT, since the SRAMs would have been disabled if
 472          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 473          */
 474         vc4_crtc_lut_load(crtc);
 475
 476         if (debug_dump_regs) {
 477                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 478                 vc4_crtc_dump_regs(vc4_crtc);
 479         }
 480 }
 481
 482 static void require_hvs_enabled(struct drm_device *dev)
 483 {
 484         struct vc4_dev *vc4 = to_vc4_dev(dev);
 485
 486         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 487                      SCALER_DISPCTRL_ENABLE);
 488 }
 489
 490 static void vc4_crtc_disable(struct drm_crtc *crtc)
 491 {
 492         struct drm_device *dev = crtc->dev;
 493         struct vc4_dev *vc4 = to_vc4_dev(dev);
 494         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 495         u32 chan = vc4_crtc->channel;
 496         int ret;
 497         require_hvs_enabled(dev);
 498
 499         /* Disable vblank irq handling before crtc is disabled. */
 500         drm_crtc_vblank_off(crtc);
 501
 502         CRTC_WRITE(PV_V_CONTROL,
 503                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 504         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 505         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 506
 507         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 508             SCALER_DISPCTRLX_ENABLE) {
 509                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 510                           SCALER_DISPCTRLX_RESET);
 511
 512                 /* While the docs say that reset is self-clearing, it
 513                  * seems it doesn't actually.
 514                  */
 515                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 516         }
 517
 518         /* Once we leave, the scaler should be disabled and its fifo empty. */
 519
 520         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 521
 522         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 523                                    SCALER_DISPSTATX_MODE) !=
 524                      SCALER_DISPSTATX_MODE_DISABLED);
 525
 526         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 527                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 528                      SCALER_DISPSTATX_EMPTY);
 529 }
 530
 531 static void vc4_crtc_enable(struct drm_crtc *crtc)
 532 {
 533         struct drm_device *dev = crtc->dev;
 534         struct vc4_dev *vc4 = to_vc4_dev(dev);
 535         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 536         struct drm_crtc_state *state = crtc->state;
 537         struct drm_display_mode *mode = &state->adjusted_mode;
 538
 539         require_hvs_enabled(dev);
 540
 541         /* Turn on the scaler, which will wait for vstart to start
 542          * compositing.
 543          */
 544         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 545                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 546                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 547                   SCALER_DISPCTRLX_ENABLE);
 548
 549         /* Turn on the pixel valve, which will emit the vstart signal. */
 550         CRTC_WRITE(PV_V_CONTROL,
 551                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 552
 553         /* Enable vblank irq handling after crtc is started. */
 554         drm_crtc_vblank_on(crtc);
 555 }
 556
 557 static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
 558                                 const struct drm_display_mode *mode,
 559                                 struct drm_display_mode *adjusted_mode)
 560 {
 561         /* Do not allow doublescan modes from user space */
 562         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 563                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 564                               crtc->base.id);
 565                 return false;
 566         }
 567
 568         return true;
 569 }
 570
 571 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 572                                  struct drm_crtc_state *state)
 573 {
 574         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 575         struct drm_device *dev = crtc->dev;
 576         struct vc4_dev *vc4 = to_vc4_dev(dev);
 577         struct drm_plane *plane;
 578         unsigned long flags;
 579         const struct drm_plane_state *plane_state;
 580         u32 dlist_count = 0;
 581         int ret;
 582
 583         /* The pixelvalve can only feed one encoder (and encoders are
 584          * 1:1 with connectors.)
 585          */
 586         if (hweight32(state->connector_mask) > 1)
 587                 return -EINVAL;
 588
 589         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 590                 dlist_count += vc4_plane_dlist_size(plane_state);
 591
 592         dlist_count++; /* Account for SCALER_CTL0_END. */
 593
 594         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 595         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 596                                  dlist_count);
 597         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 598         if (ret)
 599                 return ret;
 600
 601         return 0;
 602 }
 603
 604 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 605                                   struct drm_crtc_state *old_state)
 606 {
 607         struct drm_device *dev = crtc->dev;
 608         struct vc4_dev *vc4 = to_vc4_dev(dev);
 609         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 610         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 611         struct drm_plane *plane;
 612         bool debug_dump_regs = false;
 613         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 614         u32 __iomem *dlist_next = dlist_start;
 615
 616         if (debug_dump_regs) {
 617                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 618                 vc4_hvs_dump_state(dev);
 619         }
 620
 621         /* Copy all the active planes' dlist contents to the hardware dlist. */
 622         drm_atomic_crtc_for_each_plane(plane, crtc) {
 623                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 624         }
 625
 626         writel(SCALER_CTL0_END, dlist_next);
 627         dlist_next++;
 628
 629         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 630
 631         if (crtc->state->event) {
 632                 unsigned long flags;
 633
 634                 crtc->state->event->pipe = drm_crtc_index(crtc);
 635
 636                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 637
 638                 spin_lock_irqsave(&dev->event_lock, flags);
 639                 vc4_crtc->event = crtc->state->event;
 640                 crtc->state->event = NULL;
 641
 642                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 643                           vc4_state->mm.start);
 644
 645                 spin_unlock_irqrestore(&dev->event_lock, flags);
 646         } else {
 647                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 648                           vc4_state->mm.start);
 649         }
 650
 651         if (debug_dump_regs) {
 652                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 653                 vc4_hvs_dump_state(dev);
 654         }
 655 }
 656
 657 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
 658 {
 659         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 660         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 661
 662         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 663
 664         return 0;
 665 }
 666
 667 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
 668 {
 669         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 670         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 671
 672         CRTC_WRITE(PV_INTEN, 0);
 673 }
 674
 675 /* Must be called with the event lock held */
 676 bool vc4_event_pending(struct drm_crtc *crtc)
 677 {
 678         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 679
 680         return !!vc4_crtc->event;
 681 }
 682
 683 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 684 {
 685         struct drm_crtc *crtc = &vc4_crtc->base;
 686         struct drm_device *dev = crtc->dev;
 687         struct vc4_dev *vc4 = to_vc4_dev(dev);
 688         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 689         u32 chan = vc4_crtc->channel;
 690         unsigned long flags;
 691
 692         spin_lock_irqsave(&dev->event_lock, flags);
 693         if (vc4_crtc->event &&
 694             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
 695                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 696                 vc4_crtc->event = NULL;
 697                 drm_crtc_vblank_put(crtc);
 698         }
 699         spin_unlock_irqrestore(&dev->event_lock, flags);
 700 }
 701
 702 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 703 {
 704         struct vc4_crtc *vc4_crtc = data;
 705         u32 stat = CRTC_READ(PV_INTSTAT);
 706         irqreturn_t ret = IRQ_NONE;
 707
 708         if (stat & PV_INT_VFP_START) {
 709                 vc4_crtc->t_vblank = ktime_get();
 710                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 711                 drm_crtc_handle_vblank(&vc4_crtc->base);
 712                 vc4_crtc_handle_page_flip(vc4_crtc);
 713                 ret = IRQ_HANDLED;
 714         }
 715
 716         return ret;
 717 }
 718
 719 struct vc4_async_flip_state {
 720         struct drm_crtc *crtc;
 721         struct drm_framebuffer *fb;
 722         struct drm_pending_vblank_event *event;
 723
 724         struct vc4_seqno_cb cb;
 725 };
 726
 727 /* Called when the V3D execution for the BO being flipped to is done, so that
 728  * we can actually update the plane's address to point to it.
 729  */
 730 static void
 731 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 732 {
 733         struct vc4_async_flip_state *flip_state =
 734                 container_of(cb, struct vc4_async_flip_state, cb);
 735         struct drm_crtc *crtc = flip_state->crtc;
 736         struct drm_device *dev = crtc->dev;
 737         struct vc4_dev *vc4 = to_vc4_dev(dev);
 738         struct drm_plane *plane = crtc->primary;
 739
 740         vc4_plane_async_set_fb(plane, flip_state->fb);
 741         if (flip_state->event) {
 742                 unsigned long flags;
 743
 744                 spin_lock_irqsave(&dev->event_lock, flags);
 745                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 746                 spin_unlock_irqrestore(&dev->event_lock, flags);
 747         }
 748
 749         drm_crtc_vblank_put(crtc);
 750         drm_framebuffer_unreference(flip_state->fb);
 751         kfree(flip_state);
 752
 753         up(&vc4->async_modeset);
 754 }
 755
 756 /* Implements async (non-vblank-synced) page flips.
 757  *
 758  * The page flip ioctl needs to return immediately, so we grab the
 759  * modeset semaphore on the pipe, and queue the address update for
 760  * when V3D is done with the BO being flipped to.
 761  */
 762 static int vc4_async_page_flip(struct drm_crtc *crtc,
 763                                struct drm_framebuffer *fb,
 764                                struct drm_pending_vblank_event *event,
 765                                uint32_t flags)
 766 {
 767         struct drm_device *dev = crtc->dev;
 768         struct vc4_dev *vc4 = to_vc4_dev(dev);
 769         struct drm_plane *plane = crtc->primary;
 770         int ret = 0;
 771         struct vc4_async_flip_state *flip_state;
 772         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 773         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 774
 775         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 776         if (!flip_state)
 777                 return -ENOMEM;
 778
 779         drm_framebuffer_reference(fb);
 780         flip_state->fb = fb;
 781         flip_state->crtc = crtc;
 782         flip_state->event = event;
 783
 784         /* Make sure all other async modesetes have landed. */
 785         ret = down_interruptible(&vc4->async_modeset);
 786         if (ret) {
 787                 drm_framebuffer_unreference(fb);
 788                 kfree(flip_state);
 789                 return ret;
 790         }
 791
 792         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 793
 794         /* Immediately update the plane's legacy fb pointer, so that later
 795          * modeset prep sees the state that will be present when the semaphore
 796          * is released.
 797          */
 798         drm_atomic_set_fb_for_plane(plane->state, fb);
 799         plane->fb = fb;
 800
 801         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 802                            vc4_async_page_flip_complete);
 803
 804         /* Driver takes ownership of state on successful async commit. */
 805         return 0;
 806 }
 807
 808 static int vc4_page_flip(struct drm_crtc *crtc,
 809                          struct drm_framebuffer *fb,
 810                          struct drm_pending_vblank_event *event,
 811                          uint32_t flags)
 812 {
 813         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 814                 return vc4_async_page_flip(crtc, fb, event, flags);
 815         else
 816                 return drm_atomic_helper_page_flip(crtc, fb, event, flags);
 817 }
 818
 819 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 820 {
 821         struct vc4_crtc_state *vc4_state;
 822
 823         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 824         if (!vc4_state)
 825                 return NULL;
 826
 827         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 828         return &vc4_state->base;
 829 }
 830
 831 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 832                                    struct drm_crtc_state *state)
 833 {
 834         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 835         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 836
 837         if (vc4_state->mm.allocated) {
 838                 unsigned long flags;
 839
 840                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 841                 drm_mm_remove_node(&vc4_state->mm);
 842                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 843
 844         }
 845
 846         drm_atomic_helper_crtc_destroy_state(crtc, state);
 847 }
 848
 849 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 850         .set_config = drm_atomic_helper_set_config,
 851         .destroy = vc4_crtc_destroy,
 852         .page_flip = vc4_page_flip,
 853         .set_property = NULL,
 854         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 855         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 856         .reset = drm_atomic_helper_crtc_reset,
 857         .atomic_duplicate_state = vc4_crtc_duplicate_state,
 858         .atomic_destroy_state = vc4_crtc_destroy_state,
 859         .gamma_set = vc4_crtc_gamma_set,
 860 };
 861
 862 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 863         .mode_set_nofb = vc4_crtc_mode_set_nofb,
 864         .disable = vc4_crtc_disable,
 865         .enable = vc4_crtc_enable,
 866         .mode_fixup = vc4_crtc_mode_fixup,
 867         .atomic_check = vc4_crtc_atomic_check,
 868         .atomic_flush = vc4_crtc_atomic_flush,
 869 };
 870
 871 static const struct vc4_crtc_data pv0_data = {
 872         .hvs_channel = 0,
 873         .encoder_types = {
 874                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
 875                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
 876         },
 877 };
 878
 879 static const struct vc4_crtc_data pv1_data = {
 880         .hvs_channel = 2,
 881         .encoder_types = {
 882                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
 883                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
 884         },
 885 };
 886
 887 static const struct vc4_crtc_data pv2_data = {
 888         .hvs_channel = 1,
 889         .encoder_types = {
 890                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
 891                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
 892         },
 893 };
 894
 895 static const struct of_device_id vc4_crtc_dt_match[] = {
 896         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
 897         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
 898         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
 899         {}
 900 };
 901
 902 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
 903                                         struct drm_crtc *crtc)
 904 {
 905         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 906         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
 907         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
 908         struct drm_encoder *encoder;
 909
 910         drm_for_each_encoder(encoder, drm) {
 911                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 912                 int i;
 913
 914                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
 915                         if (vc4_encoder->type == encoder_types[i]) {
 916                                 vc4_encoder->clock_select = i;
 917                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
 918                                 break;
 919                         }
 920                 }
 921         }
 922 }
 923
 924 static void
 925 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
 926 {
 927         struct drm_device *drm = vc4_crtc->base.dev;
 928         struct vc4_dev *vc4 = to_vc4_dev(drm);
 929         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
 930         /* Top/base are supposed to be 4-pixel aligned, but the
 931          * Raspberry Pi firmware fills the low bits (which are
 932          * presumably ignored).
 933          */
 934         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
 935         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
 936
 937         vc4_crtc->cob_size = top - base + 4;
 938 }
 939
 940 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
 941 {
 942         struct platform_device *pdev = to_platform_device(dev);
 943         struct drm_device *drm = dev_get_drvdata(master);
 944         struct vc4_crtc *vc4_crtc;
 945         struct drm_crtc *crtc;
 946         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
 947         const struct of_device_id *match;
 948         int ret, i;
 949
 950         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
 951         if (!vc4_crtc)
 952                 return -ENOMEM;
 953         crtc = &vc4_crtc->base;
 954
 955         match = of_match_device(vc4_crtc_dt_match, dev);
 956         if (!match)
 957                 return -ENODEV;
 958         vc4_crtc->data = match->data;
 959
 960         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
 961         if (IS_ERR(vc4_crtc->regs))
 962                 return PTR_ERR(vc4_crtc->regs);
 963
 964         /* For now, we create just the primary and the legacy cursor
 965          * planes.  We should be able to stack more planes on easily,
 966          * but to do that we would need to compute the bandwidth
 967          * requirement of the plane configuration, and reject ones
 968          * that will take too much.
 969          */
 970         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
 971         if (IS_ERR(primary_plane)) {
 972                 dev_err(dev, "failed to construct primary plane\n");
 973                 ret = PTR_ERR(primary_plane);
 974                 goto err;
 975         }
 976
 977         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
 978                                   &vc4_crtc_funcs, NULL);
 979         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
 980         primary_plane->crtc = crtc;
 981         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
 982         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
 983
 984         /* Set up some arbitrary number of planes.  We're not limited
 985          * by a set number of physical registers, just the space in
 986          * the HVS (16k) and how small an plane can be (28 bytes).
 987          * However, each plane we set up takes up some memory, and
 988          * increases the cost of looping over planes, which atomic
 989          * modesetting does quite a bit.  As a result, we pick a
 990          * modest number of planes to expose, that should hopefully
 991          * still cover any sane usecase.
 992          */
 993         for (i = 0; i < 8; i++) {
 994                 struct drm_plane *plane =
 995                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
 996
 997                 if (IS_ERR(plane))
 998                         continue;
 999
1000                 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1001         }
1002
1003         /* Set up the legacy cursor after overlay initialization,
1004          * since we overlay planes on the CRTC in the order they were
1005          * initialized.
1006          */
1007         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1008         if (!IS_ERR(cursor_plane)) {
1009                 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1010                 cursor_plane->crtc = crtc;
1011                 crtc->cursor = cursor_plane;
1012         }
1013
1014         vc4_crtc_get_cob_allocation(vc4_crtc);
1015
1016         CRTC_WRITE(PV_INTEN, 0);
1017         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1018         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1019                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1020         if (ret)
1021                 goto err_destroy_planes;
1022
1023         vc4_set_crtc_possible_masks(drm, crtc);
1024
1025         for (i = 0; i < crtc->gamma_size; i++) {
1026                 vc4_crtc->lut_r[i] = i;
1027                 vc4_crtc->lut_g[i] = i;
1028                 vc4_crtc->lut_b[i] = i;
1029         }
1030
1031         platform_set_drvdata(pdev, vc4_crtc);
1032
1033         return 0;
1034
1035 err_destroy_planes:
1036         list_for_each_entry_safe(destroy_plane, temp,
1037                                  &drm->mode_config.plane_list, head) {
1038                 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1039                     destroy_plane->funcs->destroy(destroy_plane);
1040         }
1041 err:
1042         return ret;
1043 }
1044
1045 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1046                             void *data)
1047 {
1048         struct platform_device *pdev = to_platform_device(dev);
1049         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1050
1051         vc4_crtc_destroy(&vc4_crtc->base);
1052
1053         CRTC_WRITE(PV_INTEN, 0);
1054
1055         platform_set_drvdata(pdev, NULL);
1056 }
1057
1058 static const struct component_ops vc4_crtc_ops = {
1059         .bind   = vc4_crtc_bind,
1060         .unbind = vc4_crtc_unbind,
1061 };
1062
1063 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1064 {
1065         return component_add(&pdev->dev, &vc4_crtc_ops);
1066 }
1067
1068 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1069 {
1070         component_del(&pdev->dev, &vc4_crtc_ops);
1071         return 0;
1072 }
1073
1074 struct platform_driver vc4_crtc_driver = {
1075         .probe = vc4_crtc_dev_probe,
1076         .remove = vc4_crtc_dev_remove,
1077         .driver = {
1078                 .name = "vc4_crtc",
1079                 .of_match_table = vc4_crtc_dt_match,
1080         },
1081 };