drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * encoder's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, the CRTC is also
  19  * responsible for writing the display list for the HVS channel that
  20  * the CRTC will use.
  21  *
  22  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  23  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  24  * image domain can feed either HDMI or the SDTV controller.  The
  25  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  26  * SDTV, etc.) according to which output type is chosen in the mux.
  27  *
  28  * For power management, the pixel valve's registers are all clocked
  29  * by the AXI clock, while the timings and FIFOs make use of the
  30  * output-specific clock.  Since the encoders also directly consume
  31  * the CPRMAN clocks, and know what timings they need, they are the
  32  * ones that set the clock.
  33  */
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <linux/clk.h>
  39 #include <drm/drm_fb_cma_helper.h>
  40 #include <linux/component.h>
  41 #include <linux/of_device.h>
  42 #include "vc4_drv.h"
  43 #include "vc4_regs.h"
  44
  45 struct vc4_crtc {
  46         struct drm_crtc base;
  47         const struct vc4_crtc_data *data;
  48         void __iomem *regs;
  49
  50         /* Timestamp at start of vblank irq - unaffected by lock delays. */
  51         ktime_t t_vblank;
  52
  53         /* Which HVS channel we're using for our CRTC. */
  54         int channel;
  55
  56         u8 lut_r[256];
  57         u8 lut_g[256];
  58         u8 lut_b[256];
  59         /* Size in pixels of the COB memory allocated to this CRTC. */
  60         u32 cob_size;
  61
  62         struct drm_pending_vblank_event *event;
  63 };
  64
  65 struct vc4_crtc_state {
  66         struct drm_crtc_state base;
  67         /* Dlist area for this CRTC configuration. */
  68         struct drm_mm_node mm;
  69 };
  70
  71 static inline struct vc4_crtc *
  72 to_vc4_crtc(struct drm_crtc *crtc)
  73 {
  74         return (struct vc4_crtc *)crtc;
  75 }
  76
  77 static inline struct vc4_crtc_state *
  78 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  79 {
  80         return (struct vc4_crtc_state *)crtc_state;
  81 }
  82
  83 struct vc4_crtc_data {
  84         /* Which channel of the HVS this pixelvalve sources from. */
  85         int hvs_channel;
  86
  87         enum vc4_encoder_type encoder_types[4];
  88 };
  89
  90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  92
  93 #define CRTC_REG(reg) { reg, #reg }
  94 static const struct {
  95         u32 reg;
  96         const char *name;
  97 } crtc_regs[] = {
  98         CRTC_REG(PV_CONTROL),
  99         CRTC_REG(PV_V_CONTROL),
 100         CRTC_REG(PV_VSYNCD_EVEN),
 101         CRTC_REG(PV_HORZA),
 102         CRTC_REG(PV_HORZB),
 103         CRTC_REG(PV_VERTA),
 104         CRTC_REG(PV_VERTB),
 105         CRTC_REG(PV_VERTA_EVEN),
 106         CRTC_REG(PV_VERTB_EVEN),
 107         CRTC_REG(PV_INTEN),
 108         CRTC_REG(PV_INTSTAT),
 109         CRTC_REG(PV_STAT),
 110         CRTC_REG(PV_HACT_ACT),
 111 };
 112
 113 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
 114 {
 115         int i;
 116
 117         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 118                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 119                          crtc_regs[i].reg, crtc_regs[i].name,
 120                          CRTC_READ(crtc_regs[i].reg));
 121         }
 122 }
 123
 124 #ifdef CONFIG_DEBUG_FS
 125 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 126 {
 127         struct drm_info_node *node = (struct drm_info_node *)m->private;
 128         struct drm_device *dev = node->minor->dev;
 129         int crtc_index = (uintptr_t)node->info_ent->data;
 130         struct drm_crtc *crtc;
 131         struct vc4_crtc *vc4_crtc;
 132         int i;
 133
 134         i = 0;
 135         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 136                 if (i == crtc_index)
 137                         break;
 138                 i++;
 139         }
 140         if (!crtc)
 141                 return 0;
 142         vc4_crtc = to_vc4_crtc(crtc);
 143
 144         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 145                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 146                            crtc_regs[i].name, crtc_regs[i].reg,
 147                            CRTC_READ(crtc_regs[i].reg));
 148         }
 149
 150         return 0;
 151 }
 152 #endif
 153
 154 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 155                              bool in_vblank_irq, int *vpos, int *hpos,
 156                              ktime_t *stime, ktime_t *etime,
 157                              const struct drm_display_mode *mode)
 158 {
 159         struct vc4_dev *vc4 = to_vc4_dev(dev);
 160         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 161         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 162         u32 val;
 163         int fifo_lines;
 164         int vblank_lines;
 165         bool ret = false;
 166
 167         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 168
 169         /* Get optional system timestamp before query. */
 170         if (stime)
 171                 *stime = ktime_get();
 172
 173         /*
 174          * Read vertical scanline which is currently composed for our
 175          * pixelvalve by the HVS, and also the scaler status.
 176          */
 177         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 178
 179         /* Get optional system timestamp after query. */
 180         if (etime)
 181                 *etime = ktime_get();
 182
 183         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 184
 185         /* Vertical position of hvs composed scanline. */
 186         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 187         *hpos = 0;
 188
 189         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 190                 *vpos /= 2;
 191
 192                 /* Use hpos to correct for field offset in interlaced mode. */
 193                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 194                         *hpos += mode->crtc_htotal / 2;
 195         }
 196
 197         /* This is the offset we need for translating hvs -> pv scanout pos. */
 198         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 199
 200         if (fifo_lines > 0)
 201                 ret = true;
 202
 203         /* HVS more than fifo_lines into frame for compositing? */
 204         if (*vpos > fifo_lines) {
 205                 /*
 206                  * We are in active scanout and can get some meaningful results
 207                  * from HVS. The actual PV scanout can not trail behind more
 208                  * than fifo_lines as that is the fifo's capacity. Assume that
 209                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 210                  * refilling the fifo and PV consuming from the fifo, ie.
 211                  * whenever the PV consumes and frees up a scanline in the
 212                  * fifo, the HVS will immediately refill it, therefore
 213                  * incrementing vpos. Therefore we choose HVS read position -
 214                  * fifo size in scanlines as a estimate of the real scanout
 215                  * position of the PV.
 216                  */
 217                 *vpos -= fifo_lines + 1;
 218
 219                 return ret;
 220         }
 221
 222         /*
 223          * Less: This happens when we are in vblank and the HVS, after getting
 224          * the VSTART restart signal from the PV, just started refilling its
 225          * fifo with new lines from the top-most lines of the new framebuffers.
 226          * The PV does not scan out in vblank, so does not remove lines from
 227          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 228          * We can't get meaningful readings wrt. scanline position of the PV
 229          * and need to make things up in a approximative but consistent way.
 230          */
 231         vblank_lines = mode->vtotal - mode->vdisplay;
 232
 233         if (in_vblank_irq) {
 234                 /*
 235                  * Assume the irq handler got called close to first
 236                  * line of vblank, so PV has about a full vblank
 237                  * scanlines to go, and as a base timestamp use the
 238                  * one taken at entry into vblank irq handler, so it
 239                  * is not affected by random delays due to lock
 240                  * contention on event_lock or vblank_time lock in
 241                  * the core.
 242                  */
 243                 *vpos = -vblank_lines;
 244
 245                 if (stime)
 246                         *stime = vc4_crtc->t_vblank;
 247                 if (etime)
 248                         *etime = vc4_crtc->t_vblank;
 249
 250                 /*
 251                  * If the HVS fifo is not yet full then we know for certain
 252                  * we are at the very beginning of vblank, as the hvs just
 253                  * started refilling, and the stime and etime timestamps
 254                  * truly correspond to start of vblank.
 255                  *
 256                  * Unfortunately there's no way to report this to upper levels
 257                  * and make it more useful.
 258                  */
 259         } else {
 260                 /*
 261                  * No clue where we are inside vblank. Return a vpos of zero,
 262                  * which will cause calling code to just return the etime
 263                  * timestamp uncorrected. At least this is no worse than the
 264                  * standard fallback.
 265                  */
 266                 *vpos = 0;
 267         }
 268
 269         return ret;
 270 }
 271
 272 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 273 {
 274         drm_crtc_cleanup(crtc);
 275 }
 276
 277 static void
 278 vc4_crtc_lut_load(struct drm_crtc *crtc)
 279 {
 280         struct drm_device *dev = crtc->dev;
 281         struct vc4_dev *vc4 = to_vc4_dev(dev);
 282         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 283         u32 i;
 284
 285         /* The LUT memory is laid out with each HVS channel in order,
 286          * each of which takes 256 writes for R, 256 for G, then 256
 287          * for B.
 288          */
 289         HVS_WRITE(SCALER_GAMADDR,
 290                   SCALER_GAMADDR_AUTOINC |
 291                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 292
 293         for (i = 0; i < crtc->gamma_size; i++)
 294                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 295         for (i = 0; i < crtc->gamma_size; i++)
 296                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 297         for (i = 0; i < crtc->gamma_size; i++)
 298                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 299 }
 300
 301 static int
 302 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 303                    uint32_t size,
 304                    struct drm_modeset_acquire_ctx *ctx)
 305 {
 306         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 307         u32 i;
 308
 309         for (i = 0; i < size; i++) {
 310                 vc4_crtc->lut_r[i] = r[i] >> 8;
 311                 vc4_crtc->lut_g[i] = g[i] >> 8;
 312                 vc4_crtc->lut_b[i] = b[i] >> 8;
 313         }
 314
 315         vc4_crtc_lut_load(crtc);
 316
 317         return 0;
 318 }
 319
 320 static u32 vc4_get_fifo_full_level(u32 format)
 321 {
 322         static const u32 fifo_len_bytes = 64;
 323         static const u32 hvs_latency_pix = 6;
 324
 325         switch (format) {
 326         case PV_CONTROL_FORMAT_DSIV_16:
 327         case PV_CONTROL_FORMAT_DSIC_16:
 328                 return fifo_len_bytes - 2 * hvs_latency_pix;
 329         case PV_CONTROL_FORMAT_DSIV_18:
 330                 return fifo_len_bytes - 14;
 331         case PV_CONTROL_FORMAT_24:
 332         case PV_CONTROL_FORMAT_DSIV_24:
 333         default:
 334                 return fifo_len_bytes - 3 * hvs_latency_pix;
 335         }
 336 }
 337
 338 /*
 339  * Returns the encoder attached to the CRTC.
 340  *
 341  * VC4 can only scan out to one encoder at a time, while the DRM core
 342  * allows drivers to push pixels to more than one encoder from the
 343  * same CRTC.
 344  */
 345 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 346 {
 347         struct drm_connector *connector;
 348         struct drm_connector_list_iter conn_iter;
 349
 350         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 351         drm_for_each_connector_iter(connector, &conn_iter) {
 352                 if (connector->state->crtc == crtc) {
 353                         drm_connector_list_iter_end(&conn_iter);
 354                         return connector->encoder;
 355                 }
 356         }
 357         drm_connector_list_iter_end(&conn_iter);
 358
 359         return NULL;
 360 }
 361
 362 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 363 {
 364         struct drm_device *dev = crtc->dev;
 365         struct vc4_dev *vc4 = to_vc4_dev(dev);
 366         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 367         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 368         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 369         struct drm_crtc_state *state = crtc->state;
 370         struct drm_display_mode *mode = &state->adjusted_mode;
 371         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 372         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 373         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 374                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 375         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 376         bool debug_dump_regs = false;
 377
 378         if (debug_dump_regs) {
 379                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 380                 vc4_crtc_dump_regs(vc4_crtc);
 381         }
 382
 383         /* Reset the PV fifo. */
 384         CRTC_WRITE(PV_CONTROL, 0);
 385         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 386         CRTC_WRITE(PV_CONTROL, 0);
 387
 388         CRTC_WRITE(PV_HORZA,
 389                    VC4_SET_FIELD((mode->htotal -
 390                                   mode->hsync_end) * pixel_rep,
 391                                  PV_HORZA_HBP) |
 392                    VC4_SET_FIELD((mode->hsync_end -
 393                                   mode->hsync_start) * pixel_rep,
 394                                  PV_HORZA_HSYNC));
 395         CRTC_WRITE(PV_HORZB,
 396                    VC4_SET_FIELD((mode->hsync_start -
 397                                   mode->hdisplay) * pixel_rep,
 398                                  PV_HORZB_HFP) |
 399                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 400
 401         CRTC_WRITE(PV_VERTA,
 402                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 403                                  PV_VERTA_VBP) |
 404                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 405                                  PV_VERTA_VSYNC));
 406         CRTC_WRITE(PV_VERTB,
 407                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 408                                  PV_VERTB_VFP) |
 409                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 410
 411         if (interlace) {
 412                 CRTC_WRITE(PV_VERTA_EVEN,
 413                            VC4_SET_FIELD(mode->crtc_vtotal -
 414                                          mode->crtc_vsync_end - 1,
 415                                          PV_VERTA_VBP) |
 416                            VC4_SET_FIELD(mode->crtc_vsync_end -
 417                                          mode->crtc_vsync_start,
 418                                          PV_VERTA_VSYNC));
 419                 CRTC_WRITE(PV_VERTB_EVEN,
 420                            VC4_SET_FIELD(mode->crtc_vsync_start -
 421                                          mode->crtc_vdisplay,
 422                                          PV_VERTB_VFP) |
 423                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 424
 425                 /* We set up first field even mode for HDMI.  VEC's
 426                  * NTSC mode would want first field odd instead, once
 427                  * we support it (to do so, set ODD_FIRST and put the
 428                  * delay in VSYNCD_EVEN instead).
 429                  */
 430                 CRTC_WRITE(PV_V_CONTROL,
 431                            PV_VCONTROL_CONTINUOUS |
 432                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 433                            PV_VCONTROL_INTERLACE |
 434                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 435                                          PV_VCONTROL_ODD_DELAY));
 436                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 437         } else {
 438                 CRTC_WRITE(PV_V_CONTROL,
 439                            PV_VCONTROL_CONTINUOUS |
 440                            (is_dsi ? PV_VCONTROL_DSI : 0));
 441         }
 442
 443         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 444
 445         CRTC_WRITE(PV_CONTROL,
 446                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 447                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 448                                  PV_CONTROL_FIFO_LEVEL) |
 449                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 450                    PV_CONTROL_CLR_AT_START |
 451                    PV_CONTROL_TRIGGER_UNDERFLOW |
 452                    PV_CONTROL_WAIT_HSTART |
 453                    VC4_SET_FIELD(vc4_encoder->clock_select,
 454                                  PV_CONTROL_CLK_SELECT) |
 455                    PV_CONTROL_FIFO_CLR |
 456                    PV_CONTROL_EN);
 457
 458         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 459                   SCALER_DISPBKGND_AUTOHS |
 460                   SCALER_DISPBKGND_GAMMA |
 461                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 462
 463         /* Reload the LUT, since the SRAMs would have been disabled if
 464          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 465          */
 466         vc4_crtc_lut_load(crtc);
 467
 468         if (debug_dump_regs) {
 469                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 470                 vc4_crtc_dump_regs(vc4_crtc);
 471         }
 472 }
 473
 474 static void require_hvs_enabled(struct drm_device *dev)
 475 {
 476         struct vc4_dev *vc4 = to_vc4_dev(dev);
 477
 478         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 479                      SCALER_DISPCTRL_ENABLE);
 480 }
 481
 482 static void vc4_crtc_disable(struct drm_crtc *crtc)
 483 {
 484         struct drm_device *dev = crtc->dev;
 485         struct vc4_dev *vc4 = to_vc4_dev(dev);
 486         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 487         u32 chan = vc4_crtc->channel;
 488         int ret;
 489         require_hvs_enabled(dev);
 490
 491         /* Disable vblank irq handling before crtc is disabled. */
 492         drm_crtc_vblank_off(crtc);
 493
 494         CRTC_WRITE(PV_V_CONTROL,
 495                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 496         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 497         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 498
 499         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 500             SCALER_DISPCTRLX_ENABLE) {
 501                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 502                           SCALER_DISPCTRLX_RESET);
 503
 504                 /* While the docs say that reset is self-clearing, it
 505                  * seems it doesn't actually.
 506                  */
 507                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 508         }
 509
 510         /* Once we leave, the scaler should be disabled and its fifo empty. */
 511
 512         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 513
 514         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 515                                    SCALER_DISPSTATX_MODE) !=
 516                      SCALER_DISPSTATX_MODE_DISABLED);
 517
 518         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 519                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 520                      SCALER_DISPSTATX_EMPTY);
 521 }
 522
 523 static void vc4_crtc_enable(struct drm_crtc *crtc)
 524 {
 525         struct drm_device *dev = crtc->dev;
 526         struct vc4_dev *vc4 = to_vc4_dev(dev);
 527         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 528         struct drm_crtc_state *state = crtc->state;
 529         struct drm_display_mode *mode = &state->adjusted_mode;
 530
 531         require_hvs_enabled(dev);
 532
 533         /* Turn on the scaler, which will wait for vstart to start
 534          * compositing.
 535          */
 536         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 537                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 538                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 539                   SCALER_DISPCTRLX_ENABLE);
 540
 541         /* Turn on the pixel valve, which will emit the vstart signal. */
 542         CRTC_WRITE(PV_V_CONTROL,
 543                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 544
 545         /* Enable vblank irq handling after crtc is started. */
 546         drm_crtc_vblank_on(crtc);
 547 }
 548
 549 static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
 550                                 const struct drm_display_mode *mode,
 551                                 struct drm_display_mode *adjusted_mode)
 552 {
 553         /* Do not allow doublescan modes from user space */
 554         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 555                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 556                               crtc->base.id);
 557                 return false;
 558         }
 559
 560         return true;
 561 }
 562
 563 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 564                                  struct drm_crtc_state *state)
 565 {
 566         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 567         struct drm_device *dev = crtc->dev;
 568         struct vc4_dev *vc4 = to_vc4_dev(dev);
 569         struct drm_plane *plane;
 570         unsigned long flags;
 571         const struct drm_plane_state *plane_state;
 572         u32 dlist_count = 0;
 573         int ret;
 574
 575         /* The pixelvalve can only feed one encoder (and encoders are
 576          * 1:1 with connectors.)
 577          */
 578         if (hweight32(state->connector_mask) > 1)
 579                 return -EINVAL;
 580
 581         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 582                 dlist_count += vc4_plane_dlist_size(plane_state);
 583
 584         dlist_count++; /* Account for SCALER_CTL0_END. */
 585
 586         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 587         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 588                                  dlist_count);
 589         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 590         if (ret)
 591                 return ret;
 592
 593         return 0;
 594 }
 595
 596 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 597                                   struct drm_crtc_state *old_state)
 598 {
 599         struct drm_device *dev = crtc->dev;
 600         struct vc4_dev *vc4 = to_vc4_dev(dev);
 601         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 602         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 603         struct drm_plane *plane;
 604         bool debug_dump_regs = false;
 605         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 606         u32 __iomem *dlist_next = dlist_start;
 607
 608         if (debug_dump_regs) {
 609                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 610                 vc4_hvs_dump_state(dev);
 611         }
 612
 613         /* Copy all the active planes' dlist contents to the hardware dlist. */
 614         drm_atomic_crtc_for_each_plane(plane, crtc) {
 615                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 616         }
 617
 618         writel(SCALER_CTL0_END, dlist_next);
 619         dlist_next++;
 620
 621         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 622
 623         if (crtc->state->event) {
 624                 unsigned long flags;
 625
 626                 crtc->state->event->pipe = drm_crtc_index(crtc);
 627
 628                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 629
 630                 spin_lock_irqsave(&dev->event_lock, flags);
 631                 vc4_crtc->event = crtc->state->event;
 632                 crtc->state->event = NULL;
 633
 634                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 635                           vc4_state->mm.start);
 636
 637                 spin_unlock_irqrestore(&dev->event_lock, flags);
 638         } else {
 639                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 640                           vc4_state->mm.start);
 641         }
 642
 643         if (debug_dump_regs) {
 644                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 645                 vc4_hvs_dump_state(dev);
 646         }
 647 }
 648
 649 static int vc4_enable_vblank(struct drm_crtc *crtc)
 650 {
 651         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 652
 653         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 654
 655         return 0;
 656 }
 657
 658 static void vc4_disable_vblank(struct drm_crtc *crtc)
 659 {
 660         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 661
 662         CRTC_WRITE(PV_INTEN, 0);
 663 }
 664
 665 /* Must be called with the event lock held */
 666 bool vc4_event_pending(struct drm_crtc *crtc)
 667 {
 668         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 669
 670         return !!vc4_crtc->event;
 671 }
 672
 673 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 674 {
 675         struct drm_crtc *crtc = &vc4_crtc->base;
 676         struct drm_device *dev = crtc->dev;
 677         struct vc4_dev *vc4 = to_vc4_dev(dev);
 678         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 679         u32 chan = vc4_crtc->channel;
 680         unsigned long flags;
 681
 682         spin_lock_irqsave(&dev->event_lock, flags);
 683         if (vc4_crtc->event &&
 684             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
 685                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 686                 vc4_crtc->event = NULL;
 687                 drm_crtc_vblank_put(crtc);
 688         }
 689         spin_unlock_irqrestore(&dev->event_lock, flags);
 690 }
 691
 692 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 693 {
 694         struct vc4_crtc *vc4_crtc = data;
 695         u32 stat = CRTC_READ(PV_INTSTAT);
 696         irqreturn_t ret = IRQ_NONE;
 697
 698         if (stat & PV_INT_VFP_START) {
 699                 vc4_crtc->t_vblank = ktime_get();
 700                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 701                 drm_crtc_handle_vblank(&vc4_crtc->base);
 702                 vc4_crtc_handle_page_flip(vc4_crtc);
 703                 ret = IRQ_HANDLED;
 704         }
 705
 706         return ret;
 707 }
 708
 709 struct vc4_async_flip_state {
 710         struct drm_crtc *crtc;
 711         struct drm_framebuffer *fb;
 712         struct drm_pending_vblank_event *event;
 713
 714         struct vc4_seqno_cb cb;
 715 };
 716
 717 /* Called when the V3D execution for the BO being flipped to is done, so that
 718  * we can actually update the plane's address to point to it.
 719  */
 720 static void
 721 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 722 {
 723         struct vc4_async_flip_state *flip_state =
 724                 container_of(cb, struct vc4_async_flip_state, cb);
 725         struct drm_crtc *crtc = flip_state->crtc;
 726         struct drm_device *dev = crtc->dev;
 727         struct vc4_dev *vc4 = to_vc4_dev(dev);
 728         struct drm_plane *plane = crtc->primary;
 729
 730         vc4_plane_async_set_fb(plane, flip_state->fb);
 731         if (flip_state->event) {
 732                 unsigned long flags;
 733
 734                 spin_lock_irqsave(&dev->event_lock, flags);
 735                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 736                 spin_unlock_irqrestore(&dev->event_lock, flags);
 737         }
 738
 739         drm_crtc_vblank_put(crtc);
 740         drm_framebuffer_unreference(flip_state->fb);
 741         kfree(flip_state);
 742
 743         up(&vc4->async_modeset);
 744 }
 745
 746 /* Implements async (non-vblank-synced) page flips.
 747  *
 748  * The page flip ioctl needs to return immediately, so we grab the
 749  * modeset semaphore on the pipe, and queue the address update for
 750  * when V3D is done with the BO being flipped to.
 751  */
 752 static int vc4_async_page_flip(struct drm_crtc *crtc,
 753                                struct drm_framebuffer *fb,
 754                                struct drm_pending_vblank_event *event,
 755                                uint32_t flags)
 756 {
 757         struct drm_device *dev = crtc->dev;
 758         struct vc4_dev *vc4 = to_vc4_dev(dev);
 759         struct drm_plane *plane = crtc->primary;
 760         int ret = 0;
 761         struct vc4_async_flip_state *flip_state;
 762         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 763         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 764
 765         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 766         if (!flip_state)
 767                 return -ENOMEM;
 768
 769         drm_framebuffer_reference(fb);
 770         flip_state->fb = fb;
 771         flip_state->crtc = crtc;
 772         flip_state->event = event;
 773
 774         /* Make sure all other async modesetes have landed. */
 775         ret = down_interruptible(&vc4->async_modeset);
 776         if (ret) {
 777                 drm_framebuffer_unreference(fb);
 778                 kfree(flip_state);
 779                 return ret;
 780         }
 781
 782         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 783
 784         /* Immediately update the plane's legacy fb pointer, so that later
 785          * modeset prep sees the state that will be present when the semaphore
 786          * is released.
 787          */
 788         drm_atomic_set_fb_for_plane(plane->state, fb);
 789         plane->fb = fb;
 790
 791         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 792                            vc4_async_page_flip_complete);
 793
 794         /* Driver takes ownership of state on successful async commit. */
 795         return 0;
 796 }
 797
 798 static int vc4_page_flip(struct drm_crtc *crtc,
 799                          struct drm_framebuffer *fb,
 800                          struct drm_pending_vblank_event *event,
 801                          uint32_t flags,
 802                          struct drm_modeset_acquire_ctx *ctx)
 803 {
 804         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 805                 return vc4_async_page_flip(crtc, fb, event, flags);
 806         else
 807                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 808 }
 809
 810 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 811 {
 812         struct vc4_crtc_state *vc4_state;
 813
 814         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 815         if (!vc4_state)
 816                 return NULL;
 817
 818         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 819         return &vc4_state->base;
 820 }
 821
 822 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 823                                    struct drm_crtc_state *state)
 824 {
 825         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 826         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 827
 828         if (vc4_state->mm.allocated) {
 829                 unsigned long flags;
 830
 831                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 832                 drm_mm_remove_node(&vc4_state->mm);
 833                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 834
 835         }
 836
 837         drm_atomic_helper_crtc_destroy_state(crtc, state);
 838 }
 839
 840 static void
 841 vc4_crtc_reset(struct drm_crtc *crtc)
 842 {
 843         if (crtc->state)
 844                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 845
 846         crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
 847         if (crtc->state)
 848                 crtc->state->crtc = crtc;
 849 }
 850
 851 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 852         .set_config = drm_atomic_helper_set_config,
 853         .destroy = vc4_crtc_destroy,
 854         .page_flip = vc4_page_flip,
 855         .set_property = NULL,
 856         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 857         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 858         .reset = vc4_crtc_reset,
 859         .atomic_duplicate_state = vc4_crtc_duplicate_state,
 860         .atomic_destroy_state = vc4_crtc_destroy_state,
 861         .gamma_set = vc4_crtc_gamma_set,
 862         .enable_vblank = vc4_enable_vblank,
 863         .disable_vblank = vc4_disable_vblank,
 864 };
 865
 866 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 867         .mode_set_nofb = vc4_crtc_mode_set_nofb,
 868         .disable = vc4_crtc_disable,
 869         .enable = vc4_crtc_enable,
 870         .mode_fixup = vc4_crtc_mode_fixup,
 871         .atomic_check = vc4_crtc_atomic_check,
 872         .atomic_flush = vc4_crtc_atomic_flush,
 873 };
 874
 875 static const struct vc4_crtc_data pv0_data = {
 876         .hvs_channel = 0,
 877         .encoder_types = {
 878                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
 879                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
 880         },
 881 };
 882
 883 static const struct vc4_crtc_data pv1_data = {
 884         .hvs_channel = 2,
 885         .encoder_types = {
 886                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
 887                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
 888         },
 889 };
 890
 891 static const struct vc4_crtc_data pv2_data = {
 892         .hvs_channel = 1,
 893         .encoder_types = {
 894                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
 895                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
 896         },
 897 };
 898
 899 static const struct of_device_id vc4_crtc_dt_match[] = {
 900         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
 901         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
 902         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
 903         {}
 904 };
 905
 906 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
 907                                         struct drm_crtc *crtc)
 908 {
 909         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 910         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
 911         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
 912         struct drm_encoder *encoder;
 913
 914         drm_for_each_encoder(encoder, drm) {
 915                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 916                 int i;
 917
 918                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
 919                         if (vc4_encoder->type == encoder_types[i]) {
 920                                 vc4_encoder->clock_select = i;
 921                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
 922                                 break;
 923                         }
 924                 }
 925         }
 926 }
 927
 928 static void
 929 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
 930 {
 931         struct drm_device *drm = vc4_crtc->base.dev;
 932         struct vc4_dev *vc4 = to_vc4_dev(drm);
 933         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
 934         /* Top/base are supposed to be 4-pixel aligned, but the
 935          * Raspberry Pi firmware fills the low bits (which are
 936          * presumably ignored).
 937          */
 938         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
 939         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
 940
 941         vc4_crtc->cob_size = top - base + 4;
 942 }
 943
 944 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
 945 {
 946         struct platform_device *pdev = to_platform_device(dev);
 947         struct drm_device *drm = dev_get_drvdata(master);
 948         struct vc4_crtc *vc4_crtc;
 949         struct drm_crtc *crtc;
 950         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
 951         const struct of_device_id *match;
 952         int ret, i;
 953
 954         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
 955         if (!vc4_crtc)
 956                 return -ENOMEM;
 957         crtc = &vc4_crtc->base;
 958
 959         match = of_match_device(vc4_crtc_dt_match, dev);
 960         if (!match)
 961                 return -ENODEV;
 962         vc4_crtc->data = match->data;
 963
 964         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
 965         if (IS_ERR(vc4_crtc->regs))
 966                 return PTR_ERR(vc4_crtc->regs);
 967
 968         /* For now, we create just the primary and the legacy cursor
 969          * planes.  We should be able to stack more planes on easily,
 970          * but to do that we would need to compute the bandwidth
 971          * requirement of the plane configuration, and reject ones
 972          * that will take too much.
 973          */
 974         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
 975         if (IS_ERR(primary_plane)) {
 976                 dev_err(dev, "failed to construct primary plane\n");
 977                 ret = PTR_ERR(primary_plane);
 978                 goto err;
 979         }
 980
 981         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
 982                                   &vc4_crtc_funcs, NULL);
 983         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
 984         primary_plane->crtc = crtc;
 985         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
 986         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
 987
 988         /* Set up some arbitrary number of planes.  We're not limited
 989          * by a set number of physical registers, just the space in
 990          * the HVS (16k) and how small an plane can be (28 bytes).
 991          * However, each plane we set up takes up some memory, and
 992          * increases the cost of looping over planes, which atomic
 993          * modesetting does quite a bit.  As a result, we pick a
 994          * modest number of planes to expose, that should hopefully
 995          * still cover any sane usecase.
 996          */
 997         for (i = 0; i < 8; i++) {
 998                 struct drm_plane *plane =
 999                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1000
1001                 if (IS_ERR(plane))
1002                         continue;
1003
1004                 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1005         }
1006
1007         /* Set up the legacy cursor after overlay initialization,
1008          * since we overlay planes on the CRTC in the order they were
1009          * initialized.
1010          */
1011         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1012         if (!IS_ERR(cursor_plane)) {
1013                 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1014                 cursor_plane->crtc = crtc;
1015                 crtc->cursor = cursor_plane;
1016         }
1017
1018         vc4_crtc_get_cob_allocation(vc4_crtc);
1019
1020         CRTC_WRITE(PV_INTEN, 0);
1021         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1022         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1023                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1024         if (ret)
1025                 goto err_destroy_planes;
1026
1027         vc4_set_crtc_possible_masks(drm, crtc);
1028
1029         for (i = 0; i < crtc->gamma_size; i++) {
1030                 vc4_crtc->lut_r[i] = i;
1031                 vc4_crtc->lut_g[i] = i;
1032                 vc4_crtc->lut_b[i] = i;
1033         }
1034
1035         platform_set_drvdata(pdev, vc4_crtc);
1036
1037         return 0;
1038
1039 err_destroy_planes:
1040         list_for_each_entry_safe(destroy_plane, temp,
1041                                  &drm->mode_config.plane_list, head) {
1042                 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1043                     destroy_plane->funcs->destroy(destroy_plane);
1044         }
1045 err:
1046         return ret;
1047 }
1048
1049 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1050                             void *data)
1051 {
1052         struct platform_device *pdev = to_platform_device(dev);
1053         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1054
1055         vc4_crtc_destroy(&vc4_crtc->base);
1056
1057         CRTC_WRITE(PV_INTEN, 0);
1058
1059         platform_set_drvdata(pdev, NULL);
1060 }
1061
1062 static const struct component_ops vc4_crtc_ops = {
1063         .bind   = vc4_crtc_bind,
1064         .unbind = vc4_crtc_unbind,
1065 };
1066
1067 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1068 {
1069         return component_add(&pdev->dev, &vc4_crtc_ops);
1070 }
1071
1072 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1073 {
1074         component_del(&pdev->dev, &vc4_crtc_ops);
1075         return 0;
1076 }
1077
1078 struct platform_driver vc4_crtc_driver = {
1079         .probe = vc4_crtc_dev_probe,
1080         .remove = vc4_crtc_dev_remove,
1081         .driver = {
1082                 .name = "vc4_crtc",
1083                 .of_match_table = vc4_crtc_dt_match,
1084         },
1085 };