drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * encoder's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, the CRTC is also
  19  * responsible for writing the display list for the HVS channel that
  20  * the CRTC will use.
  21  *
  22  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  23  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  24  * image domain can feed either HDMI or the SDTV controller.  The
  25  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  26  * SDTV, etc.) according to which output type is chosen in the mux.
  27  *
  28  * For power management, the pixel valve's registers are all clocked
  29  * by the AXI clock, while the timings and FIFOs make use of the
  30  * output-specific clock.  Since the encoders also directly consume
  31  * the CPRMAN clocks, and know what timings they need, they are the
  32  * ones that set the clock.
  33  */
  34
  35 #include "drm_atomic.h"
  36 #include "drm_atomic_helper.h"
  37 #include "drm_crtc_helper.h"
  38 #include "linux/clk.h"
  39 #include "drm_fb_cma_helper.h"
  40 #include "linux/component.h"
  41 #include "linux/of_device.h"
  42 #include "vc4_drv.h"
  43 #include "vc4_regs.h"
  44
  45 struct vc4_crtc {
  46         struct drm_crtc base;
  47         const struct vc4_crtc_data *data;
  48         void __iomem *regs;
  49
  50         /* Timestamp at start of vblank irq - unaffected by lock delays. */
  51         ktime_t t_vblank;
  52
  53         /* Which HVS channel we're using for our CRTC. */
  54         int channel;
  55
  56         u8 lut_r[256];
  57         u8 lut_g[256];
  58         u8 lut_b[256];
  59         /* Size in pixels of the COB memory allocated to this CRTC. */
  60         u32 cob_size;
  61
  62         struct drm_pending_vblank_event *event;
  63 };
  64
  65 struct vc4_crtc_state {
  66         struct drm_crtc_state base;
  67         /* Dlist area for this CRTC configuration. */
  68         struct drm_mm_node mm;
  69 };
  70
  71 static inline struct vc4_crtc *
  72 to_vc4_crtc(struct drm_crtc *crtc)
  73 {
  74         return (struct vc4_crtc *)crtc;
  75 }
  76
  77 static inline struct vc4_crtc_state *
  78 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  79 {
  80         return (struct vc4_crtc_state *)crtc_state;
  81 }
  82
  83 struct vc4_crtc_data {
  84         /* Which channel of the HVS this pixelvalve sources from. */
  85         int hvs_channel;
  86
  87         enum vc4_encoder_type encoder_types[4];
  88 };
  89
  90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  92
  93 #define CRTC_REG(reg) { reg, #reg }
  94 static const struct {
  95         u32 reg;
  96         const char *name;
  97 } crtc_regs[] = {
  98         CRTC_REG(PV_CONTROL),
  99         CRTC_REG(PV_V_CONTROL),
 100         CRTC_REG(PV_VSYNCD_EVEN),
 101         CRTC_REG(PV_HORZA),
 102         CRTC_REG(PV_HORZB),
 103         CRTC_REG(PV_VERTA),
 104         CRTC_REG(PV_VERTB),
 105         CRTC_REG(PV_VERTA_EVEN),
 106         CRTC_REG(PV_VERTB_EVEN),
 107         CRTC_REG(PV_INTEN),
 108         CRTC_REG(PV_INTSTAT),
 109         CRTC_REG(PV_STAT),
 110         CRTC_REG(PV_HACT_ACT),
 111 };
 112
 113 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
 114 {
 115         int i;
 116
 117         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 118                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 119                          crtc_regs[i].reg, crtc_regs[i].name,
 120                          CRTC_READ(crtc_regs[i].reg));
 121         }
 122 }
 123
 124 #ifdef CONFIG_DEBUG_FS
 125 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 126 {
 127         struct drm_info_node *node = (struct drm_info_node *)m->private;
 128         struct drm_device *dev = node->minor->dev;
 129         int crtc_index = (uintptr_t)node->info_ent->data;
 130         struct drm_crtc *crtc;
 131         struct vc4_crtc *vc4_crtc;
 132         int i;
 133
 134         i = 0;
 135         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 136                 if (i == crtc_index)
 137                         break;
 138                 i++;
 139         }
 140         if (!crtc)
 141                 return 0;
 142         vc4_crtc = to_vc4_crtc(crtc);
 143
 144         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 145                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 146                            crtc_regs[i].name, crtc_regs[i].reg,
 147                            CRTC_READ(crtc_regs[i].reg));
 148         }
 149
 150         return 0;
 151 }
 152 #endif
 153
 154 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 155                             unsigned int flags, int *vpos, int *hpos,
 156                             ktime_t *stime, ktime_t *etime,
 157                             const struct drm_display_mode *mode)
 158 {
 159         struct vc4_dev *vc4 = to_vc4_dev(dev);
 160         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 161         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 162         u32 val;
 163         int fifo_lines;
 164         int vblank_lines;
 165         int ret = 0;
 166
 167         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 168
 169         /* Get optional system timestamp before query. */
 170         if (stime)
 171                 *stime = ktime_get();
 172
 173         /*
 174          * Read vertical scanline which is currently composed for our
 175          * pixelvalve by the HVS, and also the scaler status.
 176          */
 177         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 178
 179         /* Get optional system timestamp after query. */
 180         if (etime)
 181                 *etime = ktime_get();
 182
 183         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 184
 185         /* Vertical position of hvs composed scanline. */
 186         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 187         *hpos = 0;
 188
 189         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 190                 *vpos /= 2;
 191
 192                 /* Use hpos to correct for field offset in interlaced mode. */
 193                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 194                         *hpos += mode->crtc_htotal / 2;
 195         }
 196
 197         /* This is the offset we need for translating hvs -> pv scanout pos. */
 198         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 199
 200         if (fifo_lines > 0)
 201                 ret |= DRM_SCANOUTPOS_VALID;
 202
 203         /* HVS more than fifo_lines into frame for compositing? */
 204         if (*vpos > fifo_lines) {
 205                 /*
 206                  * We are in active scanout and can get some meaningful results
 207                  * from HVS. The actual PV scanout can not trail behind more
 208                  * than fifo_lines as that is the fifo's capacity. Assume that
 209                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 210                  * refilling the fifo and PV consuming from the fifo, ie.
 211                  * whenever the PV consumes and frees up a scanline in the
 212                  * fifo, the HVS will immediately refill it, therefore
 213                  * incrementing vpos. Therefore we choose HVS read position -
 214                  * fifo size in scanlines as a estimate of the real scanout
 215                  * position of the PV.
 216                  */
 217                 *vpos -= fifo_lines + 1;
 218
 219                 ret |= DRM_SCANOUTPOS_ACCURATE;
 220                 return ret;
 221         }
 222
 223         /*
 224          * Less: This happens when we are in vblank and the HVS, after getting
 225          * the VSTART restart signal from the PV, just started refilling its
 226          * fifo with new lines from the top-most lines of the new framebuffers.
 227          * The PV does not scan out in vblank, so does not remove lines from
 228          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 229          * We can't get meaningful readings wrt. scanline position of the PV
 230          * and need to make things up in a approximative but consistent way.
 231          */
 232         ret |= DRM_SCANOUTPOS_IN_VBLANK;
 233         vblank_lines = mode->vtotal - mode->vdisplay;
 234
 235         if (flags & DRM_CALLED_FROM_VBLIRQ) {
 236                 /*
 237                  * Assume the irq handler got called close to first
 238                  * line of vblank, so PV has about a full vblank
 239                  * scanlines to go, and as a base timestamp use the
 240                  * one taken at entry into vblank irq handler, so it
 241                  * is not affected by random delays due to lock
 242                  * contention on event_lock or vblank_time lock in
 243                  * the core.
 244                  */
 245                 *vpos = -vblank_lines;
 246
 247                 if (stime)
 248                         *stime = vc4_crtc->t_vblank;
 249                 if (etime)
 250                         *etime = vc4_crtc->t_vblank;
 251
 252                 /*
 253                  * If the HVS fifo is not yet full then we know for certain
 254                  * we are at the very beginning of vblank, as the hvs just
 255                  * started refilling, and the stime and etime timestamps
 256                  * truly correspond to start of vblank.
 257                  */
 258                 if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL)
 259                         ret |= DRM_SCANOUTPOS_ACCURATE;
 260         } else {
 261                 /*
 262                  * No clue where we are inside vblank. Return a vpos of zero,
 263                  * which will cause calling code to just return the etime
 264                  * timestamp uncorrected. At least this is no worse than the
 265                  * standard fallback.
 266                  */
 267                 *vpos = 0;
 268         }
 269
 270         return ret;
 271 }
 272
 273 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
 274                                   int *max_error, struct timeval *vblank_time,
 275                                   unsigned flags)
 276 {
 277         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 278         struct drm_crtc_state *state = crtc->state;
 279
 280         /* Helper routine in DRM core does all the work: */
 281         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error,
 282                                                      vblank_time, flags,
 283                                                      &state->adjusted_mode);
 284 }
 285
 286 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 287 {
 288         drm_crtc_cleanup(crtc);
 289 }
 290
 291 static void
 292 vc4_crtc_lut_load(struct drm_crtc *crtc)
 293 {
 294         struct drm_device *dev = crtc->dev;
 295         struct vc4_dev *vc4 = to_vc4_dev(dev);
 296         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 297         u32 i;
 298
 299         /* The LUT memory is laid out with each HVS channel in order,
 300          * each of which takes 256 writes for R, 256 for G, then 256
 301          * for B.
 302          */
 303         HVS_WRITE(SCALER_GAMADDR,
 304                   SCALER_GAMADDR_AUTOINC |
 305                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 306
 307         for (i = 0; i < crtc->gamma_size; i++)
 308                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 309         for (i = 0; i < crtc->gamma_size; i++)
 310                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 311         for (i = 0; i < crtc->gamma_size; i++)
 312                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 313 }
 314
 315 static int
 316 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 317                    uint32_t size)
 318 {
 319         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 320         u32 i;
 321
 322         for (i = 0; i < size; i++) {
 323                 vc4_crtc->lut_r[i] = r[i] >> 8;
 324                 vc4_crtc->lut_g[i] = g[i] >> 8;
 325                 vc4_crtc->lut_b[i] = b[i] >> 8;
 326         }
 327
 328         vc4_crtc_lut_load(crtc);
 329
 330         return 0;
 331 }
 332
 333 static u32 vc4_get_fifo_full_level(u32 format)
 334 {
 335         static const u32 fifo_len_bytes = 64;
 336         static const u32 hvs_latency_pix = 6;
 337
 338         switch (format) {
 339         case PV_CONTROL_FORMAT_DSIV_16:
 340         case PV_CONTROL_FORMAT_DSIC_16:
 341                 return fifo_len_bytes - 2 * hvs_latency_pix;
 342         case PV_CONTROL_FORMAT_DSIV_18:
 343                 return fifo_len_bytes - 14;
 344         case PV_CONTROL_FORMAT_24:
 345         case PV_CONTROL_FORMAT_DSIV_24:
 346         default:
 347                 return fifo_len_bytes - 3 * hvs_latency_pix;
 348         }
 349 }
 350
 351 /*
 352  * Returns the encoder attached to the CRTC.
 353  *
 354  * VC4 can only scan out to one encoder at a time, while the DRM core
 355  * allows drivers to push pixels to more than one encoder from the
 356  * same CRTC.
 357  */
 358 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 359 {
 360         struct drm_connector *connector;
 361
 362         drm_for_each_connector(connector, crtc->dev) {
 363                 if (connector->state->crtc == crtc) {
 364                         return connector->encoder;
 365                 }
 366         }
 367
 368         return NULL;
 369 }
 370
 371 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 372 {
 373         struct drm_device *dev = crtc->dev;
 374         struct vc4_dev *vc4 = to_vc4_dev(dev);
 375         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 376         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 377         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 378         struct drm_crtc_state *state = crtc->state;
 379         struct drm_display_mode *mode = &state->adjusted_mode;
 380         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 381         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 382         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 383                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 384         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 385         bool debug_dump_regs = false;
 386
 387         if (debug_dump_regs) {
 388                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 389                 vc4_crtc_dump_regs(vc4_crtc);
 390         }
 391
 392         /* Reset the PV fifo. */
 393         CRTC_WRITE(PV_CONTROL, 0);
 394         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 395         CRTC_WRITE(PV_CONTROL, 0);
 396
 397         CRTC_WRITE(PV_HORZA,
 398                    VC4_SET_FIELD((mode->htotal -
 399                                   mode->hsync_end) * pixel_rep,
 400                                  PV_HORZA_HBP) |
 401                    VC4_SET_FIELD((mode->hsync_end -
 402                                   mode->hsync_start) * pixel_rep,
 403                                  PV_HORZA_HSYNC));
 404         CRTC_WRITE(PV_HORZB,
 405                    VC4_SET_FIELD((mode->hsync_start -
 406                                   mode->hdisplay) * pixel_rep,
 407                                  PV_HORZB_HFP) |
 408                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 409
 410         CRTC_WRITE(PV_VERTA,
 411                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 412                                  PV_VERTA_VBP) |
 413                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 414                                  PV_VERTA_VSYNC));
 415         CRTC_WRITE(PV_VERTB,
 416                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 417                                  PV_VERTB_VFP) |
 418                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 419
 420         if (interlace) {
 421                 CRTC_WRITE(PV_VERTA_EVEN,
 422                            VC4_SET_FIELD(mode->crtc_vtotal -
 423                                          mode->crtc_vsync_end - 1,
 424                                          PV_VERTA_VBP) |
 425                            VC4_SET_FIELD(mode->crtc_vsync_end -
 426                                          mode->crtc_vsync_start,
 427                                          PV_VERTA_VSYNC));
 428                 CRTC_WRITE(PV_VERTB_EVEN,
 429                            VC4_SET_FIELD(mode->crtc_vsync_start -
 430                                          mode->crtc_vdisplay,
 431                                          PV_VERTB_VFP) |
 432                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 433
 434                 /* We set up first field even mode for HDMI.  VEC's
 435                  * NTSC mode would want first field odd instead, once
 436                  * we support it (to do so, set ODD_FIRST and put the
 437                  * delay in VSYNCD_EVEN instead).
 438                  */
 439                 CRTC_WRITE(PV_V_CONTROL,
 440                            PV_VCONTROL_CONTINUOUS |
 441                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 442                            PV_VCONTROL_INTERLACE |
 443                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 444                                          PV_VCONTROL_ODD_DELAY));
 445                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 446         } else {
 447                 CRTC_WRITE(PV_V_CONTROL,
 448                            PV_VCONTROL_CONTINUOUS |
 449                            (is_dsi ? PV_VCONTROL_DSI : 0));
 450         }
 451
 452         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 453
 454         CRTC_WRITE(PV_CONTROL,
 455                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 456                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 457                                  PV_CONTROL_FIFO_LEVEL) |
 458                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 459                    PV_CONTROL_CLR_AT_START |
 460                    PV_CONTROL_TRIGGER_UNDERFLOW |
 461                    PV_CONTROL_WAIT_HSTART |
 462                    VC4_SET_FIELD(vc4_encoder->clock_select,
 463                                  PV_CONTROL_CLK_SELECT) |
 464                    PV_CONTROL_FIFO_CLR |
 465                    PV_CONTROL_EN);
 466
 467         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 468                   SCALER_DISPBKGND_AUTOHS |
 469                   SCALER_DISPBKGND_GAMMA |
 470                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 471
 472         /* Reload the LUT, since the SRAMs would have been disabled if
 473          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 474          */
 475         vc4_crtc_lut_load(crtc);
 476
 477         if (debug_dump_regs) {
 478                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 479                 vc4_crtc_dump_regs(vc4_crtc);
 480         }
 481 }
 482
 483 static void require_hvs_enabled(struct drm_device *dev)
 484 {
 485         struct vc4_dev *vc4 = to_vc4_dev(dev);
 486
 487         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 488                      SCALER_DISPCTRL_ENABLE);
 489 }
 490
 491 static void vc4_crtc_disable(struct drm_crtc *crtc)
 492 {
 493         struct drm_device *dev = crtc->dev;
 494         struct vc4_dev *vc4 = to_vc4_dev(dev);
 495         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 496         u32 chan = vc4_crtc->channel;
 497         int ret;
 498         require_hvs_enabled(dev);
 499
 500         /* Disable vblank irq handling before crtc is disabled. */
 501         drm_crtc_vblank_off(crtc);
 502
 503         CRTC_WRITE(PV_V_CONTROL,
 504                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 505         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 506         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 507
 508         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 509             SCALER_DISPCTRLX_ENABLE) {
 510                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 511                           SCALER_DISPCTRLX_RESET);
 512
 513                 /* While the docs say that reset is self-clearing, it
 514                  * seems it doesn't actually.
 515                  */
 516                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 517         }
 518
 519         /* Once we leave, the scaler should be disabled and its fifo empty. */
 520
 521         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 522
 523         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 524                                    SCALER_DISPSTATX_MODE) !=
 525                      SCALER_DISPSTATX_MODE_DISABLED);
 526
 527         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 528                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 529                      SCALER_DISPSTATX_EMPTY);
 530 }
 531
 532 static void vc4_crtc_enable(struct drm_crtc *crtc)
 533 {
 534         struct drm_device *dev = crtc->dev;
 535         struct vc4_dev *vc4 = to_vc4_dev(dev);
 536         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 537         struct drm_crtc_state *state = crtc->state;
 538         struct drm_display_mode *mode = &state->adjusted_mode;
 539
 540         require_hvs_enabled(dev);
 541
 542         /* Turn on the scaler, which will wait for vstart to start
 543          * compositing.
 544          */
 545         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 546                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 547                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 548                   SCALER_DISPCTRLX_ENABLE);
 549
 550         /* Turn on the pixel valve, which will emit the vstart signal. */
 551         CRTC_WRITE(PV_V_CONTROL,
 552                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 553
 554         /* Enable vblank irq handling after crtc is started. */
 555         drm_crtc_vblank_on(crtc);
 556 }
 557
 558 static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
 559                                 const struct drm_display_mode *mode,
 560                                 struct drm_display_mode *adjusted_mode)
 561 {
 562         /* Do not allow doublescan modes from user space */
 563         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 564                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 565                               crtc->base.id);
 566                 return false;
 567         }
 568
 569         return true;
 570 }
 571
 572 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 573                                  struct drm_crtc_state *state)
 574 {
 575         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 576         struct drm_device *dev = crtc->dev;
 577         struct vc4_dev *vc4 = to_vc4_dev(dev);
 578         struct drm_plane *plane;
 579         unsigned long flags;
 580         const struct drm_plane_state *plane_state;
 581         u32 dlist_count = 0;
 582         int ret;
 583
 584         /* The pixelvalve can only feed one encoder (and encoders are
 585          * 1:1 with connectors.)
 586          */
 587         if (hweight32(state->connector_mask) > 1)
 588                 return -EINVAL;
 589
 590         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 591                 dlist_count += vc4_plane_dlist_size(plane_state);
 592
 593         dlist_count++; /* Account for SCALER_CTL0_END. */
 594
 595         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 596         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 597                                  dlist_count);
 598         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 599         if (ret)
 600                 return ret;
 601
 602         return 0;
 603 }
 604
 605 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 606                                   struct drm_crtc_state *old_state)
 607 {
 608         struct drm_device *dev = crtc->dev;
 609         struct vc4_dev *vc4 = to_vc4_dev(dev);
 610         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 611         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 612         struct drm_plane *plane;
 613         bool debug_dump_regs = false;
 614         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 615         u32 __iomem *dlist_next = dlist_start;
 616
 617         if (debug_dump_regs) {
 618                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 619                 vc4_hvs_dump_state(dev);
 620         }
 621
 622         /* Copy all the active planes' dlist contents to the hardware dlist. */
 623         drm_atomic_crtc_for_each_plane(plane, crtc) {
 624                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 625         }
 626
 627         writel(SCALER_CTL0_END, dlist_next);
 628         dlist_next++;
 629
 630         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 631
 632         if (crtc->state->event) {
 633                 unsigned long flags;
 634
 635                 crtc->state->event->pipe = drm_crtc_index(crtc);
 636
 637                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 638
 639                 spin_lock_irqsave(&dev->event_lock, flags);
 640                 vc4_crtc->event = crtc->state->event;
 641                 crtc->state->event = NULL;
 642
 643                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 644                           vc4_state->mm.start);
 645
 646                 spin_unlock_irqrestore(&dev->event_lock, flags);
 647         } else {
 648                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 649                           vc4_state->mm.start);
 650         }
 651
 652         if (debug_dump_regs) {
 653                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 654                 vc4_hvs_dump_state(dev);
 655         }
 656 }
 657
 658 static int vc4_enable_vblank(struct drm_crtc *crtc)
 659 {
 660         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 661
 662         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 663
 664         return 0;
 665 }
 666
 667 static void vc4_disable_vblank(struct drm_crtc *crtc)
 668 {
 669         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 670
 671         CRTC_WRITE(PV_INTEN, 0);
 672 }
 673
 674 /* Must be called with the event lock held */
 675 bool vc4_event_pending(struct drm_crtc *crtc)
 676 {
 677         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 678
 679         return !!vc4_crtc->event;
 680 }
 681
 682 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 683 {
 684         struct drm_crtc *crtc = &vc4_crtc->base;
 685         struct drm_device *dev = crtc->dev;
 686         struct vc4_dev *vc4 = to_vc4_dev(dev);
 687         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 688         u32 chan = vc4_crtc->channel;
 689         unsigned long flags;
 690
 691         spin_lock_irqsave(&dev->event_lock, flags);
 692         if (vc4_crtc->event &&
 693             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
 694                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 695                 vc4_crtc->event = NULL;
 696                 drm_crtc_vblank_put(crtc);
 697         }
 698         spin_unlock_irqrestore(&dev->event_lock, flags);
 699 }
 700
 701 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 702 {
 703         struct vc4_crtc *vc4_crtc = data;
 704         u32 stat = CRTC_READ(PV_INTSTAT);
 705         irqreturn_t ret = IRQ_NONE;
 706
 707         if (stat & PV_INT_VFP_START) {
 708                 vc4_crtc->t_vblank = ktime_get();
 709                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 710                 drm_crtc_handle_vblank(&vc4_crtc->base);
 711                 vc4_crtc_handle_page_flip(vc4_crtc);
 712                 ret = IRQ_HANDLED;
 713         }
 714
 715         return ret;
 716 }
 717
 718 struct vc4_async_flip_state {
 719         struct drm_crtc *crtc;
 720         struct drm_framebuffer *fb;
 721         struct drm_pending_vblank_event *event;
 722
 723         struct vc4_seqno_cb cb;
 724 };
 725
 726 /* Called when the V3D execution for the BO being flipped to is done, so that
 727  * we can actually update the plane's address to point to it.
 728  */
 729 static void
 730 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 731 {
 732         struct vc4_async_flip_state *flip_state =
 733                 container_of(cb, struct vc4_async_flip_state, cb);
 734         struct drm_crtc *crtc = flip_state->crtc;
 735         struct drm_device *dev = crtc->dev;
 736         struct vc4_dev *vc4 = to_vc4_dev(dev);
 737         struct drm_plane *plane = crtc->primary;
 738
 739         vc4_plane_async_set_fb(plane, flip_state->fb);
 740         if (flip_state->event) {
 741                 unsigned long flags;
 742
 743                 spin_lock_irqsave(&dev->event_lock, flags);
 744                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 745                 spin_unlock_irqrestore(&dev->event_lock, flags);
 746         }
 747
 748         drm_crtc_vblank_put(crtc);
 749         drm_framebuffer_unreference(flip_state->fb);
 750         kfree(flip_state);
 751
 752         up(&vc4->async_modeset);
 753 }
 754
 755 /* Implements async (non-vblank-synced) page flips.
 756  *
 757  * The page flip ioctl needs to return immediately, so we grab the
 758  * modeset semaphore on the pipe, and queue the address update for
 759  * when V3D is done with the BO being flipped to.
 760  */
 761 static int vc4_async_page_flip(struct drm_crtc *crtc,
 762                                struct drm_framebuffer *fb,
 763                                struct drm_pending_vblank_event *event,
 764                                uint32_t flags)
 765 {
 766         struct drm_device *dev = crtc->dev;
 767         struct vc4_dev *vc4 = to_vc4_dev(dev);
 768         struct drm_plane *plane = crtc->primary;
 769         int ret = 0;
 770         struct vc4_async_flip_state *flip_state;
 771         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 772         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 773
 774         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 775         if (!flip_state)
 776                 return -ENOMEM;
 777
 778         drm_framebuffer_reference(fb);
 779         flip_state->fb = fb;
 780         flip_state->crtc = crtc;
 781         flip_state->event = event;
 782
 783         /* Make sure all other async modesetes have landed. */
 784         ret = down_interruptible(&vc4->async_modeset);
 785         if (ret) {
 786                 drm_framebuffer_unreference(fb);
 787                 kfree(flip_state);
 788                 return ret;
 789         }
 790
 791         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 792
 793         /* Immediately update the plane's legacy fb pointer, so that later
 794          * modeset prep sees the state that will be present when the semaphore
 795          * is released.
 796          */
 797         drm_atomic_set_fb_for_plane(plane->state, fb);
 798         plane->fb = fb;
 799
 800         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 801                            vc4_async_page_flip_complete);
 802
 803         /* Driver takes ownership of state on successful async commit. */
 804         return 0;
 805 }
 806
 807 static int vc4_page_flip(struct drm_crtc *crtc,
 808                          struct drm_framebuffer *fb,
 809                          struct drm_pending_vblank_event *event,
 810                          uint32_t flags,
 811                          struct drm_modeset_acquire_ctx *ctx)
 812 {
 813         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 814                 return vc4_async_page_flip(crtc, fb, event, flags);
 815         else
 816                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 817 }
 818
 819 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 820 {
 821         struct vc4_crtc_state *vc4_state;
 822
 823         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 824         if (!vc4_state)
 825                 return NULL;
 826
 827         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 828         return &vc4_state->base;
 829 }
 830
 831 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 832                                    struct drm_crtc_state *state)
 833 {
 834         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 835         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 836
 837         if (vc4_state->mm.allocated) {
 838                 unsigned long flags;
 839
 840                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 841                 drm_mm_remove_node(&vc4_state->mm);
 842                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 843
 844         }
 845
 846         drm_atomic_helper_crtc_destroy_state(crtc, state);
 847 }
 848
 849 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 850         .set_config = drm_atomic_helper_set_config,
 851         .destroy = vc4_crtc_destroy,
 852         .page_flip = vc4_page_flip,
 853         .set_property = NULL,
 854         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 855         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 856         .reset = drm_atomic_helper_crtc_reset,
 857         .atomic_duplicate_state = vc4_crtc_duplicate_state,
 858         .atomic_destroy_state = vc4_crtc_destroy_state,
 859         .gamma_set = vc4_crtc_gamma_set,
 860         .enable_vblank = vc4_enable_vblank,
 861         .disable_vblank = vc4_disable_vblank,
 862 };
 863
 864 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 865         .mode_set_nofb = vc4_crtc_mode_set_nofb,
 866         .disable = vc4_crtc_disable,
 867         .enable = vc4_crtc_enable,
 868         .mode_fixup = vc4_crtc_mode_fixup,
 869         .atomic_check = vc4_crtc_atomic_check,
 870         .atomic_flush = vc4_crtc_atomic_flush,
 871 };
 872
 873 static const struct vc4_crtc_data pv0_data = {
 874         .hvs_channel = 0,
 875         .encoder_types = {
 876                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
 877                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
 878         },
 879 };
 880
 881 static const struct vc4_crtc_data pv1_data = {
 882         .hvs_channel = 2,
 883         .encoder_types = {
 884                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
 885                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
 886         },
 887 };
 888
 889 static const struct vc4_crtc_data pv2_data = {
 890         .hvs_channel = 1,
 891         .encoder_types = {
 892                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
 893                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
 894         },
 895 };
 896
 897 static const struct of_device_id vc4_crtc_dt_match[] = {
 898         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
 899         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
 900         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
 901         {}
 902 };
 903
 904 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
 905                                         struct drm_crtc *crtc)
 906 {
 907         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 908         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
 909         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
 910         struct drm_encoder *encoder;
 911
 912         drm_for_each_encoder(encoder, drm) {
 913                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 914                 int i;
 915
 916                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
 917                         if (vc4_encoder->type == encoder_types[i]) {
 918                                 vc4_encoder->clock_select = i;
 919                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
 920                                 break;
 921                         }
 922                 }
 923         }
 924 }
 925
 926 static void
 927 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
 928 {
 929         struct drm_device *drm = vc4_crtc->base.dev;
 930         struct vc4_dev *vc4 = to_vc4_dev(drm);
 931         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
 932         /* Top/base are supposed to be 4-pixel aligned, but the
 933          * Raspberry Pi firmware fills the low bits (which are
 934          * presumably ignored).
 935          */
 936         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
 937         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
 938
 939         vc4_crtc->cob_size = top - base + 4;
 940 }
 941
 942 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
 943 {
 944         struct platform_device *pdev = to_platform_device(dev);
 945         struct drm_device *drm = dev_get_drvdata(master);
 946         struct vc4_crtc *vc4_crtc;
 947         struct drm_crtc *crtc;
 948         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
 949         const struct of_device_id *match;
 950         int ret, i;
 951
 952         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
 953         if (!vc4_crtc)
 954                 return -ENOMEM;
 955         crtc = &vc4_crtc->base;
 956
 957         match = of_match_device(vc4_crtc_dt_match, dev);
 958         if (!match)
 959                 return -ENODEV;
 960         vc4_crtc->data = match->data;
 961
 962         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
 963         if (IS_ERR(vc4_crtc->regs))
 964                 return PTR_ERR(vc4_crtc->regs);
 965
 966         /* For now, we create just the primary and the legacy cursor
 967          * planes.  We should be able to stack more planes on easily,
 968          * but to do that we would need to compute the bandwidth
 969          * requirement of the plane configuration, and reject ones
 970          * that will take too much.
 971          */
 972         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
 973         if (IS_ERR(primary_plane)) {
 974                 dev_err(dev, "failed to construct primary plane\n");
 975                 ret = PTR_ERR(primary_plane);
 976                 goto err;
 977         }
 978
 979         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
 980                                   &vc4_crtc_funcs, NULL);
 981         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
 982         primary_plane->crtc = crtc;
 983         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
 984         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
 985
 986         /* Set up some arbitrary number of planes.  We're not limited
 987          * by a set number of physical registers, just the space in
 988          * the HVS (16k) and how small an plane can be (28 bytes).
 989          * However, each plane we set up takes up some memory, and
 990          * increases the cost of looping over planes, which atomic
 991          * modesetting does quite a bit.  As a result, we pick a
 992          * modest number of planes to expose, that should hopefully
 993          * still cover any sane usecase.
 994          */
 995         for (i = 0; i < 8; i++) {
 996                 struct drm_plane *plane =
 997                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
 998
 999                 if (IS_ERR(plane))
1000                         continue;
1001
1002                 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1003         }
1004
1005         /* Set up the legacy cursor after overlay initialization,
1006          * since we overlay planes on the CRTC in the order they were
1007          * initialized.
1008          */
1009         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1010         if (!IS_ERR(cursor_plane)) {
1011                 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1012                 cursor_plane->crtc = crtc;
1013                 crtc->cursor = cursor_plane;
1014         }
1015
1016         vc4_crtc_get_cob_allocation(vc4_crtc);
1017
1018         CRTC_WRITE(PV_INTEN, 0);
1019         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1020         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1021                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1022         if (ret)
1023                 goto err_destroy_planes;
1024
1025         vc4_set_crtc_possible_masks(drm, crtc);
1026
1027         for (i = 0; i < crtc->gamma_size; i++) {
1028                 vc4_crtc->lut_r[i] = i;
1029                 vc4_crtc->lut_g[i] = i;
1030                 vc4_crtc->lut_b[i] = i;
1031         }
1032
1033         platform_set_drvdata(pdev, vc4_crtc);
1034
1035         return 0;
1036
1037 err_destroy_planes:
1038         list_for_each_entry_safe(destroy_plane, temp,
1039                                  &drm->mode_config.plane_list, head) {
1040                 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1041                     destroy_plane->funcs->destroy(destroy_plane);
1042         }
1043 err:
1044         return ret;
1045 }
1046
1047 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1048                             void *data)
1049 {
1050         struct platform_device *pdev = to_platform_device(dev);
1051         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1052
1053         vc4_crtc_destroy(&vc4_crtc->base);
1054
1055         CRTC_WRITE(PV_INTEN, 0);
1056
1057         platform_set_drvdata(pdev, NULL);
1058 }
1059
1060 static const struct component_ops vc4_crtc_ops = {
1061         .bind   = vc4_crtc_bind,
1062         .unbind = vc4_crtc_unbind,
1063 };
1064
1065 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1066 {
1067         return component_add(&pdev->dev, &vc4_crtc_ops);
1068 }
1069
1070 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1071 {
1072         component_del(&pdev->dev, &vc4_crtc_ops);
1073         return 0;
1074 }
1075
1076 struct platform_driver vc4_crtc_driver = {
1077         .probe = vc4_crtc_dev_probe,
1078         .remove = vc4_crtc_dev_remove,
1079         .driver = {
1080                 .name = "vc4_crtc",
1081                 .of_match_table = vc4_crtc_dt_match,
1082         },
1083 };