drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * output's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, this file also manages
  19  * setup of the VC4 HVS's display elements on the CRTC.
  20  *
  21  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  22  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  23  * image domain can feed either HDMI or the SDTV controller.  The
  24  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  25  * SDTV, etc.) according to which output type is chosen in the mux.
  26  *
  27  * For power management, the pixel valve's registers are all clocked
  28  * by the AXI clock, while the timings and FIFOs make use of the
  29  * output-specific clock.  Since the encoders also directly consume
  30  * the CPRMAN clocks, and know what timings they need, they are the
  31  * ones that set the clock.
  32  */
  33
  34 #include "drm_atomic.h"
  35 #include "drm_atomic_helper.h"
  36 #include "drm_crtc_helper.h"
  37 #include "linux/clk.h"
  38 #include "drm_fb_cma_helper.h"
  39 #include "linux/component.h"
  40 #include "linux/of_device.h"
  41 #include "vc4_drv.h"
  42 #include "vc4_regs.h"
  43
  44 struct vc4_crtc {
  45         struct drm_crtc base;
  46         const struct vc4_crtc_data *data;
  47         void __iomem *regs;
  48
  49         /* Timestamp at start of vblank irq - unaffected by lock delays. */
  50         ktime_t t_vblank;
  51
  52         /* Which HVS channel we're using for our CRTC. */
  53         int channel;
  54
  55         u8 lut_r[256];
  56         u8 lut_g[256];
  57         u8 lut_b[256];
  58         /* Size in pixels of the COB memory allocated to this CRTC. */
  59         u32 cob_size;
  60
  61         struct drm_pending_vblank_event *event;
  62 };
  63
  64 struct vc4_crtc_state {
  65         struct drm_crtc_state base;
  66         /* Dlist area for this CRTC configuration. */
  67         struct drm_mm_node mm;
  68 };
  69
  70 static inline struct vc4_crtc *
  71 to_vc4_crtc(struct drm_crtc *crtc)
  72 {
  73         return (struct vc4_crtc *)crtc;
  74 }
  75
  76 static inline struct vc4_crtc_state *
  77 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  78 {
  79         return (struct vc4_crtc_state *)crtc_state;
  80 }
  81
  82 struct vc4_crtc_data {
  83         /* Which channel of the HVS this pixelvalve sources from. */
  84         int hvs_channel;
  85
  86         enum vc4_encoder_type encoder_types[4];
  87 };
  88
  89 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  90 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  91
  92 #define CRTC_REG(reg) { reg, #reg }
  93 static const struct {
  94         u32 reg;
  95         const char *name;
  96 } crtc_regs[] = {
  97         CRTC_REG(PV_CONTROL),
  98         CRTC_REG(PV_V_CONTROL),
  99         CRTC_REG(PV_VSYNCD_EVEN),
 100         CRTC_REG(PV_HORZA),
 101         CRTC_REG(PV_HORZB),
 102         CRTC_REG(PV_VERTA),
 103         CRTC_REG(PV_VERTB),
 104         CRTC_REG(PV_VERTA_EVEN),
 105         CRTC_REG(PV_VERTB_EVEN),
 106         CRTC_REG(PV_INTEN),
 107         CRTC_REG(PV_INTSTAT),
 108         CRTC_REG(PV_STAT),
 109         CRTC_REG(PV_HACT_ACT),
 110 };
 111
 112 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
 113 {
 114         int i;
 115
 116         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 117                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 118                          crtc_regs[i].reg, crtc_regs[i].name,
 119                          CRTC_READ(crtc_regs[i].reg));
 120         }
 121 }
 122
 123 #ifdef CONFIG_DEBUG_FS
 124 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 125 {
 126         struct drm_info_node *node = (struct drm_info_node *)m->private;
 127         struct drm_device *dev = node->minor->dev;
 128         int crtc_index = (uintptr_t)node->info_ent->data;
 129         struct drm_crtc *crtc;
 130         struct vc4_crtc *vc4_crtc;
 131         int i;
 132
 133         i = 0;
 134         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 135                 if (i == crtc_index)
 136                         break;
 137                 i++;
 138         }
 139         if (!crtc)
 140                 return 0;
 141         vc4_crtc = to_vc4_crtc(crtc);
 142
 143         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 144                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 145                            crtc_regs[i].name, crtc_regs[i].reg,
 146                            CRTC_READ(crtc_regs[i].reg));
 147         }
 148
 149         return 0;
 150 }
 151 #endif
 152
 153 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 154                             unsigned int flags, int *vpos, int *hpos,
 155                             ktime_t *stime, ktime_t *etime,
 156                             const struct drm_display_mode *mode)
 157 {
 158         struct vc4_dev *vc4 = to_vc4_dev(dev);
 159         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 160         u32 val;
 161         int fifo_lines;
 162         int vblank_lines;
 163         int ret = 0;
 164
 165         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 166
 167         /* Get optional system timestamp before query. */
 168         if (stime)
 169                 *stime = ktime_get();
 170
 171         /*
 172          * Read vertical scanline which is currently composed for our
 173          * pixelvalve by the HVS, and also the scaler status.
 174          */
 175         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 176
 177         /* Get optional system timestamp after query. */
 178         if (etime)
 179                 *etime = ktime_get();
 180
 181         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 182
 183         /* Vertical position of hvs composed scanline. */
 184         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 185         *hpos = 0;
 186
 187         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 188                 *vpos /= 2;
 189
 190                 /* Use hpos to correct for field offset in interlaced mode. */
 191                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 192                         *hpos += mode->crtc_htotal / 2;
 193         }
 194
 195         /* This is the offset we need for translating hvs -> pv scanout pos. */
 196         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 197
 198         if (fifo_lines > 0)
 199                 ret |= DRM_SCANOUTPOS_VALID;
 200
 201         /* HVS more than fifo_lines into frame for compositing? */
 202         if (*vpos > fifo_lines) {
 203                 /*
 204                  * We are in active scanout and can get some meaningful results
 205                  * from HVS. The actual PV scanout can not trail behind more
 206                  * than fifo_lines as that is the fifo's capacity. Assume that
 207                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 208                  * refilling the fifo and PV consuming from the fifo, ie.
 209                  * whenever the PV consumes and frees up a scanline in the
 210                  * fifo, the HVS will immediately refill it, therefore
 211                  * incrementing vpos. Therefore we choose HVS read position -
 212                  * fifo size in scanlines as a estimate of the real scanout
 213                  * position of the PV.
 214                  */
 215                 *vpos -= fifo_lines + 1;
 216
 217                 ret |= DRM_SCANOUTPOS_ACCURATE;
 218                 return ret;
 219         }
 220
 221         /*
 222          * Less: This happens when we are in vblank and the HVS, after getting
 223          * the VSTART restart signal from the PV, just started refilling its
 224          * fifo with new lines from the top-most lines of the new framebuffers.
 225          * The PV does not scan out in vblank, so does not remove lines from
 226          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 227          * We can't get meaningful readings wrt. scanline position of the PV
 228          * and need to make things up in a approximative but consistent way.
 229          */
 230         ret |= DRM_SCANOUTPOS_IN_VBLANK;
 231         vblank_lines = mode->vtotal - mode->vdisplay;
 232
 233         if (flags & DRM_CALLED_FROM_VBLIRQ) {
 234                 /*
 235                  * Assume the irq handler got called close to first
 236                  * line of vblank, so PV has about a full vblank
 237                  * scanlines to go, and as a base timestamp use the
 238                  * one taken at entry into vblank irq handler, so it
 239                  * is not affected by random delays due to lock
 240                  * contention on event_lock or vblank_time lock in
 241                  * the core.
 242                  */
 243                 *vpos = -vblank_lines;
 244
 245                 if (stime)
 246                         *stime = vc4_crtc->t_vblank;
 247                 if (etime)
 248                         *etime = vc4_crtc->t_vblank;
 249
 250                 /*
 251                  * If the HVS fifo is not yet full then we know for certain
 252                  * we are at the very beginning of vblank, as the hvs just
 253                  * started refilling, and the stime and etime timestamps
 254                  * truly correspond to start of vblank.
 255                  */
 256                 if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL)
 257                         ret |= DRM_SCANOUTPOS_ACCURATE;
 258         } else {
 259                 /*
 260                  * No clue where we are inside vblank. Return a vpos of zero,
 261                  * which will cause calling code to just return the etime
 262                  * timestamp uncorrected. At least this is no worse than the
 263                  * standard fallback.
 264                  */
 265                 *vpos = 0;
 266         }
 267
 268         return ret;
 269 }
 270
 271 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
 272                                   int *max_error, struct timeval *vblank_time,
 273                                   unsigned flags)
 274 {
 275         struct vc4_dev *vc4 = to_vc4_dev(dev);
 276         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 277         struct drm_crtc *crtc = &vc4_crtc->base;
 278         struct drm_crtc_state *state = crtc->state;
 279
 280         /* Helper routine in DRM core does all the work: */
 281         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error,
 282                                                      vblank_time, flags,
 283                                                      &state->adjusted_mode);
 284 }
 285
 286 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 287 {
 288         drm_crtc_cleanup(crtc);
 289 }
 290
 291 static void
 292 vc4_crtc_lut_load(struct drm_crtc *crtc)
 293 {
 294         struct drm_device *dev = crtc->dev;
 295         struct vc4_dev *vc4 = to_vc4_dev(dev);
 296         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 297         u32 i;
 298
 299         /* The LUT memory is laid out with each HVS channel in order,
 300          * each of which takes 256 writes for R, 256 for G, then 256
 301          * for B.
 302          */
 303         HVS_WRITE(SCALER_GAMADDR,
 304                   SCALER_GAMADDR_AUTOINC |
 305                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 306
 307         for (i = 0; i < crtc->gamma_size; i++)
 308                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 309         for (i = 0; i < crtc->gamma_size; i++)
 310                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 311         for (i = 0; i < crtc->gamma_size; i++)
 312                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 313 }
 314
 315 static int
 316 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 317                    uint32_t size)
 318 {
 319         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 320         u32 i;
 321
 322         for (i = 0; i < size; i++) {
 323                 vc4_crtc->lut_r[i] = r[i] >> 8;
 324                 vc4_crtc->lut_g[i] = g[i] >> 8;
 325                 vc4_crtc->lut_b[i] = b[i] >> 8;
 326         }
 327
 328         vc4_crtc_lut_load(crtc);
 329
 330         return 0;
 331 }
 332
 333 static u32 vc4_get_fifo_full_level(u32 format)
 334 {
 335         static const u32 fifo_len_bytes = 64;
 336         static const u32 hvs_latency_pix = 6;
 337
 338         switch (format) {
 339         case PV_CONTROL_FORMAT_DSIV_16:
 340         case PV_CONTROL_FORMAT_DSIC_16:
 341                 return fifo_len_bytes - 2 * hvs_latency_pix;
 342         case PV_CONTROL_FORMAT_DSIV_18:
 343                 return fifo_len_bytes - 14;
 344         case PV_CONTROL_FORMAT_24:
 345         case PV_CONTROL_FORMAT_DSIV_24:
 346         default:
 347                 return fifo_len_bytes - 3 * hvs_latency_pix;
 348         }
 349 }
 350
 351 /*
 352  * Returns the clock select bit for the connector attached to the
 353  * CRTC.
 354  */
 355 static int vc4_get_clock_select(struct drm_crtc *crtc)
 356 {
 357         struct drm_connector *connector;
 358
 359         drm_for_each_connector(connector, crtc->dev) {
 360                 if (connector->state->crtc == crtc) {
 361                         struct drm_encoder *encoder = connector->encoder;
 362                         struct vc4_encoder *vc4_encoder =
 363                                 to_vc4_encoder(encoder);
 364
 365                         return vc4_encoder->clock_select;
 366                 }
 367         }
 368
 369         return -1;
 370 }
 371
 372 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 373 {
 374         struct drm_device *dev = crtc->dev;
 375         struct vc4_dev *vc4 = to_vc4_dev(dev);
 376         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 377         struct drm_crtc_state *state = crtc->state;
 378         struct drm_display_mode *mode = &state->adjusted_mode;
 379         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 380         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 381         u32 format = PV_CONTROL_FORMAT_24;
 382         bool debug_dump_regs = false;
 383         int clock_select = vc4_get_clock_select(crtc);
 384
 385         if (debug_dump_regs) {
 386                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 387                 vc4_crtc_dump_regs(vc4_crtc);
 388         }
 389
 390         /* Reset the PV fifo. */
 391         CRTC_WRITE(PV_CONTROL, 0);
 392         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 393         CRTC_WRITE(PV_CONTROL, 0);
 394
 395         CRTC_WRITE(PV_HORZA,
 396                    VC4_SET_FIELD((mode->htotal -
 397                                   mode->hsync_end) * pixel_rep,
 398                                  PV_HORZA_HBP) |
 399                    VC4_SET_FIELD((mode->hsync_end -
 400                                   mode->hsync_start) * pixel_rep,
 401                                  PV_HORZA_HSYNC));
 402         CRTC_WRITE(PV_HORZB,
 403                    VC4_SET_FIELD((mode->hsync_start -
 404                                   mode->hdisplay) * pixel_rep,
 405                                  PV_HORZB_HFP) |
 406                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 407
 408         CRTC_WRITE(PV_VERTA,
 409                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 410                                  PV_VERTA_VBP) |
 411                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 412                                  PV_VERTA_VSYNC));
 413         CRTC_WRITE(PV_VERTB,
 414                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 415                                  PV_VERTB_VFP) |
 416                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 417
 418         if (interlace) {
 419                 CRTC_WRITE(PV_VERTA_EVEN,
 420                            VC4_SET_FIELD(mode->crtc_vtotal -
 421                                          mode->crtc_vsync_end - 1,
 422                                          PV_VERTA_VBP) |
 423                            VC4_SET_FIELD(mode->crtc_vsync_end -
 424                                          mode->crtc_vsync_start,
 425                                          PV_VERTA_VSYNC));
 426                 CRTC_WRITE(PV_VERTB_EVEN,
 427                            VC4_SET_FIELD(mode->crtc_vsync_start -
 428                                          mode->crtc_vdisplay,
 429                                          PV_VERTB_VFP) |
 430                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 431
 432                 /* We set up first field even mode for HDMI.  VEC's
 433                  * NTSC mode would want first field odd instead, once
 434                  * we support it (to do so, set ODD_FIRST and put the
 435                  * delay in VSYNCD_EVEN instead).
 436                  */
 437                 CRTC_WRITE(PV_V_CONTROL,
 438                            PV_VCONTROL_CONTINUOUS |
 439                            PV_VCONTROL_INTERLACE |
 440                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 441                                          PV_VCONTROL_ODD_DELAY));
 442                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 443         } else {
 444                 CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS);
 445         }
 446
 447         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 448
 449
 450         CRTC_WRITE(PV_CONTROL,
 451                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 452                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 453                                  PV_CONTROL_FIFO_LEVEL) |
 454                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 455                    PV_CONTROL_CLR_AT_START |
 456                    PV_CONTROL_TRIGGER_UNDERFLOW |
 457                    PV_CONTROL_WAIT_HSTART |
 458                    VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
 459                    PV_CONTROL_FIFO_CLR |
 460                    PV_CONTROL_EN);
 461
 462         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 463                   SCALER_DISPBKGND_AUTOHS |
 464                   SCALER_DISPBKGND_GAMMA |
 465                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 466
 467         /* Reload the LUT, since the SRAMs would have been disabled if
 468          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 469          */
 470         vc4_crtc_lut_load(crtc);
 471
 472         if (debug_dump_regs) {
 473                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 474                 vc4_crtc_dump_regs(vc4_crtc);
 475         }
 476 }
 477
 478 static void require_hvs_enabled(struct drm_device *dev)
 479 {
 480         struct vc4_dev *vc4 = to_vc4_dev(dev);
 481
 482         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 483                      SCALER_DISPCTRL_ENABLE);
 484 }
 485
 486 static void vc4_crtc_disable(struct drm_crtc *crtc)
 487 {
 488         struct drm_device *dev = crtc->dev;
 489         struct vc4_dev *vc4 = to_vc4_dev(dev);
 490         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 491         u32 chan = vc4_crtc->channel;
 492         int ret;
 493         require_hvs_enabled(dev);
 494
 495         /* Disable vblank irq handling before crtc is disabled. */
 496         drm_crtc_vblank_off(crtc);
 497
 498         CRTC_WRITE(PV_V_CONTROL,
 499                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 500         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 501         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 502
 503         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 504             SCALER_DISPCTRLX_ENABLE) {
 505                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 506                           SCALER_DISPCTRLX_RESET);
 507
 508                 /* While the docs say that reset is self-clearing, it
 509                  * seems it doesn't actually.
 510                  */
 511                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 512         }
 513
 514         /* Once we leave, the scaler should be disabled and its fifo empty. */
 515
 516         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 517
 518         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 519                                    SCALER_DISPSTATX_MODE) !=
 520                      SCALER_DISPSTATX_MODE_DISABLED);
 521
 522         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 523                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 524                      SCALER_DISPSTATX_EMPTY);
 525 }
 526
 527 static void vc4_crtc_enable(struct drm_crtc *crtc)
 528 {
 529         struct drm_device *dev = crtc->dev;
 530         struct vc4_dev *vc4 = to_vc4_dev(dev);
 531         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 532         struct drm_crtc_state *state = crtc->state;
 533         struct drm_display_mode *mode = &state->adjusted_mode;
 534
 535         require_hvs_enabled(dev);
 536
 537         /* Turn on the scaler, which will wait for vstart to start
 538          * compositing.
 539          */
 540         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 541                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 542                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 543                   SCALER_DISPCTRLX_ENABLE);
 544
 545         /* Turn on the pixel valve, which will emit the vstart signal. */
 546         CRTC_WRITE(PV_V_CONTROL,
 547                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 548
 549         /* Enable vblank irq handling after crtc is started. */
 550         drm_crtc_vblank_on(crtc);
 551 }
 552
 553 static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
 554                                 const struct drm_display_mode *mode,
 555                                 struct drm_display_mode *adjusted_mode)
 556 {
 557         /* Do not allow doublescan modes from user space */
 558         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 559                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 560                               crtc->base.id);
 561                 return false;
 562         }
 563
 564         return true;
 565 }
 566
 567 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 568                                  struct drm_crtc_state *state)
 569 {
 570         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 571         struct drm_device *dev = crtc->dev;
 572         struct vc4_dev *vc4 = to_vc4_dev(dev);
 573         struct drm_plane *plane;
 574         unsigned long flags;
 575         const struct drm_plane_state *plane_state;
 576         u32 dlist_count = 0;
 577         int ret;
 578
 579         /* The pixelvalve can only feed one encoder (and encoders are
 580          * 1:1 with connectors.)
 581          */
 582         if (hweight32(state->connector_mask) > 1)
 583                 return -EINVAL;
 584
 585         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 586                 dlist_count += vc4_plane_dlist_size(plane_state);
 587
 588         dlist_count++; /* Account for SCALER_CTL0_END. */
 589
 590         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 591         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 592                                  dlist_count, 1, 0);
 593         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 594         if (ret)
 595                 return ret;
 596
 597         return 0;
 598 }
 599
 600 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 601                                   struct drm_crtc_state *old_state)
 602 {
 603         struct drm_device *dev = crtc->dev;
 604         struct vc4_dev *vc4 = to_vc4_dev(dev);
 605         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 606         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 607         struct drm_plane *plane;
 608         bool debug_dump_regs = false;
 609         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 610         u32 __iomem *dlist_next = dlist_start;
 611
 612         if (debug_dump_regs) {
 613                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 614                 vc4_hvs_dump_state(dev);
 615         }
 616
 617         /* Copy all the active planes' dlist contents to the hardware dlist. */
 618         drm_atomic_crtc_for_each_plane(plane, crtc) {
 619                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 620         }
 621
 622         writel(SCALER_CTL0_END, dlist_next);
 623         dlist_next++;
 624
 625         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 626
 627         if (crtc->state->event) {
 628                 unsigned long flags;
 629
 630                 crtc->state->event->pipe = drm_crtc_index(crtc);
 631
 632                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 633
 634                 spin_lock_irqsave(&dev->event_lock, flags);
 635                 vc4_crtc->event = crtc->state->event;
 636                 crtc->state->event = NULL;
 637
 638                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 639                           vc4_state->mm.start);
 640
 641                 spin_unlock_irqrestore(&dev->event_lock, flags);
 642         } else {
 643                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 644                           vc4_state->mm.start);
 645         }
 646
 647         if (debug_dump_regs) {
 648                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 649                 vc4_hvs_dump_state(dev);
 650         }
 651 }
 652
 653 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
 654 {
 655         struct vc4_dev *vc4 = to_vc4_dev(dev);
 656         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 657
 658         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 659
 660         return 0;
 661 }
 662
 663 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
 664 {
 665         struct vc4_dev *vc4 = to_vc4_dev(dev);
 666         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 667
 668         CRTC_WRITE(PV_INTEN, 0);
 669 }
 670
 671 /* Must be called with the event lock held */
 672 bool vc4_event_pending(struct drm_crtc *crtc)
 673 {
 674         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 675
 676         return !!vc4_crtc->event;
 677 }
 678
 679 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 680 {
 681         struct drm_crtc *crtc = &vc4_crtc->base;
 682         struct drm_device *dev = crtc->dev;
 683         struct vc4_dev *vc4 = to_vc4_dev(dev);
 684         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 685         u32 chan = vc4_crtc->channel;
 686         unsigned long flags;
 687
 688         spin_lock_irqsave(&dev->event_lock, flags);
 689         if (vc4_crtc->event &&
 690             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
 691                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 692                 vc4_crtc->event = NULL;
 693                 drm_crtc_vblank_put(crtc);
 694         }
 695         spin_unlock_irqrestore(&dev->event_lock, flags);
 696 }
 697
 698 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 699 {
 700         struct vc4_crtc *vc4_crtc = data;
 701         u32 stat = CRTC_READ(PV_INTSTAT);
 702         irqreturn_t ret = IRQ_NONE;
 703
 704         if (stat & PV_INT_VFP_START) {
 705                 vc4_crtc->t_vblank = ktime_get();
 706                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 707                 drm_crtc_handle_vblank(&vc4_crtc->base);
 708                 vc4_crtc_handle_page_flip(vc4_crtc);
 709                 ret = IRQ_HANDLED;
 710         }
 711
 712         return ret;
 713 }
 714
 715 struct vc4_async_flip_state {
 716         struct drm_crtc *crtc;
 717         struct drm_framebuffer *fb;
 718         struct drm_pending_vblank_event *event;
 719
 720         struct vc4_seqno_cb cb;
 721 };
 722
 723 /* Called when the V3D execution for the BO being flipped to is done, so that
 724  * we can actually update the plane's address to point to it.
 725  */
 726 static void
 727 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 728 {
 729         struct vc4_async_flip_state *flip_state =
 730                 container_of(cb, struct vc4_async_flip_state, cb);
 731         struct drm_crtc *crtc = flip_state->crtc;
 732         struct drm_device *dev = crtc->dev;
 733         struct vc4_dev *vc4 = to_vc4_dev(dev);
 734         struct drm_plane *plane = crtc->primary;
 735
 736         vc4_plane_async_set_fb(plane, flip_state->fb);
 737         if (flip_state->event) {
 738                 unsigned long flags;
 739
 740                 spin_lock_irqsave(&dev->event_lock, flags);
 741                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 742                 spin_unlock_irqrestore(&dev->event_lock, flags);
 743         }
 744
 745         drm_crtc_vblank_put(crtc);
 746         drm_framebuffer_unreference(flip_state->fb);
 747         kfree(flip_state);
 748
 749         up(&vc4->async_modeset);
 750 }
 751
 752 /* Implements async (non-vblank-synced) page flips.
 753  *
 754  * The page flip ioctl needs to return immediately, so we grab the
 755  * modeset semaphore on the pipe, and queue the address update for
 756  * when V3D is done with the BO being flipped to.
 757  */
 758 static int vc4_async_page_flip(struct drm_crtc *crtc,
 759                                struct drm_framebuffer *fb,
 760                                struct drm_pending_vblank_event *event,
 761                                uint32_t flags)
 762 {
 763         struct drm_device *dev = crtc->dev;
 764         struct vc4_dev *vc4 = to_vc4_dev(dev);
 765         struct drm_plane *plane = crtc->primary;
 766         int ret = 0;
 767         struct vc4_async_flip_state *flip_state;
 768         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 769         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 770
 771         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 772         if (!flip_state)
 773                 return -ENOMEM;
 774
 775         drm_framebuffer_reference(fb);
 776         flip_state->fb = fb;
 777         flip_state->crtc = crtc;
 778         flip_state->event = event;
 779
 780         /* Make sure all other async modesetes have landed. */
 781         ret = down_interruptible(&vc4->async_modeset);
 782         if (ret) {
 783                 drm_framebuffer_unreference(fb);
 784                 kfree(flip_state);
 785                 return ret;
 786         }
 787
 788         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 789
 790         /* Immediately update the plane's legacy fb pointer, so that later
 791          * modeset prep sees the state that will be present when the semaphore
 792          * is released.
 793          */
 794         drm_atomic_set_fb_for_plane(plane->state, fb);
 795         plane->fb = fb;
 796
 797         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 798                            vc4_async_page_flip_complete);
 799
 800         /* Driver takes ownership of state on successful async commit. */
 801         return 0;
 802 }
 803
 804 static int vc4_page_flip(struct drm_crtc *crtc,
 805                          struct drm_framebuffer *fb,
 806                          struct drm_pending_vblank_event *event,
 807                          uint32_t flags)
 808 {
 809         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 810                 return vc4_async_page_flip(crtc, fb, event, flags);
 811         else
 812                 return drm_atomic_helper_page_flip(crtc, fb, event, flags);
 813 }
 814
 815 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 816 {
 817         struct vc4_crtc_state *vc4_state;
 818
 819         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 820         if (!vc4_state)
 821                 return NULL;
 822
 823         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 824         return &vc4_state->base;
 825 }
 826
 827 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 828                                    struct drm_crtc_state *state)
 829 {
 830         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 831         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 832
 833         if (vc4_state->mm.allocated) {
 834                 unsigned long flags;
 835
 836                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 837                 drm_mm_remove_node(&vc4_state->mm);
 838                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 839
 840         }
 841
 842         __drm_atomic_helper_crtc_destroy_state(state);
 843 }
 844
 845 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 846         .set_config = drm_atomic_helper_set_config,
 847         .destroy = vc4_crtc_destroy,
 848         .page_flip = vc4_page_flip,
 849         .set_property = NULL,
 850         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 851         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 852         .reset = drm_atomic_helper_crtc_reset,
 853         .atomic_duplicate_state = vc4_crtc_duplicate_state,
 854         .atomic_destroy_state = vc4_crtc_destroy_state,
 855         .gamma_set = vc4_crtc_gamma_set,
 856 };
 857
 858 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 859         .mode_set_nofb = vc4_crtc_mode_set_nofb,
 860         .disable = vc4_crtc_disable,
 861         .enable = vc4_crtc_enable,
 862         .mode_fixup = vc4_crtc_mode_fixup,
 863         .atomic_check = vc4_crtc_atomic_check,
 864         .atomic_flush = vc4_crtc_atomic_flush,
 865 };
 866
 867 static const struct vc4_crtc_data pv0_data = {
 868         .hvs_channel = 0,
 869         .encoder_types = {
 870                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
 871                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
 872         },
 873 };
 874
 875 static const struct vc4_crtc_data pv1_data = {
 876         .hvs_channel = 2,
 877         .encoder_types = {
 878                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
 879                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
 880         },
 881 };
 882
 883 static const struct vc4_crtc_data pv2_data = {
 884         .hvs_channel = 1,
 885         .encoder_types = {
 886                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
 887                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
 888         },
 889 };
 890
 891 static const struct of_device_id vc4_crtc_dt_match[] = {
 892         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
 893         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
 894         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
 895         {}
 896 };
 897
 898 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
 899                                         struct drm_crtc *crtc)
 900 {
 901         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 902         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
 903         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
 904         struct drm_encoder *encoder;
 905
 906         drm_for_each_encoder(encoder, drm) {
 907                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 908                 int i;
 909
 910                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
 911                         if (vc4_encoder->type == encoder_types[i]) {
 912                                 vc4_encoder->clock_select = i;
 913                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
 914                                 break;
 915                         }
 916                 }
 917         }
 918 }
 919
 920 static void
 921 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
 922 {
 923         struct drm_device *drm = vc4_crtc->base.dev;
 924         struct vc4_dev *vc4 = to_vc4_dev(drm);
 925         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
 926         /* Top/base are supposed to be 4-pixel aligned, but the
 927          * Raspberry Pi firmware fills the low bits (which are
 928          * presumably ignored).
 929          */
 930         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
 931         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
 932
 933         vc4_crtc->cob_size = top - base + 4;
 934 }
 935
 936 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
 937 {
 938         struct platform_device *pdev = to_platform_device(dev);
 939         struct drm_device *drm = dev_get_drvdata(master);
 940         struct vc4_dev *vc4 = to_vc4_dev(drm);
 941         struct vc4_crtc *vc4_crtc;
 942         struct drm_crtc *crtc;
 943         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
 944         const struct of_device_id *match;
 945         int ret, i;
 946
 947         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
 948         if (!vc4_crtc)
 949                 return -ENOMEM;
 950         crtc = &vc4_crtc->base;
 951
 952         match = of_match_device(vc4_crtc_dt_match, dev);
 953         if (!match)
 954                 return -ENODEV;
 955         vc4_crtc->data = match->data;
 956
 957         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
 958         if (IS_ERR(vc4_crtc->regs))
 959                 return PTR_ERR(vc4_crtc->regs);
 960
 961         /* For now, we create just the primary and the legacy cursor
 962          * planes.  We should be able to stack more planes on easily,
 963          * but to do that we would need to compute the bandwidth
 964          * requirement of the plane configuration, and reject ones
 965          * that will take too much.
 966          */
 967         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
 968         if (IS_ERR(primary_plane)) {
 969                 dev_err(dev, "failed to construct primary plane\n");
 970                 ret = PTR_ERR(primary_plane);
 971                 goto err;
 972         }
 973
 974         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
 975                                   &vc4_crtc_funcs, NULL);
 976         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
 977         primary_plane->crtc = crtc;
 978         vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
 979         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
 980         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
 981
 982         /* Set up some arbitrary number of planes.  We're not limited
 983          * by a set number of physical registers, just the space in
 984          * the HVS (16k) and how small an plane can be (28 bytes).
 985          * However, each plane we set up takes up some memory, and
 986          * increases the cost of looping over planes, which atomic
 987          * modesetting does quite a bit.  As a result, we pick a
 988          * modest number of planes to expose, that should hopefully
 989          * still cover any sane usecase.
 990          */
 991         for (i = 0; i < 8; i++) {
 992                 struct drm_plane *plane =
 993                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
 994
 995                 if (IS_ERR(plane))
 996                         continue;
 997
 998                 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
 999         }
1000
1001         /* Set up the legacy cursor after overlay initialization,
1002          * since we overlay planes on the CRTC in the order they were
1003          * initialized.
1004          */
1005         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1006         if (!IS_ERR(cursor_plane)) {
1007                 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1008                 cursor_plane->crtc = crtc;
1009                 crtc->cursor = cursor_plane;
1010         }
1011
1012         vc4_crtc_get_cob_allocation(vc4_crtc);
1013
1014         CRTC_WRITE(PV_INTEN, 0);
1015         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1016         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1017                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1018         if (ret)
1019                 goto err_destroy_planes;
1020
1021         vc4_set_crtc_possible_masks(drm, crtc);
1022
1023         for (i = 0; i < crtc->gamma_size; i++) {
1024                 vc4_crtc->lut_r[i] = i;
1025                 vc4_crtc->lut_g[i] = i;
1026                 vc4_crtc->lut_b[i] = i;
1027         }
1028
1029         platform_set_drvdata(pdev, vc4_crtc);
1030
1031         return 0;
1032
1033 err_destroy_planes:
1034         list_for_each_entry_safe(destroy_plane, temp,
1035                                  &drm->mode_config.plane_list, head) {
1036                 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1037                     destroy_plane->funcs->destroy(destroy_plane);
1038         }
1039 err:
1040         return ret;
1041 }
1042
1043 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1044                             void *data)
1045 {
1046         struct platform_device *pdev = to_platform_device(dev);
1047         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1048
1049         vc4_crtc_destroy(&vc4_crtc->base);
1050
1051         CRTC_WRITE(PV_INTEN, 0);
1052
1053         platform_set_drvdata(pdev, NULL);
1054 }
1055
1056 static const struct component_ops vc4_crtc_ops = {
1057         .bind   = vc4_crtc_bind,
1058         .unbind = vc4_crtc_unbind,
1059 };
1060
1061 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1062 {
1063         return component_add(&pdev->dev, &vc4_crtc_ops);
1064 }
1065
1066 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1067 {
1068         component_del(&pdev->dev, &vc4_crtc_ops);
1069         return 0;
1070 }
1071
1072 struct platform_driver vc4_crtc_driver = {
1073         .probe = vc4_crtc_dev_probe,
1074         .remove = vc4_crtc_dev_remove,
1075         .driver = {
1076                 .name = "vc4_crtc",
1077                 .of_match_table = vc4_crtc_dt_match,
1078         },
1079 };