drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27 #include <linux/module.h>
  28
  29 #include <drm/drmP.h>
  30 #include "vmwgfx_drv.h"
  31 #include <drm/ttm/ttm_placement.h>
  32 #include <drm/ttm/ttm_bo_driver.h>
  33 #include <drm/ttm/ttm_object.h>
  34 #include <drm/ttm/ttm_module.h>
  35 #include <linux/dma_remapping.h>
  36
  37 #define VMWGFX_DRIVER_NAME "vmwgfx"
  38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  39 #define VMWGFX_CHIP_SVGAII 0
  40 #define VMW_FB_RESERVATION 0
  41
  42 #define VMW_MIN_INITIAL_WIDTH 800
  43 #define VMW_MIN_INITIAL_HEIGHT 600
  44
  45
  46 /**
  47  * Fully encoded drm commands. Might move to vmw_drm.h
  48  */
  49
  50 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  51         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  52                  struct drm_vmw_getparam_arg)
  53 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  54         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  55                 union drm_vmw_alloc_dmabuf_arg)
  56 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  57         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  58                 struct drm_vmw_unref_dmabuf_arg)
  59 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  60         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  61                  struct drm_vmw_cursor_bypass_arg)
  62
  63 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  64         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  65                  struct drm_vmw_control_stream_arg)
  66 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  67         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  68                  struct drm_vmw_stream_arg)
  69 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  70         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  71                  struct drm_vmw_stream_arg)
  72
  73 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  74         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  75                 struct drm_vmw_context_arg)
  76 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  77         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  78                 struct drm_vmw_context_arg)
  79 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  80         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  81                  union drm_vmw_surface_create_arg)
  82 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  83         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  84                  struct drm_vmw_surface_arg)
  85 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  86         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  87                  union drm_vmw_surface_reference_arg)
  88 #define DRM_IOCTL_VMW_EXECBUF                                   \
  89         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  90                 struct drm_vmw_execbuf_arg)
  91 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
  92         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
  93                  struct drm_vmw_get_3d_cap_arg)
  94 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
  95         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
  96                  struct drm_vmw_fence_wait_arg)
  97 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
  98         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
  99                  struct drm_vmw_fence_signaled_arg)
 100 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
 101         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
 102                  struct drm_vmw_fence_arg)
 103 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
 104         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
 105                  struct drm_vmw_fence_event_arg)
 106 #define DRM_IOCTL_VMW_PRESENT                                   \
 107         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
 108                  struct drm_vmw_present_arg)
 109 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
 110         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
 111                  struct drm_vmw_present_readback_arg)
 112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
 113         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
 114                  struct drm_vmw_update_layout_arg)
 115 #define DRM_IOCTL_VMW_CREATE_SHADER                             \
 116         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,      \
 117                  struct drm_vmw_shader_create_arg)
 118 #define DRM_IOCTL_VMW_UNREF_SHADER                              \
 119         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,        \
 120                  struct drm_vmw_shader_arg)
 121 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE                         \
 122         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,  \
 123                  union drm_vmw_gb_surface_create_arg)
 124 #define DRM_IOCTL_VMW_GB_SURFACE_REF                            \
 125         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,     \
 126                  union drm_vmw_gb_surface_reference_arg)
 127 #define DRM_IOCTL_VMW_SYNCCPU                                   \
 128         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,             \
 129                  struct drm_vmw_synccpu_arg)
 130
 131 /**
 132  * The core DRM version of this macro doesn't account for
 133  * DRM_COMMAND_BASE.
 134  */
 135
 136 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 137   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
 138
 139 /**
 140  * Ioctl definitions.
 141  */
 142
 143 static const struct drm_ioctl_desc vmw_ioctls[] = {
 144         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 145                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 146         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
 147                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 148         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
 149                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
 150         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 151                       vmw_kms_cursor_bypass_ioctl,
 152                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 153
 154         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 155                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 156         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 157                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 158         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 159                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 160
 161         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 162                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 163         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 164                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
 165         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 166                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 167         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 168                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
 169         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 170                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 171         VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
 172                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 173         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 174                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
 175         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 176                       vmw_fence_obj_signaled_ioctl,
 177                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
 178         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 179                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
 180         VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
 181                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 182         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 183                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 184
 185         /* these allow direct access to the framebuffers mark as master only */
 186         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
 187                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 188         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
 189                       vmw_present_readback_ioctl,
 190                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 191         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
 192                       vmw_kms_update_layout_ioctl,
 193                       DRM_MASTER | DRM_UNLOCKED),
 194         VMW_IOCTL_DEF(VMW_CREATE_SHADER,
 195                       vmw_shader_define_ioctl,
 196                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 197         VMW_IOCTL_DEF(VMW_UNREF_SHADER,
 198                       vmw_shader_destroy_ioctl,
 199                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
 200         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
 201                       vmw_gb_surface_define_ioctl,
 202                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 203         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
 204                       vmw_gb_surface_reference_ioctl,
 205                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 206         VMW_IOCTL_DEF(VMW_SYNCCPU,
 207                       vmw_user_dmabuf_synccpu_ioctl,
 208                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
 209 };
 210
 211 static struct pci_device_id vmw_pci_id_list[] = {
 212         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 213         {0, 0, 0}
 214 };
 215 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
 216
 217 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
 218 static int vmw_force_iommu;
 219 static int vmw_restrict_iommu;
 220 static int vmw_force_coherent;
 221 static int vmw_restrict_dma_mask;
 222
 223 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 224 static void vmw_master_init(struct vmw_master *);
 225 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 226                               void *ptr);
 227
 228 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 229 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 230 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
 231 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
 232 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
 233 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
 234 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
 235 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
 236 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
 237 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
 238
 239
 240 static void vmw_print_capabilities(uint32_t capabilities)
 241 {
 242         DRM_INFO("Capabilities:\n");
 243         if (capabilities & SVGA_CAP_RECT_COPY)
 244                 DRM_INFO("  Rect copy.\n");
 245         if (capabilities & SVGA_CAP_CURSOR)
 246                 DRM_INFO("  Cursor.\n");
 247         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 248                 DRM_INFO("  Cursor bypass.\n");
 249         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 250                 DRM_INFO("  Cursor bypass 2.\n");
 251         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 252                 DRM_INFO("  8bit emulation.\n");
 253         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 254                 DRM_INFO("  Alpha cursor.\n");
 255         if (capabilities & SVGA_CAP_3D)
 256                 DRM_INFO("  3D.\n");
 257         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 258                 DRM_INFO("  Extended Fifo.\n");
 259         if (capabilities & SVGA_CAP_MULTIMON)
 260                 DRM_INFO("  Multimon.\n");
 261         if (capabilities & SVGA_CAP_PITCHLOCK)
 262                 DRM_INFO("  Pitchlock.\n");
 263         if (capabilities & SVGA_CAP_IRQMASK)
 264                 DRM_INFO("  Irq mask.\n");
 265         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 266                 DRM_INFO("  Display Topology.\n");
 267         if (capabilities & SVGA_CAP_GMR)
 268                 DRM_INFO("  GMR.\n");
 269         if (capabilities & SVGA_CAP_TRACES)
 270                 DRM_INFO("  Traces.\n");
 271         if (capabilities & SVGA_CAP_GMR2)
 272                 DRM_INFO("  GMR2.\n");
 273         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 274                 DRM_INFO("  Screen Object 2.\n");
 275         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
 276                 DRM_INFO("  Command Buffers.\n");
 277         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
 278                 DRM_INFO("  Command Buffers 2.\n");
 279         if (capabilities & SVGA_CAP_GBOBJECTS)
 280                 DRM_INFO("  Guest Backed Resources.\n");
 281         if (capabilities & SVGA_CAP_DX)
 282                 DRM_INFO("  DX Features.\n");
 283 }
 284
 285 /**
 286  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 287  *
 288  * @dev_priv: A device private structure.
 289  *
 290  * This function creates a small buffer object that holds the query
 291  * result for dummy queries emitted as query barriers.
 292  * The function will then map the first page and initialize a pending
 293  * occlusion query result structure, Finally it will unmap the buffer.
 294  * No interruptible waits are done within this function.
 295  *
 296  * Returns an error if bo creation or initialization fails.
 297  */
 298 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
 299 {
 300         int ret;
 301         struct vmw_dma_buffer *vbo;
 302         struct ttm_bo_kmap_obj map;
 303         volatile SVGA3dQueryResult *result;
 304         bool dummy;
 305
 306         /*
 307          * Create the vbo as pinned, so that a tryreserve will
 308          * immediately succeed. This is because we're the only
 309          * user of the bo currently.
 310          */
 311         vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
 312         if (!vbo)
 313                 return -ENOMEM;
 314
 315         ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE,
 316                               &vmw_sys_ne_placement, false,
 317                               &vmw_dmabuf_bo_free);
 318         if (unlikely(ret != 0))
 319                 return ret;
 320
 321         ret = ttm_bo_reserve(&vbo->base, false, true, false, NULL);
 322         BUG_ON(ret != 0);
 323         vmw_bo_pin_reserved(vbo, true);
 324
 325         ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
 326         if (likely(ret == 0)) {
 327                 result = ttm_kmap_obj_virtual(&map, &dummy);
 328                 result->totalSize = sizeof(*result);
 329                 result->state = SVGA3D_QUERYSTATE_PENDING;
 330                 result->result32 = 0xff;
 331                 ttm_bo_kunmap(&map);
 332         }
 333         vmw_bo_pin_reserved(vbo, false);
 334         ttm_bo_unreserve(&vbo->base);
 335
 336         if (unlikely(ret != 0)) {
 337                 DRM_ERROR("Dummy query buffer map failed.\n");
 338                 vmw_dmabuf_unreference(&vbo);
 339         } else
 340                 dev_priv->dummy_query_bo = vbo;
 341
 342         return ret;
 343 }
 344
 345 /**
 346  * vmw_request_device_late - Perform late device setup
 347  *
 348  * @dev_priv: Pointer to device private.
 349  *
 350  * This function performs setup of otables and enables large command
 351  * buffer submission. These tasks are split out to a separate function
 352  * because it reverts vmw_release_device_early and is intended to be used
 353  * by an error path in the hibernation code.
 354  */
 355 static int vmw_request_device_late(struct vmw_private *dev_priv)
 356 {
 357         int ret;
 358
 359         if (dev_priv->has_mob) {
 360                 ret = vmw_otables_setup(dev_priv);
 361                 if (unlikely(ret != 0)) {
 362                         DRM_ERROR("Unable to initialize "
 363                                   "guest Memory OBjects.\n");
 364                         return ret;
 365                 }
 366         }
 367
 368         if (dev_priv->cman) {
 369                 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
 370                                                256*4096, 2*4096);
 371                 if (ret) {
 372                         struct vmw_cmdbuf_man *man = dev_priv->cman;
 373
 374                         dev_priv->cman = NULL;
 375                         vmw_cmdbuf_man_destroy(man);
 376                 }
 377         }
 378
 379         return 0;
 380 }
 381
 382 static int vmw_request_device(struct vmw_private *dev_priv)
 383 {
 384         int ret;
 385
 386         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 387         if (unlikely(ret != 0)) {
 388                 DRM_ERROR("Unable to initialize FIFO.\n");
 389                 return ret;
 390         }
 391         vmw_fence_fifo_up(dev_priv->fman);
 392         dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
 393         if (IS_ERR(dev_priv->cman))
 394                 dev_priv->cman = NULL;
 395
 396         ret = vmw_request_device_late(dev_priv);
 397         if (ret)
 398                 goto out_no_mob;
 399
 400         ret = vmw_dummy_query_bo_create(dev_priv);
 401         if (unlikely(ret != 0))
 402                 goto out_no_query_bo;
 403
 404         return 0;
 405
 406 out_no_query_bo:
 407         if (dev_priv->cman)
 408                 vmw_cmdbuf_remove_pool(dev_priv->cman);
 409         if (dev_priv->has_mob) {
 410                 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
 411                 vmw_otables_takedown(dev_priv);
 412         }
 413         if (dev_priv->cman)
 414                 vmw_cmdbuf_man_destroy(dev_priv->cman);
 415 out_no_mob:
 416         vmw_fence_fifo_down(dev_priv->fman);
 417         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 418         return ret;
 419 }
 420
 421 /**
 422  * vmw_release_device_early - Early part of fifo takedown.
 423  *
 424  * @dev_priv: Pointer to device private struct.
 425  *
 426  * This is the first part of command submission takedown, to be called before
 427  * buffer management is taken down.
 428  */
 429 static void vmw_release_device_early(struct vmw_private *dev_priv)
 430 {
 431         /*
 432          * Previous destructions should've released
 433          * the pinned bo.
 434          */
 435
 436         BUG_ON(dev_priv->pinned_bo != NULL);
 437
 438         vmw_dmabuf_unreference(&dev_priv->dummy_query_bo);
 439         if (dev_priv->cman)
 440                 vmw_cmdbuf_remove_pool(dev_priv->cman);
 441
 442         if (dev_priv->has_mob) {
 443                 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
 444                 vmw_otables_takedown(dev_priv);
 445         }
 446 }
 447
 448 /**
 449  * vmw_release_device_late - Late part of fifo takedown.
 450  *
 451  * @dev_priv: Pointer to device private struct.
 452  *
 453  * This is the last part of the command submission takedown, to be called when
 454  * command submission is no longer needed. It may wait on pending fences.
 455  */
 456 static void vmw_release_device_late(struct vmw_private *dev_priv)
 457 {
 458         vmw_fence_fifo_down(dev_priv->fman);
 459         if (dev_priv->cman)
 460                 vmw_cmdbuf_man_destroy(dev_priv->cman);
 461
 462         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 463 }
 464
 465 /**
 466  * Sets the initial_[width|height] fields on the given vmw_private.
 467  *
 468  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
 469  * clamping the value to fb_max_[width|height] fields and the
 470  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 471  * If the values appear to be invalid, set them to
 472  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 473  */
 474 static void vmw_get_initial_size(struct vmw_private *dev_priv)
 475 {
 476         uint32_t width;
 477         uint32_t height;
 478
 479         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
 480         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
 481
 482         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
 483         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
 484
 485         if (width > dev_priv->fb_max_width ||
 486             height > dev_priv->fb_max_height) {
 487
 488                 /*
 489                  * This is a host error and shouldn't occur.
 490                  */
 491
 492                 width = VMW_MIN_INITIAL_WIDTH;
 493                 height = VMW_MIN_INITIAL_HEIGHT;
 494         }
 495
 496         dev_priv->initial_width = width;
 497         dev_priv->initial_height = height;
 498 }
 499
 500 /**
 501  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
 502  * system.
 503  *
 504  * @dev_priv: Pointer to a struct vmw_private
 505  *
 506  * This functions tries to determine the IOMMU setup and what actions
 507  * need to be taken by the driver to make system pages visible to the
 508  * device.
 509  * If this function decides that DMA is not possible, it returns -EINVAL.
 510  * The driver may then try to disable features of the device that require
 511  * DMA.
 512  */
 513 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
 514 {
 515         static const char *names[vmw_dma_map_max] = {
 516                 [vmw_dma_phys] = "Using physical TTM page addresses.",
 517                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
 518                 [vmw_dma_map_populate] = "Keeping DMA mappings.",
 519                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
 520 #ifdef CONFIG_X86
 521         const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
 522
 523 #ifdef CONFIG_INTEL_IOMMU
 524         if (intel_iommu_enabled) {
 525                 dev_priv->map_mode = vmw_dma_map_populate;
 526                 goto out_fixup;
 527         }
 528 #endif
 529
 530         if (!(vmw_force_iommu || vmw_force_coherent)) {
 531                 dev_priv->map_mode = vmw_dma_phys;
 532                 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 533                 return 0;
 534         }
 535
 536         dev_priv->map_mode = vmw_dma_map_populate;
 537
 538         if (dma_ops->sync_single_for_cpu)
 539                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 540 #ifdef CONFIG_SWIOTLB
 541         if (swiotlb_nr_tbl() == 0)
 542                 dev_priv->map_mode = vmw_dma_map_populate;
 543 #endif
 544
 545 #ifdef CONFIG_INTEL_IOMMU
 546 out_fixup:
 547 #endif
 548         if (dev_priv->map_mode == vmw_dma_map_populate &&
 549             vmw_restrict_iommu)
 550                 dev_priv->map_mode = vmw_dma_map_bind;
 551
 552         if (vmw_force_coherent)
 553                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 554
 555 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
 556         /*
 557          * No coherent page pool
 558          */
 559         if (dev_priv->map_mode == vmw_dma_alloc_coherent)
 560                 return -EINVAL;
 561 #endif
 562
 563 #else /* CONFIG_X86 */
 564         dev_priv->map_mode = vmw_dma_map_populate;
 565 #endif /* CONFIG_X86 */
 566
 567         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 568
 569         return 0;
 570 }
 571
 572 /**
 573  * vmw_dma_masks - set required page- and dma masks
 574  *
 575  * @dev: Pointer to struct drm-device
 576  *
 577  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
 578  * restriction also for 64-bit systems.
 579  */
 580 #ifdef CONFIG_INTEL_IOMMU
 581 static int vmw_dma_masks(struct vmw_private *dev_priv)
 582 {
 583         struct drm_device *dev = dev_priv->dev;
 584
 585         if (intel_iommu_enabled &&
 586             (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
 587                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
 588                 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
 589         }
 590         return 0;
 591 }
 592 #else
 593 static int vmw_dma_masks(struct vmw_private *dev_priv)
 594 {
 595         return 0;
 596 }
 597 #endif
 598
 599 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 600 {
 601         struct vmw_private *dev_priv;
 602         int ret;
 603         uint32_t svga_id;
 604         enum vmw_res_type i;
 605         bool refuse_dma = false;
 606
 607         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 608         if (unlikely(dev_priv == NULL)) {
 609                 DRM_ERROR("Failed allocating a device private struct.\n");
 610                 return -ENOMEM;
 611         }
 612
 613         pci_set_master(dev->pdev);
 614
 615         dev_priv->dev = dev;
 616         dev_priv->vmw_chipset = chipset;
 617         dev_priv->last_read_seqno = (uint32_t) -100;
 618         mutex_init(&dev_priv->cmdbuf_mutex);
 619         mutex_init(&dev_priv->release_mutex);
 620         mutex_init(&dev_priv->binding_mutex);
 621         rwlock_init(&dev_priv->resource_lock);
 622         ttm_lock_init(&dev_priv->reservation_sem);
 623         spin_lock_init(&dev_priv->hw_lock);
 624         spin_lock_init(&dev_priv->waiter_lock);
 625         spin_lock_init(&dev_priv->cap_lock);
 626         spin_lock_init(&dev_priv->svga_lock);
 627
 628         for (i = vmw_res_context; i < vmw_res_max; ++i) {
 629                 idr_init(&dev_priv->res_idr[i]);
 630                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
 631         }
 632
 633         mutex_init(&dev_priv->init_mutex);
 634         init_waitqueue_head(&dev_priv->fence_queue);
 635         init_waitqueue_head(&dev_priv->fifo_queue);
 636         dev_priv->fence_queue_waiters = 0;
 637         atomic_set(&dev_priv->fifo_queue_waiters, 0);
 638
 639         dev_priv->used_memory_size = 0;
 640
 641         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 642         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 643         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 644
 645         dev_priv->enable_fb = enable_fbdev;
 646
 647         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 648         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 649         if (svga_id != SVGA_ID_2) {
 650                 ret = -ENOSYS;
 651                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
 652                 goto out_err0;
 653         }
 654
 655         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 656         ret = vmw_dma_select_mode(dev_priv);
 657         if (unlikely(ret != 0)) {
 658                 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
 659                 refuse_dma = true;
 660         }
 661
 662         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 663         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 664         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 665         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 666
 667         vmw_get_initial_size(dev_priv);
 668
 669         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 670                 dev_priv->max_gmr_ids =
 671                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 672                 dev_priv->max_gmr_pages =
 673                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 674                 dev_priv->memory_size =
 675                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 676                 dev_priv->memory_size -= dev_priv->vram_size;
 677         } else {
 678                 /*
 679                  * An arbitrary limit of 512MiB on surface
 680                  * memory. But all HWV8 hardware supports GMR2.
 681                  */
 682                 dev_priv->memory_size = 512*1024*1024;
 683         }
 684         dev_priv->max_mob_pages = 0;
 685         dev_priv->max_mob_size = 0;
 686         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 687                 uint64_t mem_size =
 688                         vmw_read(dev_priv,
 689                                  SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
 690
 691                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
 692                 dev_priv->prim_bb_mem =
 693                         vmw_read(dev_priv,
 694                                  SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
 695                 dev_priv->max_mob_size =
 696                         vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
 697                 dev_priv->stdu_max_width =
 698                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
 699                 dev_priv->stdu_max_height =
 700                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
 701
 702                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 703                           SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
 704                 dev_priv->texture_max_width = vmw_read(dev_priv,
 705                                                        SVGA_REG_DEV_CAP);
 706                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 707                           SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
 708                 dev_priv->texture_max_height = vmw_read(dev_priv,
 709                                                         SVGA_REG_DEV_CAP);
 710         } else {
 711                 dev_priv->texture_max_width = 8192;
 712                 dev_priv->texture_max_height = 8192;
 713                 dev_priv->prim_bb_mem = dev_priv->vram_size;
 714         }
 715
 716         vmw_print_capabilities(dev_priv->capabilities);
 717
 718         ret = vmw_dma_masks(dev_priv);
 719         if (unlikely(ret != 0))
 720                 goto out_err0;
 721
 722         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 723                 DRM_INFO("Max GMR ids is %u\n",
 724                          (unsigned)dev_priv->max_gmr_ids);
 725                 DRM_INFO("Max number of GMR pages is %u\n",
 726                          (unsigned)dev_priv->max_gmr_pages);
 727                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 728                          (unsigned)dev_priv->memory_size / 1024);
 729         }
 730         DRM_INFO("Maximum display memory size is %u kiB\n",
 731                  dev_priv->prim_bb_mem / 1024);
 732         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 733                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 734         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 735                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 736
 737         ret = vmw_ttm_global_init(dev_priv);
 738         if (unlikely(ret != 0))
 739                 goto out_err0;
 740
 741
 742         vmw_master_init(&dev_priv->fbdev_master);
 743         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 744         dev_priv->active_master = &dev_priv->fbdev_master;
 745
 746
 747         dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
 748                                                dev_priv->mmio_size);
 749
 750         dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
 751                                          dev_priv->mmio_size);
 752
 753         if (unlikely(dev_priv->mmio_virt == NULL)) {
 754                 ret = -ENOMEM;
 755                 DRM_ERROR("Failed mapping MMIO.\n");
 756                 goto out_err3;
 757         }
 758
 759         /* Need mmio memory to check for fifo pitchlock cap. */
 760         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 761             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 762             !vmw_fifo_have_pitchlock(dev_priv)) {
 763                 ret = -ENOSYS;
 764                 DRM_ERROR("Hardware has no pitchlock\n");
 765                 goto out_err4;
 766         }
 767
 768         dev_priv->tdev = ttm_object_device_init
 769                 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
 770
 771         if (unlikely(dev_priv->tdev == NULL)) {
 772                 DRM_ERROR("Unable to initialize TTM object management.\n");
 773                 ret = -ENOMEM;
 774                 goto out_err4;
 775         }
 776
 777         dev->dev_private = dev_priv;
 778
 779         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 780         dev_priv->stealth = (ret != 0);
 781         if (dev_priv->stealth) {
 782                 /**
 783                  * Request at least the mmio PCI resource.
 784                  */
 785
 786                 DRM_INFO("It appears like vesafb is loaded. "
 787                          "Ignore above error if any.\n");
 788                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 789                 if (unlikely(ret != 0)) {
 790                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 791                         goto out_no_device;
 792                 }
 793         }
 794
 795         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 796                 ret = drm_irq_install(dev, dev->pdev->irq);
 797                 if (ret != 0) {
 798                         DRM_ERROR("Failed installing irq: %d\n", ret);
 799                         goto out_no_irq;
 800                 }
 801         }
 802
 803         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 804         if (unlikely(dev_priv->fman == NULL)) {
 805                 ret = -ENOMEM;
 806                 goto out_no_fman;
 807         }
 808
 809         ret = ttm_bo_device_init(&dev_priv->bdev,
 810                                  dev_priv->bo_global_ref.ref.object,
 811                                  &vmw_bo_driver,
 812                                  dev->anon_inode->i_mapping,
 813                                  VMWGFX_FILE_PAGE_OFFSET,
 814                                  false);
 815         if (unlikely(ret != 0)) {
 816                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 817                 goto out_no_bdev;
 818         }
 819
 820         /*
 821          * Enable VRAM, but initially don't use it until SVGA is enabled and
 822          * unhidden.
 823          */
 824         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 825                              (dev_priv->vram_size >> PAGE_SHIFT));
 826         if (unlikely(ret != 0)) {
 827                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 828                 goto out_no_vram;
 829         }
 830         dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
 831
 832         dev_priv->has_gmr = true;
 833         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
 834             refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 835                                          VMW_PL_GMR) != 0) {
 836                 DRM_INFO("No GMR memory available. "
 837                          "Graphics memory resources are very limited.\n");
 838                 dev_priv->has_gmr = false;
 839         }
 840
 841         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 842                 dev_priv->has_mob = true;
 843                 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
 844                                    VMW_PL_MOB) != 0) {
 845                         DRM_INFO("No MOB memory available. "
 846                                  "3D will be disabled.\n");
 847                         dev_priv->has_mob = false;
 848                 }
 849         }
 850
 851         ret = vmw_kms_init(dev_priv);
 852         if (unlikely(ret != 0))
 853                 goto out_no_kms;
 854         vmw_overlay_init(dev_priv);
 855
 856         ret = vmw_request_device(dev_priv);
 857         if (ret)
 858                 goto out_no_fifo;
 859
 860         if (dev_priv->enable_fb) {
 861                 vmw_fifo_resource_inc(dev_priv);
 862                 vmw_svga_enable(dev_priv);
 863                 vmw_fb_init(dev_priv);
 864         }
 865
 866         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 867         register_pm_notifier(&dev_priv->pm_nb);
 868
 869         return 0;
 870
 871 out_no_fifo:
 872         vmw_overlay_close(dev_priv);
 873         vmw_kms_close(dev_priv);
 874 out_no_kms:
 875         if (dev_priv->has_mob)
 876                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 877         if (dev_priv->has_gmr)
 878                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 879         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 880 out_no_vram:
 881         (void)ttm_bo_device_release(&dev_priv->bdev);
 882 out_no_bdev:
 883         vmw_fence_manager_takedown(dev_priv->fman);
 884 out_no_fman:
 885         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 886                 drm_irq_uninstall(dev_priv->dev);
 887 out_no_irq:
 888         if (dev_priv->stealth)
 889                 pci_release_region(dev->pdev, 2);
 890         else
 891                 pci_release_regions(dev->pdev);
 892 out_no_device:
 893         ttm_object_device_release(&dev_priv->tdev);
 894 out_err4:
 895         iounmap(dev_priv->mmio_virt);
 896 out_err3:
 897         arch_phys_wc_del(dev_priv->mmio_mtrr);
 898         vmw_ttm_global_release(dev_priv);
 899 out_err0:
 900         for (i = vmw_res_context; i < vmw_res_max; ++i)
 901                 idr_destroy(&dev_priv->res_idr[i]);
 902
 903         kfree(dev_priv);
 904         return ret;
 905 }
 906
 907 static int vmw_driver_unload(struct drm_device *dev)
 908 {
 909         struct vmw_private *dev_priv = vmw_priv(dev);
 910         enum vmw_res_type i;
 911
 912         unregister_pm_notifier(&dev_priv->pm_nb);
 913
 914         if (dev_priv->ctx.res_ht_initialized)
 915                 drm_ht_remove(&dev_priv->ctx.res_ht);
 916         vfree(dev_priv->ctx.cmd_bounce);
 917         if (dev_priv->enable_fb) {
 918                 vmw_fb_off(dev_priv);
 919                 vmw_fb_close(dev_priv);
 920                 vmw_fifo_resource_dec(dev_priv);
 921                 vmw_svga_disable(dev_priv);
 922         }
 923
 924         vmw_kms_close(dev_priv);
 925         vmw_overlay_close(dev_priv);
 926
 927         if (dev_priv->has_gmr)
 928                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 929         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 930
 931         vmw_release_device_early(dev_priv);
 932         if (dev_priv->has_mob)
 933                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 934         (void) ttm_bo_device_release(&dev_priv->bdev);
 935         vmw_release_device_late(dev_priv);
 936         vmw_fence_manager_takedown(dev_priv->fman);
 937         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 938                 drm_irq_uninstall(dev_priv->dev);
 939         if (dev_priv->stealth)
 940                 pci_release_region(dev->pdev, 2);
 941         else
 942                 pci_release_regions(dev->pdev);
 943
 944         ttm_object_device_release(&dev_priv->tdev);
 945         iounmap(dev_priv->mmio_virt);
 946         arch_phys_wc_del(dev_priv->mmio_mtrr);
 947         (void)ttm_bo_device_release(&dev_priv->bdev);
 948         vmw_ttm_global_release(dev_priv);
 949
 950         for (i = vmw_res_context; i < vmw_res_max; ++i)
 951                 idr_destroy(&dev_priv->res_idr[i]);
 952
 953         kfree(dev_priv);
 954
 955         return 0;
 956 }
 957
 958 static void vmw_preclose(struct drm_device *dev,
 959                          struct drm_file *file_priv)
 960 {
 961         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 962         struct vmw_private *dev_priv = vmw_priv(dev);
 963
 964         vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
 965 }
 966
 967 static void vmw_postclose(struct drm_device *dev,
 968                          struct drm_file *file_priv)
 969 {
 970         struct vmw_fpriv *vmw_fp;
 971
 972         vmw_fp = vmw_fpriv(file_priv);
 973
 974         if (vmw_fp->locked_master) {
 975                 struct vmw_master *vmaster =
 976                         vmw_master(vmw_fp->locked_master);
 977
 978                 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 979                 ttm_vt_unlock(&vmaster->lock);
 980                 drm_master_put(&vmw_fp->locked_master);
 981         }
 982
 983         ttm_object_file_release(&vmw_fp->tfile);
 984         kfree(vmw_fp);
 985 }
 986
 987 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 988 {
 989         struct vmw_private *dev_priv = vmw_priv(dev);
 990         struct vmw_fpriv *vmw_fp;
 991         int ret = -ENOMEM;
 992
 993         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
 994         if (unlikely(vmw_fp == NULL))
 995                 return ret;
 996
 997         INIT_LIST_HEAD(&vmw_fp->fence_events);
 998         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
 999         if (unlikely(vmw_fp->tfile == NULL))
1000                 goto out_no_tfile;
1001
1002         file_priv->driver_priv = vmw_fp;
1003
1004         return 0;
1005
1006 out_no_tfile:
1007         kfree(vmw_fp);
1008         return ret;
1009 }
1010
1011 static struct vmw_master *vmw_master_check(struct drm_device *dev,
1012                                            struct drm_file *file_priv,
1013                                            unsigned int flags)
1014 {
1015         int ret;
1016         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1017         struct vmw_master *vmaster;
1018
1019         if (file_priv->minor->type != DRM_MINOR_LEGACY ||
1020             !(flags & DRM_AUTH))
1021                 return NULL;
1022
1023         ret = mutex_lock_interruptible(&dev->master_mutex);
1024         if (unlikely(ret != 0))
1025                 return ERR_PTR(-ERESTARTSYS);
1026
1027         if (file_priv->is_master) {
1028                 mutex_unlock(&dev->master_mutex);
1029                 return NULL;
1030         }
1031
1032         /*
1033          * Check if we were previously master, but now dropped.
1034          */
1035         if (vmw_fp->locked_master) {
1036                 mutex_unlock(&dev->master_mutex);
1037                 DRM_ERROR("Dropped master trying to access ioctl that "
1038                           "requires authentication.\n");
1039                 return ERR_PTR(-EACCES);
1040         }
1041         mutex_unlock(&dev->master_mutex);
1042
1043         /*
1044          * Taking the drm_global_mutex after the TTM lock might deadlock
1045          */
1046         if (!(flags & DRM_UNLOCKED)) {
1047                 DRM_ERROR("Refusing locked ioctl access.\n");
1048                 return ERR_PTR(-EDEADLK);
1049         }
1050
1051         /*
1052          * Take the TTM lock. Possibly sleep waiting for the authenticating
1053          * master to become master again, or for a SIGTERM if the
1054          * authenticating master exits.
1055          */
1056         vmaster = vmw_master(file_priv->master);
1057         ret = ttm_read_lock(&vmaster->lock, true);
1058         if (unlikely(ret != 0))
1059                 vmaster = ERR_PTR(ret);
1060
1061         return vmaster;
1062 }
1063
1064 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1065                               unsigned long arg,
1066                               long (*ioctl_func)(struct file *, unsigned int,
1067                                                  unsigned long))
1068 {
1069         struct drm_file *file_priv = filp->private_data;
1070         struct drm_device *dev = file_priv->minor->dev;
1071         unsigned int nr = DRM_IOCTL_NR(cmd);
1072         struct vmw_master *vmaster;
1073         unsigned int flags;
1074         long ret;
1075
1076         /*
1077          * Do extra checking on driver private ioctls.
1078          */
1079
1080         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1081             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1082                 const struct drm_ioctl_desc *ioctl =
1083                         &vmw_ioctls[nr - DRM_COMMAND_BASE];
1084
1085                 if (unlikely(ioctl->cmd != cmd)) {
1086                         DRM_ERROR("Invalid command format, ioctl %d\n",
1087                                   nr - DRM_COMMAND_BASE);
1088                         return -EINVAL;
1089                 }
1090                 flags = ioctl->flags;
1091         } else if (!drm_ioctl_flags(nr, &flags))
1092                 return -EINVAL;
1093
1094         vmaster = vmw_master_check(dev, file_priv, flags);
1095         if (unlikely(IS_ERR(vmaster))) {
1096                 ret = PTR_ERR(vmaster);
1097
1098                 if (ret != -ERESTARTSYS)
1099                         DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1100                                  nr, ret);
1101                 return ret;
1102         }
1103
1104         ret = ioctl_func(filp, cmd, arg);
1105         if (vmaster)
1106                 ttm_read_unlock(&vmaster->lock);
1107
1108         return ret;
1109 }
1110
1111 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1112                                unsigned long arg)
1113 {
1114         return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1115 }
1116
1117 #ifdef CONFIG_COMPAT
1118 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1119                              unsigned long arg)
1120 {
1121         return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1122 }
1123 #endif
1124
1125 static void vmw_lastclose(struct drm_device *dev)
1126 {
1127 }
1128
1129 static void vmw_master_init(struct vmw_master *vmaster)
1130 {
1131         ttm_lock_init(&vmaster->lock);
1132 }
1133
1134 static int vmw_master_create(struct drm_device *dev,
1135                              struct drm_master *master)
1136 {
1137         struct vmw_master *vmaster;
1138
1139         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1140         if (unlikely(vmaster == NULL))
1141                 return -ENOMEM;
1142
1143         vmw_master_init(vmaster);
1144         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1145         master->driver_priv = vmaster;
1146
1147         return 0;
1148 }
1149
1150 static void vmw_master_destroy(struct drm_device *dev,
1151                                struct drm_master *master)
1152 {
1153         struct vmw_master *vmaster = vmw_master(master);
1154
1155         master->driver_priv = NULL;
1156         kfree(vmaster);
1157 }
1158
1159
1160 static int vmw_master_set(struct drm_device *dev,
1161                           struct drm_file *file_priv,
1162                           bool from_open)
1163 {
1164         struct vmw_private *dev_priv = vmw_priv(dev);
1165         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1166         struct vmw_master *active = dev_priv->active_master;
1167         struct vmw_master *vmaster = vmw_master(file_priv->master);
1168         int ret = 0;
1169
1170         if (active) {
1171                 BUG_ON(active != &dev_priv->fbdev_master);
1172                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1173                 if (unlikely(ret != 0))
1174                         return ret;
1175
1176                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1177                 dev_priv->active_master = NULL;
1178         }
1179
1180         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1181         if (!from_open) {
1182                 ttm_vt_unlock(&vmaster->lock);
1183                 BUG_ON(vmw_fp->locked_master != file_priv->master);
1184                 drm_master_put(&vmw_fp->locked_master);
1185         }
1186
1187         dev_priv->active_master = vmaster;
1188
1189         return 0;
1190 }
1191
1192 static void vmw_master_drop(struct drm_device *dev,
1193                             struct drm_file *file_priv,
1194                             bool from_release)
1195 {
1196         struct vmw_private *dev_priv = vmw_priv(dev);
1197         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1198         struct vmw_master *vmaster = vmw_master(file_priv->master);
1199         int ret;
1200
1201         /**
1202          * Make sure the master doesn't disappear while we have
1203          * it locked.
1204          */
1205
1206         vmw_fp->locked_master = drm_master_get(file_priv->master);
1207         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1208         if (unlikely((ret != 0))) {
1209                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1210                 drm_master_put(&vmw_fp->locked_master);
1211         }
1212
1213         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1214
1215         if (!dev_priv->enable_fb)
1216                 vmw_svga_disable(dev_priv);
1217
1218         dev_priv->active_master = &dev_priv->fbdev_master;
1219         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1220         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1221
1222         if (dev_priv->enable_fb)
1223                 vmw_fb_on(dev_priv);
1224 }
1225
1226 /**
1227  * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1228  *
1229  * @dev_priv: Pointer to device private struct.
1230  * Needs the reservation sem to be held in non-exclusive mode.
1231  */
1232 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1233 {
1234         spin_lock(&dev_priv->svga_lock);
1235         if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1236                 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1237                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1238         }
1239         spin_unlock(&dev_priv->svga_lock);
1240 }
1241
1242 /**
1243  * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1244  *
1245  * @dev_priv: Pointer to device private struct.
1246  */
1247 void vmw_svga_enable(struct vmw_private *dev_priv)
1248 {
1249         ttm_read_lock(&dev_priv->reservation_sem, false);
1250         __vmw_svga_enable(dev_priv);
1251         ttm_read_unlock(&dev_priv->reservation_sem);
1252 }
1253
1254 /**
1255  * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1256  *
1257  * @dev_priv: Pointer to device private struct.
1258  * Needs the reservation sem to be held in exclusive mode.
1259  * Will not empty VRAM. VRAM must be emptied by caller.
1260  */
1261 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1262 {
1263         spin_lock(&dev_priv->svga_lock);
1264         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1265                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1266                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1267                           SVGA_REG_ENABLE_HIDE |
1268                           SVGA_REG_ENABLE_ENABLE);
1269         }
1270         spin_unlock(&dev_priv->svga_lock);
1271 }
1272
1273 /**
1274  * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1275  * running.
1276  *
1277  * @dev_priv: Pointer to device private struct.
1278  * Will empty VRAM.
1279  */
1280 void vmw_svga_disable(struct vmw_private *dev_priv)
1281 {
1282         ttm_write_lock(&dev_priv->reservation_sem, false);
1283         spin_lock(&dev_priv->svga_lock);
1284         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1285                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1286                 spin_unlock(&dev_priv->svga_lock);
1287                 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1288                         DRM_ERROR("Failed evicting VRAM buffers.\n");
1289                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1290                           SVGA_REG_ENABLE_HIDE |
1291                           SVGA_REG_ENABLE_ENABLE);
1292         } else
1293                 spin_unlock(&dev_priv->svga_lock);
1294         ttm_write_unlock(&dev_priv->reservation_sem);
1295 }
1296
1297 static void vmw_remove(struct pci_dev *pdev)
1298 {
1299         struct drm_device *dev = pci_get_drvdata(pdev);
1300
1301         pci_disable_device(pdev);
1302         drm_put_dev(dev);
1303 }
1304
1305 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1306                               void *ptr)
1307 {
1308         struct vmw_private *dev_priv =
1309                 container_of(nb, struct vmw_private, pm_nb);
1310
1311         switch (val) {
1312         case PM_HIBERNATION_PREPARE:
1313                 if (dev_priv->enable_fb)
1314                         vmw_fb_off(dev_priv);
1315                 ttm_suspend_lock(&dev_priv->reservation_sem);
1316
1317                 /*
1318                  * This empties VRAM and unbinds all GMR bindings.
1319                  * Buffer contents is moved to swappable memory.
1320                  */
1321                 vmw_execbuf_release_pinned_bo(dev_priv);
1322                 vmw_resource_evict_all(dev_priv);
1323                 vmw_release_device_early(dev_priv);
1324                 ttm_bo_swapout_all(&dev_priv->bdev);
1325                 vmw_fence_fifo_down(dev_priv->fman);
1326                 break;
1327         case PM_POST_HIBERNATION:
1328         case PM_POST_RESTORE:
1329                 vmw_fence_fifo_up(dev_priv->fman);
1330                 ttm_suspend_unlock(&dev_priv->reservation_sem);
1331                 if (dev_priv->enable_fb)
1332                         vmw_fb_on(dev_priv);
1333                 break;
1334         case PM_RESTORE_PREPARE:
1335                 break;
1336         default:
1337                 break;
1338         }
1339         return 0;
1340 }
1341
1342 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1343 {
1344         struct drm_device *dev = pci_get_drvdata(pdev);
1345         struct vmw_private *dev_priv = vmw_priv(dev);
1346
1347         if (dev_priv->refuse_hibernation)
1348                 return -EBUSY;
1349
1350         pci_save_state(pdev);
1351         pci_disable_device(pdev);
1352         pci_set_power_state(pdev, PCI_D3hot);
1353         return 0;
1354 }
1355
1356 static int vmw_pci_resume(struct pci_dev *pdev)
1357 {
1358         pci_set_power_state(pdev, PCI_D0);
1359         pci_restore_state(pdev);
1360         return pci_enable_device(pdev);
1361 }
1362
1363 static int vmw_pm_suspend(struct device *kdev)
1364 {
1365         struct pci_dev *pdev = to_pci_dev(kdev);
1366         struct pm_message dummy;
1367
1368         dummy.event = 0;
1369
1370         return vmw_pci_suspend(pdev, dummy);
1371 }
1372
1373 static int vmw_pm_resume(struct device *kdev)
1374 {
1375         struct pci_dev *pdev = to_pci_dev(kdev);
1376
1377         return vmw_pci_resume(pdev);
1378 }
1379
1380 static int vmw_pm_freeze(struct device *kdev)
1381 {
1382         struct pci_dev *pdev = to_pci_dev(kdev);
1383         struct drm_device *dev = pci_get_drvdata(pdev);
1384         struct vmw_private *dev_priv = vmw_priv(dev);
1385
1386         dev_priv->suspended = true;
1387         if (dev_priv->enable_fb)
1388                 vmw_fifo_resource_dec(dev_priv);
1389
1390         if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1391                 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1392                 if (dev_priv->enable_fb)
1393                         vmw_fifo_resource_inc(dev_priv);
1394                 WARN_ON(vmw_request_device_late(dev_priv));
1395                 dev_priv->suspended = false;
1396                 return -EBUSY;
1397         }
1398
1399         if (dev_priv->enable_fb)
1400                 __vmw_svga_disable(dev_priv);
1401
1402         vmw_release_device_late(dev_priv);
1403
1404         return 0;
1405 }
1406
1407 static int vmw_pm_restore(struct device *kdev)
1408 {
1409         struct pci_dev *pdev = to_pci_dev(kdev);
1410         struct drm_device *dev = pci_get_drvdata(pdev);
1411         struct vmw_private *dev_priv = vmw_priv(dev);
1412         int ret;
1413
1414         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1415         (void) vmw_read(dev_priv, SVGA_REG_ID);
1416
1417         if (dev_priv->enable_fb)
1418                 vmw_fifo_resource_inc(dev_priv);
1419
1420         ret = vmw_request_device(dev_priv);
1421         if (ret)
1422                 return ret;
1423
1424         if (dev_priv->enable_fb)
1425                 __vmw_svga_enable(dev_priv);
1426
1427         dev_priv->suspended = false;
1428
1429         return 0;
1430 }
1431
1432 static const struct dev_pm_ops vmw_pm_ops = {
1433         .freeze = vmw_pm_freeze,
1434         .thaw = vmw_pm_restore,
1435         .restore = vmw_pm_restore,
1436         .suspend = vmw_pm_suspend,
1437         .resume = vmw_pm_resume,
1438 };
1439
1440 static const struct file_operations vmwgfx_driver_fops = {
1441         .owner = THIS_MODULE,
1442         .open = drm_open,
1443         .release = drm_release,
1444         .unlocked_ioctl = vmw_unlocked_ioctl,
1445         .mmap = vmw_mmap,
1446         .poll = vmw_fops_poll,
1447         .read = vmw_fops_read,
1448 #if defined(CONFIG_COMPAT)
1449         .compat_ioctl = vmw_compat_ioctl,
1450 #endif
1451         .llseek = noop_llseek,
1452 };
1453
1454 static struct drm_driver driver = {
1455         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1456         DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
1457         .load = vmw_driver_load,
1458         .unload = vmw_driver_unload,
1459         .lastclose = vmw_lastclose,
1460         .irq_preinstall = vmw_irq_preinstall,
1461         .irq_postinstall = vmw_irq_postinstall,
1462         .irq_uninstall = vmw_irq_uninstall,
1463         .irq_handler = vmw_irq_handler,
1464         .get_vblank_counter = vmw_get_vblank_counter,
1465         .enable_vblank = vmw_enable_vblank,
1466         .disable_vblank = vmw_disable_vblank,
1467         .ioctls = vmw_ioctls,
1468         .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1469         .master_create = vmw_master_create,
1470         .master_destroy = vmw_master_destroy,
1471         .master_set = vmw_master_set,
1472         .master_drop = vmw_master_drop,
1473         .open = vmw_driver_open,
1474         .preclose = vmw_preclose,
1475         .postclose = vmw_postclose,
1476         .set_busid = drm_pci_set_busid,
1477
1478         .dumb_create = vmw_dumb_create,
1479         .dumb_map_offset = vmw_dumb_map_offset,
1480         .dumb_destroy = vmw_dumb_destroy,
1481
1482         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1483         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1484
1485         .fops = &vmwgfx_driver_fops,
1486         .name = VMWGFX_DRIVER_NAME,
1487         .desc = VMWGFX_DRIVER_DESC,
1488         .date = VMWGFX_DRIVER_DATE,
1489         .major = VMWGFX_DRIVER_MAJOR,
1490         .minor = VMWGFX_DRIVER_MINOR,
1491         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1492 };
1493
1494 static struct pci_driver vmw_pci_driver = {
1495         .name = VMWGFX_DRIVER_NAME,
1496         .id_table = vmw_pci_id_list,
1497         .probe = vmw_probe,
1498         .remove = vmw_remove,
1499         .driver = {
1500                 .pm = &vmw_pm_ops
1501         }
1502 };
1503
1504 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1505 {
1506         return drm_get_pci_dev(pdev, ent, &driver);
1507 }
1508
1509 static int __init vmwgfx_init(void)
1510 {
1511         int ret;
1512         ret = drm_pci_init(&driver, &vmw_pci_driver);
1513         if (ret)
1514                 DRM_ERROR("Failed initializing DRM.\n");
1515         return ret;
1516 }
1517
1518 static void __exit vmwgfx_exit(void)
1519 {
1520         drm_pci_exit(&driver, &vmw_pci_driver);
1521 }
1522
1523 module_init(vmwgfx_init);
1524 module_exit(vmwgfx_exit);
1525
1526 MODULE_AUTHOR("VMware Inc. and others");
1527 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1528 MODULE_LICENSE("GPL and additional rights");
1529 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1530                __stringify(VMWGFX_DRIVER_MINOR) "."
1531                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1532                "0");