1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "vmwgfx_drv.h"
31 #define VMW_FENCE_WRAP (1 << 24)
33 irqreturn_t vmw_irq_handler(DRM_IRQ_ARGS)
35 struct drm_device *dev = (struct drm_device *)arg;
36 struct vmw_private *dev_priv = vmw_priv(dev);
39 spin_lock(&dev_priv->irq_lock);
40 status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
41 spin_unlock(&dev_priv->irq_lock);
43 if (status & SVGA_IRQFLAG_ANY_FENCE)
44 wake_up_all(&dev_priv->fence_queue);
45 if (status & SVGA_IRQFLAG_FIFO_PROGRESS)
46 wake_up_all(&dev_priv->fifo_queue);
49 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
56 static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t sequence)
60 mutex_lock(&dev_priv->hw_mutex);
61 busy = vmw_read(dev_priv, SVGA_REG_BUSY);
62 mutex_unlock(&dev_priv->hw_mutex);
68 bool vmw_fence_signaled(struct vmw_private *dev_priv,
71 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
72 struct vmw_fifo_state *fifo_state;
75 if (likely(dev_priv->last_read_sequence - sequence < VMW_FENCE_WRAP))
78 dev_priv->last_read_sequence = ioread32(fifo_mem + SVGA_FIFO_FENCE);
79 if (likely(dev_priv->last_read_sequence - sequence < VMW_FENCE_WRAP))
82 fifo_state = &dev_priv->fifo;
83 if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
84 vmw_fifo_idle(dev_priv, sequence))
88 * Below is to signal stale fences that have wrapped.
89 * First, block fence submission.
92 down_read(&fifo_state->rwsem);
95 * Then check if the sequence is higher than what we've actually
96 * emitted. Then the fence is stale and signaled.
99 ret = ((dev_priv->fence_seq - sequence) > VMW_FENCE_WRAP);
100 up_read(&fifo_state->rwsem);
105 int vmw_fallback_wait(struct vmw_private *dev_priv,
110 unsigned long timeout)
112 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
117 unsigned long end_jiffies = jiffies + timeout;
118 bool (*wait_condition)(struct vmw_private *, uint32_t);
121 wait_condition = (fifo_idle) ? &vmw_fifo_idle :
125 * Block command submission while waiting for idle.
129 down_read(&fifo_state->rwsem);
130 signal_seq = dev_priv->fence_seq;
134 prepare_to_wait(&dev_priv->fence_queue, &__wait,
136 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
137 if (wait_condition(dev_priv, sequence))
139 if (time_after_eq(jiffies, end_jiffies)) {
140 DRM_ERROR("SVGA device lockup.\n");
145 else if ((++count & 0x0F) == 0) {
147 * FIXME: Use schedule_hr_timeout here for
148 * newer kernels and lower CPU utilization.
151 __set_current_state(TASK_RUNNING);
153 __set_current_state((interruptible) ?
155 TASK_UNINTERRUPTIBLE);
157 if (interruptible && signal_pending(current)) {
162 finish_wait(&dev_priv->fence_queue, &__wait);
163 if (ret == 0 && fifo_idle) {
164 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
165 iowrite32(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
167 wake_up_all(&dev_priv->fence_queue);
169 up_read(&fifo_state->rwsem);
174 int vmw_wait_fence(struct vmw_private *dev_priv,
175 bool lazy, uint32_t sequence,
176 bool interruptible, unsigned long timeout)
179 unsigned long irq_flags;
180 struct vmw_fifo_state *fifo = &dev_priv->fifo;
182 if (likely(dev_priv->last_read_sequence - sequence < VMW_FENCE_WRAP))
185 if (likely(vmw_fence_signaled(dev_priv, sequence)))
188 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
190 if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE))
191 return vmw_fallback_wait(dev_priv, lazy, true, sequence,
192 interruptible, timeout);
194 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
195 return vmw_fallback_wait(dev_priv, lazy, false, sequence,
196 interruptible, timeout);
198 mutex_lock(&dev_priv->hw_mutex);
199 if (atomic_add_return(1, &dev_priv->fence_queue_waiters) > 0) {
200 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
201 outl(SVGA_IRQFLAG_ANY_FENCE,
202 dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
203 vmw_write(dev_priv, SVGA_REG_IRQMASK,
204 vmw_read(dev_priv, SVGA_REG_IRQMASK) |
205 SVGA_IRQFLAG_ANY_FENCE);
206 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
208 mutex_unlock(&dev_priv->hw_mutex);
211 ret = wait_event_interruptible_timeout
212 (dev_priv->fence_queue,
213 vmw_fence_signaled(dev_priv, sequence),
216 ret = wait_event_timeout
217 (dev_priv->fence_queue,
218 vmw_fence_signaled(dev_priv, sequence),
221 if (unlikely(ret == 0))
223 else if (likely(ret > 0))
226 mutex_lock(&dev_priv->hw_mutex);
227 if (atomic_dec_and_test(&dev_priv->fence_queue_waiters)) {
228 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
229 vmw_write(dev_priv, SVGA_REG_IRQMASK,
230 vmw_read(dev_priv, SVGA_REG_IRQMASK) &
231 ~SVGA_IRQFLAG_ANY_FENCE);
232 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
234 mutex_unlock(&dev_priv->hw_mutex);
239 void vmw_irq_preinstall(struct drm_device *dev)
241 struct vmw_private *dev_priv = vmw_priv(dev);
244 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
247 spin_lock_init(&dev_priv->irq_lock);
248 status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
249 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
252 int vmw_irq_postinstall(struct drm_device *dev)
257 void vmw_irq_uninstall(struct drm_device *dev)
259 struct vmw_private *dev_priv = vmw_priv(dev);
262 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
265 mutex_lock(&dev_priv->hw_mutex);
266 vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
267 mutex_unlock(&dev_priv->hw_mutex);
269 status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
270 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
273 #define VMW_FENCE_WAIT_TIMEOUT 3*HZ;
275 int vmw_fence_wait_ioctl(struct drm_device *dev, void *data,
276 struct drm_file *file_priv)
278 struct drm_vmw_fence_wait_arg *arg =
279 (struct drm_vmw_fence_wait_arg *)data;
280 unsigned long timeout;
282 if (!arg->cookie_valid) {
283 arg->cookie_valid = 1;
284 arg->kernel_cookie = jiffies + VMW_FENCE_WAIT_TIMEOUT;
288 if (time_after_eq(timeout, (unsigned long)arg->kernel_cookie))
291 timeout = (unsigned long)arg->kernel_cookie - timeout;
292 return vmw_wait_fence(vmw_priv(dev), true, arg->sequence, true, timeout);