drivers/gpu/drm/zte/zx_plane_regs.h

   1 /*
   2  * Copyright 2016 Linaro Ltd.
   3  * Copyright 2016 ZTE Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #ifndef __ZX_PLANE_REGS_H__
  12 #define __ZX_PLANE_REGS_H__
  13
  14 /* GL registers */
  15 #define GL_CTRL0                        0x00
  16 #define GL_UPDATE                       BIT(5)
  17 #define GL_CTRL1                        0x04
  18 #define GL_DATA_FMT_SHIFT               0
  19 #define GL_DATA_FMT_MASK                (0xf << GL_DATA_FMT_SHIFT)
  20 #define GL_FMT_ARGB8888                 0
  21 #define GL_FMT_RGB888                   1
  22 #define GL_FMT_RGB565                   2
  23 #define GL_FMT_ARGB1555                 3
  24 #define GL_FMT_ARGB4444                 4
  25 #define GL_CTRL2                        0x08
  26 #define GL_GLOBAL_ALPHA_SHIFT           8
  27 #define GL_GLOBAL_ALPHA_MASK            (0xff << GL_GLOBAL_ALPHA_SHIFT)
  28 #define GL_CTRL3                        0x0c
  29 #define GL_SCALER_BYPASS_MODE           BIT(0)
  30 #define GL_STRIDE                       0x18
  31 #define GL_ADDR                         0x1c
  32 #define GL_SRC_SIZE                     0x38
  33 #define GL_SRC_W_SHIFT                  16
  34 #define GL_SRC_W_MASK                   (0x3fff << GL_SRC_W_SHIFT)
  35 #define GL_SRC_H_SHIFT                  0
  36 #define GL_SRC_H_MASK                   (0x3fff << GL_SRC_H_SHIFT)
  37 #define GL_POS_START                    0x9c
  38 #define GL_POS_END                      0xa0
  39 #define GL_POS_X_SHIFT                  16
  40 #define GL_POS_X_MASK                   (0x1fff << GL_POS_X_SHIFT)
  41 #define GL_POS_Y_SHIFT                  0
  42 #define GL_POS_Y_MASK                   (0x1fff << GL_POS_Y_SHIFT)
  43
  44 #define GL_SRC_W(x)     (((x) << GL_SRC_W_SHIFT) & GL_SRC_W_MASK)
  45 #define GL_SRC_H(x)     (((x) << GL_SRC_H_SHIFT) & GL_SRC_H_MASK)
  46 #define GL_POS_X(x)     (((x) << GL_POS_X_SHIFT) & GL_POS_X_MASK)
  47 #define GL_POS_Y(x)     (((x) << GL_POS_Y_SHIFT) & GL_POS_Y_MASK)
  48
  49 /* CSC registers */
  50 #define CSC_CTRL0                       0x30
  51 #define CSC_COV_MODE_SHIFT              16
  52 #define CSC_COV_MODE_MASK               (0xffff << CSC_COV_MODE_SHIFT)
  53 #define CSC_BT601_IMAGE_RGB2YCBCR       0
  54 #define CSC_BT601_IMAGE_YCBCR2RGB       1
  55 #define CSC_BT601_VIDEO_RGB2YCBCR       2
  56 #define CSC_BT601_VIDEO_YCBCR2RGB       3
  57 #define CSC_BT709_IMAGE_RGB2YCBCR       4
  58 #define CSC_BT709_IMAGE_YCBCR2RGB       5
  59 #define CSC_BT709_VIDEO_RGB2YCBCR       6
  60 #define CSC_BT709_VIDEO_YCBCR2RGB       7
  61 #define CSC_BT2020_IMAGE_RGB2YCBCR      8
  62 #define CSC_BT2020_IMAGE_YCBCR2RGB      9
  63 #define CSC_BT2020_VIDEO_RGB2YCBCR      10
  64 #define CSC_BT2020_VIDEO_YCBCR2RGB      11
  65 #define CSC_WORK_ENABLE                 BIT(0)
  66
  67 /* RSZ registers */
  68 #define RSZ_SRC_CFG                     0x00
  69 #define RSZ_DEST_CFG                    0x04
  70 #define RSZ_ENABLE_CFG                  0x14
  71
  72 #define RSZ_VER_SHIFT                   16
  73 #define RSZ_VER_MASK                    (0xffff << RSZ_VER_SHIFT)
  74 #define RSZ_HOR_SHIFT                   0
  75 #define RSZ_HOR_MASK                    (0xffff << RSZ_HOR_SHIFT)
  76
  77 #define RSZ_VER(x)      (((x) << RSZ_VER_SHIFT) & RSZ_VER_MASK)
  78 #define RSZ_HOR(x)      (((x) << RSZ_HOR_SHIFT) & RSZ_HOR_MASK)
  79
  80 /* HBSC registers */
  81 #define HBSC_SATURATION                 0x00
  82 #define HBSC_HUE                        0x04
  83 #define HBSC_BRIGHT                     0x08
  84 #define HBSC_CONTRAST                   0x0c
  85 #define HBSC_THRESHOLD_COL1             0x10
  86 #define HBSC_THRESHOLD_COL2             0x14
  87 #define HBSC_THRESHOLD_COL3             0x18
  88 #define HBSC_CTRL0                      0x28
  89 #define HBSC_CTRL_EN                    BIT(2)
  90
  91 #endif /* __ZX_PLANE_REGS_H__ */