4 * Copyright (c) 2010-2013, NVIDIA Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/list.h>
23 #include <linux/module.h>
24 #include <linux/of_device.h>
26 #include <linux/slab.h>
28 #define CREATE_TRACE_POINTS
29 #include <trace/events/host1x.h>
30 #undef CREATE_TRACE_POINTS
38 #include "hw/host1x01.h"
39 #include "hw/host1x02.h"
40 #include "hw/host1x04.h"
41 #include "hw/host1x05.h"
43 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
45 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
47 writel(v, sync_regs + r);
50 u32 host1x_sync_readl(struct host1x *host1x, u32 r)
52 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
54 return readl(sync_regs + r);
57 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
59 writel(v, ch->regs + r);
62 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
64 return readl(ch->regs + r);
67 static const struct host1x_info host1x01_info = {
72 .init = host1x01_init,
73 .sync_offset = 0x3000,
74 .dma_mask = DMA_BIT_MASK(32),
77 static const struct host1x_info host1x02_info = {
82 .init = host1x02_init,
83 .sync_offset = 0x3000,
84 .dma_mask = DMA_BIT_MASK(32),
87 static const struct host1x_info host1x04_info = {
92 .init = host1x04_init,
93 .sync_offset = 0x2100,
94 .dma_mask = DMA_BIT_MASK(34),
97 static const struct host1x_info host1x05_info = {
102 .init = host1x05_init,
103 .sync_offset = 0x2100,
104 .dma_mask = DMA_BIT_MASK(34),
107 static const struct of_device_id host1x_of_match[] = {
108 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
109 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
110 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
111 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
112 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
115 MODULE_DEVICE_TABLE(of, host1x_of_match);
117 static int host1x_probe(struct platform_device *pdev)
119 const struct of_device_id *id;
121 struct resource *regs;
125 id = of_match_device(host1x_of_match, &pdev->dev);
129 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
131 dev_err(&pdev->dev, "failed to get registers\n");
135 syncpt_irq = platform_get_irq(pdev, 0);
136 if (syncpt_irq < 0) {
137 dev_err(&pdev->dev, "failed to get IRQ\n");
141 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
145 mutex_init(&host->devices_lock);
146 INIT_LIST_HEAD(&host->devices);
147 INIT_LIST_HEAD(&host->list);
148 host->dev = &pdev->dev;
149 host->info = id->data;
151 /* set common host1x device data */
152 platform_set_drvdata(pdev, host);
154 host->regs = devm_ioremap_resource(&pdev->dev, regs);
155 if (IS_ERR(host->regs))
156 return PTR_ERR(host->regs);
158 dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
160 if (host->info->init) {
161 err = host->info->init(host);
166 host->clk = devm_clk_get(&pdev->dev, NULL);
167 if (IS_ERR(host->clk)) {
168 dev_err(&pdev->dev, "failed to get clock\n");
169 err = PTR_ERR(host->clk);
173 host->rst = devm_reset_control_get(&pdev->dev, "host1x");
174 if (IS_ERR(host->rst)) {
175 err = PTR_ERR(host->clk);
176 dev_err(&pdev->dev, "failed to get reset: %d\n", err);
180 if (iommu_present(&platform_bus_type)) {
181 struct iommu_domain_geometry *geometry;
184 host->domain = iommu_domain_alloc(&platform_bus_type);
188 err = iommu_attach_device(host->domain, &pdev->dev);
190 goto fail_free_domain;
192 geometry = &host->domain->geometry;
194 order = __ffs(host->domain->pgsize_bitmap);
195 init_iova_domain(&host->iova, 1UL << order,
196 geometry->aperture_start >> order,
197 geometry->aperture_end >> order);
198 host->iova_end = geometry->aperture_end;
201 err = host1x_channel_list_init(host);
203 dev_err(&pdev->dev, "failed to initialize channel list\n");
204 goto fail_detach_device;
207 err = clk_prepare_enable(host->clk);
209 dev_err(&pdev->dev, "failed to enable clock\n");
210 goto fail_detach_device;
213 err = reset_control_deassert(host->rst);
215 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
216 goto fail_unprepare_disable;
219 err = host1x_syncpt_init(host);
221 dev_err(&pdev->dev, "failed to initialize syncpts\n");
222 goto fail_reset_assert;
225 err = host1x_intr_init(host, syncpt_irq);
227 dev_err(&pdev->dev, "failed to initialize interrupts\n");
228 goto fail_deinit_syncpt;
231 host1x_debug_init(host);
233 err = host1x_register(host);
235 goto fail_deinit_intr;
240 host1x_intr_deinit(host);
242 host1x_syncpt_deinit(host);
244 reset_control_assert(host->rst);
245 fail_unprepare_disable:
246 clk_disable_unprepare(host->clk);
249 put_iova_domain(&host->iova);
250 iommu_detach_device(host->domain, &pdev->dev);
254 iommu_domain_free(host->domain);
259 static int host1x_remove(struct platform_device *pdev)
261 struct host1x *host = platform_get_drvdata(pdev);
263 host1x_unregister(host);
264 host1x_intr_deinit(host);
265 host1x_syncpt_deinit(host);
266 reset_control_assert(host->rst);
267 clk_disable_unprepare(host->clk);
270 put_iova_domain(&host->iova);
271 iommu_detach_device(host->domain, &pdev->dev);
272 iommu_domain_free(host->domain);
278 static struct platform_driver tegra_host1x_driver = {
280 .name = "tegra-host1x",
281 .of_match_table = host1x_of_match,
283 .probe = host1x_probe,
284 .remove = host1x_remove,
287 static struct platform_driver * const drivers[] = {
288 &tegra_host1x_driver,
292 static int __init tegra_host1x_init(void)
296 err = bus_register(&host1x_bus_type);
300 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
302 bus_unregister(&host1x_bus_type);
306 module_init(tegra_host1x_init);
308 static void __exit tegra_host1x_exit(void)
310 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
311 bus_unregister(&host1x_bus_type);
313 module_exit(tegra_host1x_exit);
315 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
316 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
317 MODULE_DESCRIPTION("Host1x driver for Tegra products");
318 MODULE_LICENSE("GPL");