2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/gpio.h>
13 #include <linux/hdmi.h>
14 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/clk/tegra.h>
20 #include <drm/drm_edid.h>
25 #include "host1x_client.h"
28 struct host1x_client client;
29 struct tegra_output output;
32 struct regulator *vdd;
33 struct regulator *pll;
38 struct clk *clk_parent;
41 unsigned int audio_source;
42 unsigned int audio_freq;
46 struct drm_info_list *debugfs_files;
47 struct drm_minor *minor;
48 struct dentry *debugfs;
51 static inline struct tegra_hdmi *
52 host1x_client_to_hdmi(struct host1x_client *client)
54 return container_of(client, struct tegra_hdmi, client);
57 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
59 return container_of(output, struct tegra_hdmi, output);
62 #define HDMI_AUDIOCLK_FREQ 216000000
63 #define HDMI_REKEY_DEFAULT 56
71 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
74 return readl(hdmi->regs + (reg << 2));
77 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
80 writel(val, hdmi->regs + (reg << 2));
83 struct tegra_hdmi_audio_config {
90 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
91 { 25200000, 4096, 25200, 24000 },
92 { 27000000, 4096, 27000, 24000 },
93 { 74250000, 4096, 74250, 24000 },
94 { 148500000, 4096, 148500, 24000 },
98 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
99 { 25200000, 5880, 26250, 25000 },
100 { 27000000, 5880, 28125, 25000 },
101 { 74250000, 4704, 61875, 20000 },
102 { 148500000, 4704, 123750, 20000 },
106 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
107 { 25200000, 6144, 25200, 24000 },
108 { 27000000, 6144, 27000, 24000 },
109 { 74250000, 6144, 74250, 24000 },
110 { 148500000, 6144, 148500, 24000 },
114 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
115 { 25200000, 11760, 26250, 25000 },
116 { 27000000, 11760, 28125, 25000 },
117 { 74250000, 9408, 61875, 20000 },
118 { 148500000, 9408, 123750, 20000 },
122 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
123 { 25200000, 12288, 25200, 24000 },
124 { 27000000, 12288, 27000, 24000 },
125 { 74250000, 12288, 74250, 24000 },
126 { 148500000, 12288, 148500, 24000 },
130 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
131 { 25200000, 23520, 26250, 25000 },
132 { 27000000, 23520, 28125, 25000 },
133 { 74250000, 18816, 61875, 20000 },
134 { 148500000, 18816, 123750, 20000 },
138 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
139 { 25200000, 24576, 25200, 24000 },
140 { 27000000, 24576, 27000, 24000 },
141 { 74250000, 24576, 74250, 24000 },
142 { 148500000, 24576, 148500, 24000 },
154 static const struct tmds_config tegra2_tmds_config[] = {
155 { /* slow pixel clock modes */
157 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
158 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
159 SOR_PLL_TX_REG_LOAD(3),
160 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
161 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
162 PE_CURRENT1(PE_CURRENT_0_0_mA) |
163 PE_CURRENT2(PE_CURRENT_0_0_mA) |
164 PE_CURRENT3(PE_CURRENT_0_0_mA),
165 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
166 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
167 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
168 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
170 { /* high pixel clock modes */
172 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
173 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
174 SOR_PLL_TX_REG_LOAD(3),
175 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
176 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
177 PE_CURRENT1(PE_CURRENT_6_0_mA) |
178 PE_CURRENT2(PE_CURRENT_6_0_mA) |
179 PE_CURRENT3(PE_CURRENT_6_0_mA),
180 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
181 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
182 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
183 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
187 static const struct tmds_config tegra3_tmds_config[] = {
190 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
191 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
192 SOR_PLL_TX_REG_LOAD(0),
193 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
194 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
195 PE_CURRENT1(PE_CURRENT_0_0_mA) |
196 PE_CURRENT2(PE_CURRENT_0_0_mA) |
197 PE_CURRENT3(PE_CURRENT_0_0_mA),
198 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
199 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
200 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
201 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
202 }, { /* 720p modes */
204 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
205 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
206 SOR_PLL_TX_REG_LOAD(0),
207 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
208 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
209 PE_CURRENT1(PE_CURRENT_5_0_mA) |
210 PE_CURRENT2(PE_CURRENT_5_0_mA) |
211 PE_CURRENT3(PE_CURRENT_5_0_mA),
212 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
213 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
214 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
215 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
216 }, { /* 1080p modes */
218 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
219 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
220 SOR_PLL_TX_REG_LOAD(0),
221 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
222 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
223 PE_CURRENT1(PE_CURRENT_5_0_mA) |
224 PE_CURRENT2(PE_CURRENT_5_0_mA) |
225 PE_CURRENT3(PE_CURRENT_5_0_mA),
226 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
227 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
228 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
229 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
233 static const struct tegra_hdmi_audio_config *
234 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
236 const struct tegra_hdmi_audio_config *table;
238 switch (audio_freq) {
240 table = tegra_hdmi_audio_32k;
244 table = tegra_hdmi_audio_44_1k;
248 table = tegra_hdmi_audio_48k;
252 table = tegra_hdmi_audio_88_2k;
256 table = tegra_hdmi_audio_96k;
260 table = tegra_hdmi_audio_176_4k;
264 table = tegra_hdmi_audio_192k;
271 while (table->pclk) {
272 if (table->pclk == pclk)
281 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
283 const unsigned int freqs[] = {
284 32000, 44100, 48000, 88200, 96000, 176400, 192000
288 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
289 unsigned int f = freqs[i];
290 unsigned int eight_half;
301 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
302 value = AUDIO_FS_LOW(eight_half - delta) |
303 AUDIO_FS_HIGH(eight_half + delta);
304 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
308 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
310 struct device_node *node = hdmi->dev->of_node;
311 const struct tegra_hdmi_audio_config *config;
312 unsigned int offset = 0;
315 switch (hdmi->audio_source) {
317 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
321 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
325 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
329 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
330 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
331 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
332 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
334 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
335 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
337 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
338 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
339 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
342 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
344 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
345 hdmi->audio_freq, pclk);
349 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
351 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
352 AUDIO_N_VALUE(config->n - 1);
353 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
355 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
356 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
358 value = ACR_SUBPACK_CTS(config->cts);
359 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
361 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
362 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
364 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
365 value &= ~AUDIO_N_RESETF;
366 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
368 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
369 switch (hdmi->audio_freq) {
371 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
375 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
379 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
383 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
387 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
391 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
395 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
399 tegra_hdmi_writel(hdmi, config->aval, offset);
402 tegra_hdmi_setup_audio_fs_tables(hdmi);
407 static inline unsigned long tegra_hdmi_subpack(const u8 *ptr, size_t size)
409 unsigned long value = 0;
412 for (i = size; i > 0; i--)
413 value = (value << 8) | ptr[i - 1];
418 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
421 const u8 *ptr = data;
422 unsigned long offset;
427 case HDMI_INFOFRAME_TYPE_AVI:
428 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
431 case HDMI_INFOFRAME_TYPE_AUDIO:
432 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
435 case HDMI_INFOFRAME_TYPE_VENDOR:
436 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
440 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
445 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
446 INFOFRAME_HEADER_VERSION(ptr[1]) |
447 INFOFRAME_HEADER_LEN(ptr[2]);
448 tegra_hdmi_writel(hdmi, value, offset);
452 * Each subpack contains 7 bytes, divided into:
453 * - subpack_low: bytes 0 - 3
454 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
456 for (i = 3, j = 0; i < size; i += 7, j += 8) {
457 size_t rem = size - i, num = min_t(size_t, rem, 4);
459 value = tegra_hdmi_subpack(&ptr[i], num);
460 tegra_hdmi_writel(hdmi, value, offset++);
462 num = min_t(size_t, rem - num, 3);
464 value = tegra_hdmi_subpack(&ptr[i + 4], num);
465 tegra_hdmi_writel(hdmi, value, offset++);
469 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
470 struct drm_display_mode *mode)
472 struct hdmi_avi_infoframe frame;
477 tegra_hdmi_writel(hdmi, 0,
478 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
482 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
484 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
488 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
490 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
494 tegra_hdmi_write_infopack(hdmi, buffer, err);
496 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
497 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
500 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
502 struct hdmi_audio_infoframe frame;
507 tegra_hdmi_writel(hdmi, 0,
508 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
512 err = hdmi_audio_infoframe_init(&frame);
514 dev_err(hdmi->dev, "failed to initialize audio infoframe: %d\n",
521 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
523 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
529 * The audio infoframe has only one set of subpack registers, so the
530 * infoframe needs to be truncated. One set of subpack registers can
531 * contain 7 bytes. Including the 3 byte header only the first 10
532 * bytes can be programmed.
534 tegra_hdmi_write_infopack(hdmi, buffer, min(10, err));
536 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
537 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
540 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
542 struct hdmi_vendor_infoframe frame;
548 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
549 value &= ~GENERIC_CTRL_ENABLE;
550 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
554 hdmi_vendor_infoframe_init(&frame);
555 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
557 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
559 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
564 tegra_hdmi_write_infopack(hdmi, buffer, err);
566 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
567 value |= GENERIC_CTRL_ENABLE;
568 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
571 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
572 const struct tmds_config *tmds)
576 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
577 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
578 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
580 value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
581 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
584 static int tegra_output_hdmi_enable(struct tegra_output *output)
586 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
587 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
588 struct drm_display_mode *mode = &dc->base.mode;
589 struct tegra_hdmi *hdmi = to_hdmi(output);
590 struct device_node *node = hdmi->dev->of_node;
591 unsigned int pulse_start, div82, pclk;
592 const struct tmds_config *tmds;
593 unsigned int num_tmds;
598 pclk = mode->clock * 1000;
599 h_sync_width = mode->hsync_end - mode->hsync_start;
600 h_back_porch = mode->htotal - mode->hsync_end;
601 h_front_porch = mode->hsync_start - mode->hdisplay;
603 err = regulator_enable(hdmi->vdd);
605 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
609 err = regulator_enable(hdmi->pll);
611 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
616 * This assumes that the display controller will divide its parent
617 * clock by 2 to generate the pixel clock.
619 err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
621 dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
625 err = clk_set_rate(hdmi->clk, pclk);
629 err = clk_enable(hdmi->clk);
631 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
635 tegra_periph_reset_assert(hdmi->clk);
636 usleep_range(1000, 2000);
637 tegra_periph_reset_deassert(hdmi->clk);
639 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
640 DC_DISP_DISP_TIMING_OPTIONS);
641 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
642 DC_DISP_DISP_COLOR_CONTROL);
644 /* video_preamble uses h_pulse2 */
645 pulse_start = 1 + h_sync_width + h_back_porch - 10;
647 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
649 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
651 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
653 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
654 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
656 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
658 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
661 value = HDMI_SRC_DISPLAYB;
663 value = HDMI_SRC_DISPLAYA;
665 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
666 (mode->vdisplay == 576)))
667 tegra_hdmi_writel(hdmi,
668 value | ARM_VIDEO_RANGE_FULL,
669 HDMI_NV_PDISP_INPUT_CONTROL);
671 tegra_hdmi_writel(hdmi,
672 value | ARM_VIDEO_RANGE_LIMITED,
673 HDMI_NV_PDISP_INPUT_CONTROL);
675 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
676 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
677 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
680 err = tegra_hdmi_setup_audio(hdmi, pclk);
685 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
687 * TODO: add ELD support
691 rekey = HDMI_REKEY_DEFAULT;
692 value = HDMI_CTRL_REKEY(rekey);
693 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
694 h_front_porch - rekey - 18) / 32);
697 value |= HDMI_CTRL_ENABLE;
699 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
702 tegra_hdmi_writel(hdmi, 0x0,
703 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
705 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
706 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
708 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
709 tegra_hdmi_setup_audio_infoframe(hdmi);
710 tegra_hdmi_setup_stereo_infoframe(hdmi);
713 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
714 num_tmds = ARRAY_SIZE(tegra3_tmds_config);
715 tmds = tegra3_tmds_config;
717 num_tmds = ARRAY_SIZE(tegra2_tmds_config);
718 tmds = tegra2_tmds_config;
721 for (i = 0; i < num_tmds; i++) {
722 if (pclk <= tmds[i].pclk) {
723 tegra_hdmi_setup_tmds(hdmi, &tmds[i]);
728 tegra_hdmi_writel(hdmi,
729 SOR_SEQ_CTL_PU_PC(0) |
730 SOR_SEQ_PU_PC_ALT(0) |
732 SOR_SEQ_PD_PC_ALT(8),
733 HDMI_NV_PDISP_SOR_SEQ_CTL);
735 value = SOR_SEQ_INST_WAIT_TIME(1) |
736 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
738 SOR_SEQ_INST_PIN_A_LOW |
739 SOR_SEQ_INST_PIN_B_LOW |
740 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
742 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
743 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
746 value &= ~SOR_CSTM_ROTCLK(~0);
747 value |= SOR_CSTM_ROTCLK(2);
748 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
750 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
751 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
752 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
755 tegra_hdmi_writel(hdmi,
756 SOR_PWR_NORMAL_STATE_PU |
757 SOR_PWR_NORMAL_START_NORMAL |
758 SOR_PWR_SAFE_STATE_PD |
759 SOR_PWR_SETTING_NEW_TRIGGER,
760 HDMI_NV_PDISP_SOR_PWR);
761 tegra_hdmi_writel(hdmi,
762 SOR_PWR_NORMAL_STATE_PU |
763 SOR_PWR_NORMAL_START_NORMAL |
764 SOR_PWR_SAFE_STATE_PD |
765 SOR_PWR_SETTING_NEW_DONE,
766 HDMI_NV_PDISP_SOR_PWR);
769 BUG_ON(--retries < 0);
770 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
771 } while (value & SOR_PWR_SETTING_NEW_PENDING);
773 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
774 SOR_STATE_ASY_OWNER_HEAD0 |
775 SOR_STATE_ASY_SUBOWNER_BOTH |
776 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
777 SOR_STATE_ASY_DEPOL_POS;
779 /* setup sync polarities */
780 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
781 value |= SOR_STATE_ASY_HSYNCPOL_POS;
783 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
784 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
786 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
787 value |= SOR_STATE_ASY_VSYNCPOL_POS;
789 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
790 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
792 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
794 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
795 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
797 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
798 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
799 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
800 HDMI_NV_PDISP_SOR_STATE1);
801 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
803 tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
805 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
806 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
807 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
809 value = DISP_CTRL_MODE_C_DISPLAY;
810 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
812 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
813 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
815 /* TODO: add HDCP support */
820 static int tegra_output_hdmi_disable(struct tegra_output *output)
822 struct tegra_hdmi *hdmi = to_hdmi(output);
824 tegra_periph_reset_assert(hdmi->clk);
825 clk_disable(hdmi->clk);
826 regulator_disable(hdmi->pll);
827 regulator_disable(hdmi->vdd);
832 static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
833 struct clk *clk, unsigned long pclk)
835 struct tegra_hdmi *hdmi = to_hdmi(output);
839 err = clk_set_parent(clk, hdmi->clk_parent);
841 dev_err(output->dev, "failed to set parent: %d\n", err);
845 base = clk_get_parent(hdmi->clk_parent);
848 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
849 * respectively, each of which divides the base pll_d by 2.
851 err = clk_set_rate(base, pclk * 2);
854 "failed to set base clock rate to %lu Hz\n",
860 static int tegra_output_hdmi_check_mode(struct tegra_output *output,
861 struct drm_display_mode *mode,
862 enum drm_mode_status *status)
864 struct tegra_hdmi *hdmi = to_hdmi(output);
865 unsigned long pclk = mode->clock * 1000;
869 parent = clk_get_parent(hdmi->clk_parent);
871 err = clk_round_rate(parent, pclk * 4);
873 *status = MODE_NOCLOCK;
880 static const struct tegra_output_ops hdmi_ops = {
881 .enable = tegra_output_hdmi_enable,
882 .disable = tegra_output_hdmi_disable,
883 .setup_clock = tegra_output_hdmi_setup_clock,
884 .check_mode = tegra_output_hdmi_check_mode,
887 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
889 struct drm_info_node *node = s->private;
890 struct tegra_hdmi *hdmi = node->info_ent->data;
893 err = clk_enable(hdmi->clk);
897 #define DUMP_REG(name) \
898 seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \
899 tegra_hdmi_readl(hdmi, name))
901 DUMP_REG(HDMI_CTXSW);
902 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
903 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
904 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
905 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
906 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
907 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
908 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
909 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
910 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
911 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
912 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
913 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
914 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
915 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
916 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
917 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
918 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
919 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
920 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
921 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
922 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
923 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
924 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
925 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
926 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
927 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
928 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
929 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
930 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
931 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
932 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
933 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
934 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
935 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
936 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
937 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
938 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
939 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
940 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
941 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
942 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
943 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
944 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
945 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
946 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
947 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
948 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
949 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
950 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
951 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
952 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
953 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
954 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
955 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
956 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
957 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
958 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
959 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
960 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
961 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
962 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
963 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
964 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
965 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
966 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
967 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
968 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
969 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
970 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
971 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
972 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
973 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
974 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
975 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
976 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
977 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
978 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
979 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
980 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
981 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
982 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
983 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
984 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
985 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
986 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
987 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
988 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
989 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
990 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
991 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
992 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
993 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
994 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
995 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
996 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
997 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
998 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
999 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1000 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1001 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1002 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1003 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1004 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1005 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1006 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1007 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1008 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1009 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1010 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1011 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1012 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1013 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1014 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1015 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1016 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1017 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1018 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1019 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1020 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1021 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1022 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1023 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1024 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1025 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1026 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1027 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1028 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1029 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1030 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1031 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1032 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1033 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1034 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1035 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1036 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1037 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1038 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1039 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1040 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1041 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1042 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1043 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1044 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1045 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1046 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1047 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1048 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1049 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1050 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1051 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1052 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1053 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1054 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1055 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1056 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1057 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1061 clk_disable(hdmi->clk);
1066 static struct drm_info_list debugfs_files[] = {
1067 { "regs", tegra_hdmi_show_regs, 0, NULL },
1070 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1071 struct drm_minor *minor)
1076 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1080 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1082 if (!hdmi->debugfs_files) {
1087 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1088 hdmi->debugfs_files[i].data = hdmi;
1090 err = drm_debugfs_create_files(hdmi->debugfs_files,
1091 ARRAY_SIZE(debugfs_files),
1092 hdmi->debugfs, minor);
1096 hdmi->minor = minor;
1101 kfree(hdmi->debugfs_files);
1102 hdmi->debugfs_files = NULL;
1104 debugfs_remove(hdmi->debugfs);
1105 hdmi->debugfs = NULL;
1110 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1112 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1116 kfree(hdmi->debugfs_files);
1117 hdmi->debugfs_files = NULL;
1119 debugfs_remove(hdmi->debugfs);
1120 hdmi->debugfs = NULL;
1125 static int tegra_hdmi_drm_init(struct host1x_client *client,
1126 struct drm_device *drm)
1128 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1131 hdmi->output.type = TEGRA_OUTPUT_HDMI;
1132 hdmi->output.dev = client->dev;
1133 hdmi->output.ops = &hdmi_ops;
1135 err = tegra_output_init(drm, &hdmi->output);
1137 dev_err(client->dev, "output setup failed: %d\n", err);
1141 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1142 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1144 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1150 static int tegra_hdmi_drm_exit(struct host1x_client *client)
1152 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1155 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1156 err = tegra_hdmi_debugfs_exit(hdmi);
1158 dev_err(client->dev, "debugfs cleanup failed: %d\n",
1162 err = tegra_output_disable(&hdmi->output);
1164 dev_err(client->dev, "output failed to disable: %d\n", err);
1168 err = tegra_output_exit(&hdmi->output);
1170 dev_err(client->dev, "output cleanup failed: %d\n", err);
1177 static const struct host1x_client_ops hdmi_client_ops = {
1178 .drm_init = tegra_hdmi_drm_init,
1179 .drm_exit = tegra_hdmi_drm_exit,
1182 static int tegra_hdmi_probe(struct platform_device *pdev)
1184 struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
1185 struct tegra_hdmi *hdmi;
1186 struct resource *regs;
1189 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1193 hdmi->dev = &pdev->dev;
1194 hdmi->audio_source = AUTO;
1195 hdmi->audio_freq = 44100;
1196 hdmi->stereo = false;
1199 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1200 if (IS_ERR(hdmi->clk)) {
1201 dev_err(&pdev->dev, "failed to get clock\n");
1202 return PTR_ERR(hdmi->clk);
1205 err = clk_prepare(hdmi->clk);
1209 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1210 if (IS_ERR(hdmi->clk_parent))
1211 return PTR_ERR(hdmi->clk_parent);
1213 err = clk_prepare(hdmi->clk_parent);
1217 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1219 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1223 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1224 if (IS_ERR(hdmi->vdd)) {
1225 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1226 return PTR_ERR(hdmi->vdd);
1229 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1230 if (IS_ERR(hdmi->pll)) {
1231 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1232 return PTR_ERR(hdmi->pll);
1235 hdmi->output.dev = &pdev->dev;
1237 err = tegra_output_parse_dt(&hdmi->output);
1241 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1245 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1246 if (IS_ERR(hdmi->regs))
1247 return PTR_ERR(hdmi->regs);
1249 err = platform_get_irq(pdev, 0);
1255 hdmi->client.ops = &hdmi_client_ops;
1256 INIT_LIST_HEAD(&hdmi->client.list);
1257 hdmi->client.dev = &pdev->dev;
1259 err = host1x_register_client(host1x, &hdmi->client);
1261 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1266 platform_set_drvdata(pdev, hdmi);
1271 static int tegra_hdmi_remove(struct platform_device *pdev)
1273 struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
1274 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1277 err = host1x_unregister_client(host1x, &hdmi->client);
1279 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1284 clk_unprepare(hdmi->clk_parent);
1285 clk_unprepare(hdmi->clk);
1290 static struct of_device_id tegra_hdmi_of_match[] = {
1291 { .compatible = "nvidia,tegra30-hdmi", },
1292 { .compatible = "nvidia,tegra20-hdmi", },
1296 struct platform_driver tegra_hdmi_driver = {
1298 .name = "tegra-hdmi",
1299 .owner = THIS_MODULE,
1300 .of_match_table = tegra_hdmi_of_match,
1302 .probe = tegra_hdmi_probe,
1303 .remove = tegra_hdmi_remove,