drivers/gpu/ipu-v3/ipu-common.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/export.h>
  17 #include <linux/types.h>
  18 #include <linux/reset.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/err.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/clk.h>
  26 #include <linux/list.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqchip/chained_irq.h>
  29 #include <linux/irqdomain.h>
  30 #include <linux/of_device.h>
  31 #include <linux/of_graph.h>
  32
  33 #include <drm/drm_fourcc.h>
  34
  35 #include <video/imx-ipu-v3.h>
  36 #include "ipu-prv.h"
  37
  38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
  39 {
  40         return readl(ipu->cm_reg + offset);
  41 }
  42
  43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
  44 {
  45         writel(value, ipu->cm_reg + offset);
  46 }
  47
  48 int ipu_get_num(struct ipu_soc *ipu)
  49 {
  50         return ipu->id;
  51 }
  52 EXPORT_SYMBOL_GPL(ipu_get_num);
  53
  54 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync)
  55 {
  56         u32 val;
  57
  58         val = ipu_cm_read(ipu, IPU_SRM_PRI2);
  59         val &= ~DP_S_SRM_MODE_MASK;
  60         val |= sync ? DP_S_SRM_MODE_NEXT_FRAME :
  61                       DP_S_SRM_MODE_NOW;
  62         ipu_cm_write(ipu, val, IPU_SRM_PRI2);
  63 }
  64 EXPORT_SYMBOL_GPL(ipu_srm_dp_update);
  65
  66 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
  67 {
  68         switch (drm_fourcc) {
  69         case DRM_FORMAT_ARGB1555:
  70         case DRM_FORMAT_ABGR1555:
  71         case DRM_FORMAT_RGBA5551:
  72         case DRM_FORMAT_BGRA5551:
  73         case DRM_FORMAT_RGB565:
  74         case DRM_FORMAT_BGR565:
  75         case DRM_FORMAT_RGB888:
  76         case DRM_FORMAT_BGR888:
  77         case DRM_FORMAT_ARGB4444:
  78         case DRM_FORMAT_XRGB8888:
  79         case DRM_FORMAT_XBGR8888:
  80         case DRM_FORMAT_RGBX8888:
  81         case DRM_FORMAT_BGRX8888:
  82         case DRM_FORMAT_ARGB8888:
  83         case DRM_FORMAT_ABGR8888:
  84         case DRM_FORMAT_RGBA8888:
  85         case DRM_FORMAT_BGRA8888:
  86         case DRM_FORMAT_RGB565_A8:
  87         case DRM_FORMAT_BGR565_A8:
  88         case DRM_FORMAT_RGB888_A8:
  89         case DRM_FORMAT_BGR888_A8:
  90         case DRM_FORMAT_RGBX8888_A8:
  91         case DRM_FORMAT_BGRX8888_A8:
  92                 return IPUV3_COLORSPACE_RGB;
  93         case DRM_FORMAT_YUYV:
  94         case DRM_FORMAT_UYVY:
  95         case DRM_FORMAT_YUV420:
  96         case DRM_FORMAT_YVU420:
  97         case DRM_FORMAT_YUV422:
  98         case DRM_FORMAT_YVU422:
  99         case DRM_FORMAT_YUV444:
 100         case DRM_FORMAT_YVU444:
 101         case DRM_FORMAT_NV12:
 102         case DRM_FORMAT_NV21:
 103         case DRM_FORMAT_NV16:
 104         case DRM_FORMAT_NV61:
 105                 return IPUV3_COLORSPACE_YUV;
 106         default:
 107                 return IPUV3_COLORSPACE_UNKNOWN;
 108         }
 109 }
 110 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
 111
 112 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
 113 {
 114         switch (pixelformat) {
 115         case V4L2_PIX_FMT_YUV420:
 116         case V4L2_PIX_FMT_YVU420:
 117         case V4L2_PIX_FMT_YUV422P:
 118         case V4L2_PIX_FMT_UYVY:
 119         case V4L2_PIX_FMT_YUYV:
 120         case V4L2_PIX_FMT_NV12:
 121         case V4L2_PIX_FMT_NV21:
 122         case V4L2_PIX_FMT_NV16:
 123         case V4L2_PIX_FMT_NV61:
 124                 return IPUV3_COLORSPACE_YUV;
 125         case V4L2_PIX_FMT_RGB32:
 126         case V4L2_PIX_FMT_BGR32:
 127         case V4L2_PIX_FMT_RGB24:
 128         case V4L2_PIX_FMT_BGR24:
 129         case V4L2_PIX_FMT_RGB565:
 130                 return IPUV3_COLORSPACE_RGB;
 131         default:
 132                 return IPUV3_COLORSPACE_UNKNOWN;
 133         }
 134 }
 135 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
 136
 137 bool ipu_pixelformat_is_planar(u32 pixelformat)
 138 {
 139         switch (pixelformat) {
 140         case V4L2_PIX_FMT_YUV420:
 141         case V4L2_PIX_FMT_YVU420:
 142         case V4L2_PIX_FMT_YUV422P:
 143         case V4L2_PIX_FMT_NV12:
 144         case V4L2_PIX_FMT_NV21:
 145         case V4L2_PIX_FMT_NV16:
 146         case V4L2_PIX_FMT_NV61:
 147                 return true;
 148         }
 149
 150         return false;
 151 }
 152 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
 153
 154 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
 155 {
 156         switch (mbus_code & 0xf000) {
 157         case 0x1000:
 158                 return IPUV3_COLORSPACE_RGB;
 159         case 0x2000:
 160                 return IPUV3_COLORSPACE_YUV;
 161         default:
 162                 return IPUV3_COLORSPACE_UNKNOWN;
 163         }
 164 }
 165 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
 166
 167 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
 168 {
 169         switch (pixelformat) {
 170         case V4L2_PIX_FMT_YUV420:
 171         case V4L2_PIX_FMT_YVU420:
 172         case V4L2_PIX_FMT_YUV422P:
 173         case V4L2_PIX_FMT_NV12:
 174         case V4L2_PIX_FMT_NV21:
 175         case V4L2_PIX_FMT_NV16:
 176         case V4L2_PIX_FMT_NV61:
 177                 /*
 178                  * for the planar YUV formats, the stride passed to
 179                  * cpmem must be the stride in bytes of the Y plane.
 180                  * And all the planar YUV formats have an 8-bit
 181                  * Y component.
 182                  */
 183                 return (8 * pixel_stride) >> 3;
 184         case V4L2_PIX_FMT_RGB565:
 185         case V4L2_PIX_FMT_YUYV:
 186         case V4L2_PIX_FMT_UYVY:
 187                 return (16 * pixel_stride) >> 3;
 188         case V4L2_PIX_FMT_BGR24:
 189         case V4L2_PIX_FMT_RGB24:
 190                 return (24 * pixel_stride) >> 3;
 191         case V4L2_PIX_FMT_BGR32:
 192         case V4L2_PIX_FMT_RGB32:
 193                 return (32 * pixel_stride) >> 3;
 194         default:
 195                 break;
 196         }
 197
 198         return -EINVAL;
 199 }
 200 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
 201
 202 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 203                             bool hflip, bool vflip)
 204 {
 205         u32 r90, vf, hf;
 206
 207         switch (degrees) {
 208         case 0:
 209                 vf = hf = r90 = 0;
 210                 break;
 211         case 90:
 212                 vf = hf = 0;
 213                 r90 = 1;
 214                 break;
 215         case 180:
 216                 vf = hf = 1;
 217                 r90 = 0;
 218                 break;
 219         case 270:
 220                 vf = hf = r90 = 1;
 221                 break;
 222         default:
 223                 return -EINVAL;
 224         }
 225
 226         hf ^= (u32)hflip;
 227         vf ^= (u32)vflip;
 228
 229         *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
 230         return 0;
 231 }
 232 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
 233
 234 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
 235                             bool hflip, bool vflip)
 236 {
 237         u32 r90, vf, hf;
 238
 239         r90 = ((u32)mode >> 2) & 0x1;
 240         hf = ((u32)mode >> 1) & 0x1;
 241         vf = ((u32)mode >> 0) & 0x1;
 242         hf ^= (u32)hflip;
 243         vf ^= (u32)vflip;
 244
 245         switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
 246         case IPU_ROTATE_NONE:
 247                 *degrees = 0;
 248                 break;
 249         case IPU_ROTATE_90_RIGHT:
 250                 *degrees = 90;
 251                 break;
 252         case IPU_ROTATE_180:
 253                 *degrees = 180;
 254                 break;
 255         case IPU_ROTATE_90_LEFT:
 256                 *degrees = 270;
 257                 break;
 258         default:
 259                 return -EINVAL;
 260         }
 261
 262         return 0;
 263 }
 264 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
 265
 266 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
 267 {
 268         struct ipuv3_channel *channel;
 269
 270         dev_dbg(ipu->dev, "%s %d\n", __func__, num);
 271
 272         if (num > 63)
 273                 return ERR_PTR(-ENODEV);
 274
 275         mutex_lock(&ipu->channel_lock);
 276
 277         channel = &ipu->channel[num];
 278
 279         if (channel->busy) {
 280                 channel = ERR_PTR(-EBUSY);
 281                 goto out;
 282         }
 283
 284         channel->busy = true;
 285         channel->num = num;
 286
 287 out:
 288         mutex_unlock(&ipu->channel_lock);
 289
 290         return channel;
 291 }
 292 EXPORT_SYMBOL_GPL(ipu_idmac_get);
 293
 294 void ipu_idmac_put(struct ipuv3_channel *channel)
 295 {
 296         struct ipu_soc *ipu = channel->ipu;
 297
 298         dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
 299
 300         mutex_lock(&ipu->channel_lock);
 301
 302         channel->busy = false;
 303
 304         mutex_unlock(&ipu->channel_lock);
 305 }
 306 EXPORT_SYMBOL_GPL(ipu_idmac_put);
 307
 308 #define idma_mask(ch)                   (1 << ((ch) & 0x1f))
 309
 310 /*
 311  * This is an undocumented feature, a write one to a channel bit in
 312  * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
 313  * internal current buffer pointer so that transfers start from buffer
 314  * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
 315  * only says these are read-only registers). This operation is required
 316  * for channel linking to work correctly, for instance video capture
 317  * pipelines that carry out image rotations will fail after the first
 318  * streaming unless this function is called for each channel before
 319  * re-enabling the channels.
 320  */
 321 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
 322 {
 323         struct ipu_soc *ipu = channel->ipu;
 324         unsigned int chno = channel->num;
 325
 326         ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
 327 }
 328
 329 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
 330                 bool doublebuffer)
 331 {
 332         struct ipu_soc *ipu = channel->ipu;
 333         unsigned long flags;
 334         u32 reg;
 335
 336         spin_lock_irqsave(&ipu->lock, flags);
 337
 338         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 339         if (doublebuffer)
 340                 reg |= idma_mask(channel->num);
 341         else
 342                 reg &= ~idma_mask(channel->num);
 343         ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
 344
 345         __ipu_idmac_reset_current_buffer(channel);
 346
 347         spin_unlock_irqrestore(&ipu->lock, flags);
 348 }
 349 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
 350
 351 static const struct {
 352         int chnum;
 353         u32 reg;
 354         int shift;
 355 } idmac_lock_en_info[] = {
 356         { .chnum =  5, .reg = IDMAC_CH_LOCK_EN_1, .shift =  0, },
 357         { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift =  2, },
 358         { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift =  4, },
 359         { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift =  6, },
 360         { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift =  8, },
 361         { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
 362         { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
 363         { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
 364         { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
 365         { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
 366         { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
 367         { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift =  0, },
 368         { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift =  2, },
 369         { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift =  4, },
 370         { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift =  6, },
 371         { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift =  8, },
 372         { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
 373 };
 374
 375 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
 376 {
 377         struct ipu_soc *ipu = channel->ipu;
 378         unsigned long flags;
 379         u32 bursts, regval;
 380         int i;
 381
 382         switch (num_bursts) {
 383         case 0:
 384         case 1:
 385                 bursts = 0x00; /* locking disabled */
 386                 break;
 387         case 2:
 388                 bursts = 0x01;
 389                 break;
 390         case 4:
 391                 bursts = 0x02;
 392                 break;
 393         case 8:
 394                 bursts = 0x03;
 395                 break;
 396         default:
 397                 return -EINVAL;
 398         }
 399
 400         for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
 401                 if (channel->num == idmac_lock_en_info[i].chnum)
 402                         break;
 403         }
 404         if (i >= ARRAY_SIZE(idmac_lock_en_info))
 405                 return -EINVAL;
 406
 407         spin_lock_irqsave(&ipu->lock, flags);
 408
 409         regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
 410         regval &= ~(0x03 << idmac_lock_en_info[i].shift);
 411         regval |= (bursts << idmac_lock_en_info[i].shift);
 412         ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
 413
 414         spin_unlock_irqrestore(&ipu->lock, flags);
 415
 416         return 0;
 417 }
 418 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
 419
 420 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
 421 {
 422         unsigned long lock_flags;
 423         u32 val;
 424
 425         spin_lock_irqsave(&ipu->lock, lock_flags);
 426
 427         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 428
 429         if (mask & IPU_CONF_DI0_EN)
 430                 val |= IPU_DI0_COUNTER_RELEASE;
 431         if (mask & IPU_CONF_DI1_EN)
 432                 val |= IPU_DI1_COUNTER_RELEASE;
 433
 434         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 435
 436         val = ipu_cm_read(ipu, IPU_CONF);
 437         val |= mask;
 438         ipu_cm_write(ipu, val, IPU_CONF);
 439
 440         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 441
 442         return 0;
 443 }
 444 EXPORT_SYMBOL_GPL(ipu_module_enable);
 445
 446 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
 447 {
 448         unsigned long lock_flags;
 449         u32 val;
 450
 451         spin_lock_irqsave(&ipu->lock, lock_flags);
 452
 453         val = ipu_cm_read(ipu, IPU_CONF);
 454         val &= ~mask;
 455         ipu_cm_write(ipu, val, IPU_CONF);
 456
 457         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 458
 459         if (mask & IPU_CONF_DI0_EN)
 460                 val &= ~IPU_DI0_COUNTER_RELEASE;
 461         if (mask & IPU_CONF_DI1_EN)
 462                 val &= ~IPU_DI1_COUNTER_RELEASE;
 463
 464         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 465
 466         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 467
 468         return 0;
 469 }
 470 EXPORT_SYMBOL_GPL(ipu_module_disable);
 471
 472 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
 473 {
 474         struct ipu_soc *ipu = channel->ipu;
 475         unsigned int chno = channel->num;
 476
 477         return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
 478 }
 479 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
 480
 481 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
 482 {
 483         struct ipu_soc *ipu = channel->ipu;
 484         unsigned long flags;
 485         u32 reg = 0;
 486
 487         spin_lock_irqsave(&ipu->lock, flags);
 488         switch (buf_num) {
 489         case 0:
 490                 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
 491                 break;
 492         case 1:
 493                 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
 494                 break;
 495         case 2:
 496                 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
 497                 break;
 498         }
 499         spin_unlock_irqrestore(&ipu->lock, flags);
 500
 501         return ((reg & idma_mask(channel->num)) != 0);
 502 }
 503 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
 504
 505 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
 506 {
 507         struct ipu_soc *ipu = channel->ipu;
 508         unsigned int chno = channel->num;
 509         unsigned long flags;
 510
 511         spin_lock_irqsave(&ipu->lock, flags);
 512
 513         /* Mark buffer as ready. */
 514         if (buf_num == 0)
 515                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 516         else
 517                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 518
 519         spin_unlock_irqrestore(&ipu->lock, flags);
 520 }
 521 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
 522
 523 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
 524 {
 525         struct ipu_soc *ipu = channel->ipu;
 526         unsigned int chno = channel->num;
 527         unsigned long flags;
 528
 529         spin_lock_irqsave(&ipu->lock, flags);
 530
 531         ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
 532         switch (buf_num) {
 533         case 0:
 534                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 535                 break;
 536         case 1:
 537                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 538                 break;
 539         case 2:
 540                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
 541                 break;
 542         default:
 543                 break;
 544         }
 545         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 546
 547         spin_unlock_irqrestore(&ipu->lock, flags);
 548 }
 549 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
 550
 551 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
 552 {
 553         struct ipu_soc *ipu = channel->ipu;
 554         u32 val;
 555         unsigned long flags;
 556
 557         spin_lock_irqsave(&ipu->lock, flags);
 558
 559         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 560         val |= idma_mask(channel->num);
 561         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 562
 563         spin_unlock_irqrestore(&ipu->lock, flags);
 564
 565         return 0;
 566 }
 567 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
 568
 569 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
 570 {
 571         return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
 572 }
 573 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
 574
 575 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
 576 {
 577         struct ipu_soc *ipu = channel->ipu;
 578         unsigned long timeout;
 579
 580         timeout = jiffies + msecs_to_jiffies(ms);
 581         while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
 582                         idma_mask(channel->num)) {
 583                 if (time_after(jiffies, timeout))
 584                         return -ETIMEDOUT;
 585                 cpu_relax();
 586         }
 587
 588         return 0;
 589 }
 590 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
 591
 592 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
 593 {
 594         unsigned long timeout;
 595
 596         timeout = jiffies + msecs_to_jiffies(ms);
 597         ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
 598         while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
 599                 if (time_after(jiffies, timeout))
 600                         return -ETIMEDOUT;
 601                 cpu_relax();
 602         }
 603
 604         return 0;
 605 }
 606 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
 607
 608 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
 609 {
 610         struct ipu_soc *ipu = channel->ipu;
 611         u32 val;
 612         unsigned long flags;
 613
 614         spin_lock_irqsave(&ipu->lock, flags);
 615
 616         /* Disable DMA channel(s) */
 617         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 618         val &= ~idma_mask(channel->num);
 619         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 620
 621         __ipu_idmac_reset_current_buffer(channel);
 622
 623         /* Set channel buffers NOT to be ready */
 624         ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
 625
 626         if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
 627                         idma_mask(channel->num)) {
 628                 ipu_cm_write(ipu, idma_mask(channel->num),
 629                              IPU_CHA_BUF0_RDY(channel->num));
 630         }
 631
 632         if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
 633                         idma_mask(channel->num)) {
 634                 ipu_cm_write(ipu, idma_mask(channel->num),
 635                              IPU_CHA_BUF1_RDY(channel->num));
 636         }
 637
 638         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 639
 640         /* Reset the double buffer */
 641         val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 642         val &= ~idma_mask(channel->num);
 643         ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
 644
 645         spin_unlock_irqrestore(&ipu->lock, flags);
 646
 647         return 0;
 648 }
 649 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
 650
 651 /*
 652  * The imx6 rev. D TRM says that enabling the WM feature will increase
 653  * a channel's priority. Refer to Table 36-8 Calculated priority value.
 654  * The sub-module that is the sink or source for the channel must enable
 655  * watermark signal for this to take effect (SMFC_WM for instance).
 656  */
 657 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
 658 {
 659         struct ipu_soc *ipu = channel->ipu;
 660         unsigned long flags;
 661         u32 val;
 662
 663         spin_lock_irqsave(&ipu->lock, flags);
 664
 665         val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
 666         if (enable)
 667                 val |= 1 << (channel->num % 32);
 668         else
 669                 val &= ~(1 << (channel->num % 32));
 670         ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
 671
 672         spin_unlock_irqrestore(&ipu->lock, flags);
 673 }
 674 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
 675
 676 static int ipu_memory_reset(struct ipu_soc *ipu)
 677 {
 678         unsigned long timeout;
 679
 680         ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
 681
 682         timeout = jiffies + msecs_to_jiffies(1000);
 683         while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
 684                 if (time_after(jiffies, timeout))
 685                         return -ETIME;
 686                 cpu_relax();
 687         }
 688
 689         return 0;
 690 }
 691
 692 /*
 693  * Set the source mux for the given CSI. Selects either parallel or
 694  * MIPI CSI2 sources.
 695  */
 696 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
 697 {
 698         unsigned long flags;
 699         u32 val, mask;
 700
 701         mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
 702                 IPU_CONF_CSI0_DATA_SOURCE;
 703
 704         spin_lock_irqsave(&ipu->lock, flags);
 705
 706         val = ipu_cm_read(ipu, IPU_CONF);
 707         if (mipi_csi2)
 708                 val |= mask;
 709         else
 710                 val &= ~mask;
 711         ipu_cm_write(ipu, val, IPU_CONF);
 712
 713         spin_unlock_irqrestore(&ipu->lock, flags);
 714 }
 715 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
 716
 717 /*
 718  * Set the source mux for the IC. Selects either CSI[01] or the VDI.
 719  */
 720 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
 721 {
 722         unsigned long flags;
 723         u32 val;
 724
 725         spin_lock_irqsave(&ipu->lock, flags);
 726
 727         val = ipu_cm_read(ipu, IPU_CONF);
 728         if (vdi) {
 729                 val |= IPU_CONF_IC_INPUT;
 730         } else {
 731                 val &= ~IPU_CONF_IC_INPUT;
 732                 if (csi_id == 1)
 733                         val |= IPU_CONF_CSI_SEL;
 734                 else
 735                         val &= ~IPU_CONF_CSI_SEL;
 736         }
 737         ipu_cm_write(ipu, val, IPU_CONF);
 738
 739         spin_unlock_irqrestore(&ipu->lock, flags);
 740 }
 741 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
 742
 743
 744 /* Frame Synchronization Unit Channel Linking */
 745
 746 struct fsu_link_reg_info {
 747         int chno;
 748         u32 reg;
 749         u32 mask;
 750         u32 val;
 751 };
 752
 753 struct fsu_link_info {
 754         struct fsu_link_reg_info src;
 755         struct fsu_link_reg_info sink;
 756 };
 757
 758 static const struct fsu_link_info fsu_link_info[] = {
 759         {
 760                 .src  = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
 761                           FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
 762                 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
 763                           FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
 764         }, {
 765                 .src =  { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
 766                           FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
 767                 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
 768                           FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
 769         }, {
 770                 .src =  { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
 771                           FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
 772                 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
 773                           FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
 774         }, {
 775                 .src =  { IPUV3_CHANNEL_CSI_DIRECT, 0 },
 776                 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
 777                           FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
 778         },
 779 };
 780
 781 static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
 782 {
 783         int i;
 784
 785         for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
 786                 if (src == fsu_link_info[i].src.chno &&
 787                     sink == fsu_link_info[i].sink.chno)
 788                         return &fsu_link_info[i];
 789         }
 790
 791         return NULL;
 792 }
 793
 794 /*
 795  * Links a source channel to a sink channel in the FSU.
 796  */
 797 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
 798 {
 799         const struct fsu_link_info *link;
 800         u32 src_reg, sink_reg;
 801         unsigned long flags;
 802
 803         link = find_fsu_link_info(src_ch, sink_ch);
 804         if (!link)
 805                 return -EINVAL;
 806
 807         spin_lock_irqsave(&ipu->lock, flags);
 808
 809         if (link->src.mask) {
 810                 src_reg = ipu_cm_read(ipu, link->src.reg);
 811                 src_reg &= ~link->src.mask;
 812                 src_reg |= link->src.val;
 813                 ipu_cm_write(ipu, src_reg, link->src.reg);
 814         }
 815
 816         if (link->sink.mask) {
 817                 sink_reg = ipu_cm_read(ipu, link->sink.reg);
 818                 sink_reg &= ~link->sink.mask;
 819                 sink_reg |= link->sink.val;
 820                 ipu_cm_write(ipu, sink_reg, link->sink.reg);
 821         }
 822
 823         spin_unlock_irqrestore(&ipu->lock, flags);
 824         return 0;
 825 }
 826 EXPORT_SYMBOL_GPL(ipu_fsu_link);
 827
 828 /*
 829  * Unlinks source and sink channels in the FSU.
 830  */
 831 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
 832 {
 833         const struct fsu_link_info *link;
 834         u32 src_reg, sink_reg;
 835         unsigned long flags;
 836
 837         link = find_fsu_link_info(src_ch, sink_ch);
 838         if (!link)
 839                 return -EINVAL;
 840
 841         spin_lock_irqsave(&ipu->lock, flags);
 842
 843         if (link->src.mask) {
 844                 src_reg = ipu_cm_read(ipu, link->src.reg);
 845                 src_reg &= ~link->src.mask;
 846                 ipu_cm_write(ipu, src_reg, link->src.reg);
 847         }
 848
 849         if (link->sink.mask) {
 850                 sink_reg = ipu_cm_read(ipu, link->sink.reg);
 851                 sink_reg &= ~link->sink.mask;
 852                 ipu_cm_write(ipu, sink_reg, link->sink.reg);
 853         }
 854
 855         spin_unlock_irqrestore(&ipu->lock, flags);
 856         return 0;
 857 }
 858 EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
 859
 860 /* Link IDMAC channels in the FSU */
 861 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
 862 {
 863         return ipu_fsu_link(src->ipu, src->num, sink->num);
 864 }
 865 EXPORT_SYMBOL_GPL(ipu_idmac_link);
 866
 867 /* Unlink IDMAC channels in the FSU */
 868 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
 869 {
 870         return ipu_fsu_unlink(src->ipu, src->num, sink->num);
 871 }
 872 EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
 873
 874 struct ipu_devtype {
 875         const char *name;
 876         unsigned long cm_ofs;
 877         unsigned long cpmem_ofs;
 878         unsigned long srm_ofs;
 879         unsigned long tpm_ofs;
 880         unsigned long csi0_ofs;
 881         unsigned long csi1_ofs;
 882         unsigned long ic_ofs;
 883         unsigned long disp0_ofs;
 884         unsigned long disp1_ofs;
 885         unsigned long dc_tmpl_ofs;
 886         unsigned long vdi_ofs;
 887         enum ipuv3_type type;
 888 };
 889
 890 static struct ipu_devtype ipu_type_imx51 = {
 891         .name = "IPUv3EX",
 892         .cm_ofs = 0x1e000000,
 893         .cpmem_ofs = 0x1f000000,
 894         .srm_ofs = 0x1f040000,
 895         .tpm_ofs = 0x1f060000,
 896         .csi0_ofs = 0x1f030000,
 897         .csi1_ofs = 0x1f038000,
 898         .ic_ofs = 0x1e020000,
 899         .disp0_ofs = 0x1e040000,
 900         .disp1_ofs = 0x1e048000,
 901         .dc_tmpl_ofs = 0x1f080000,
 902         .vdi_ofs = 0x1e068000,
 903         .type = IPUV3EX,
 904 };
 905
 906 static struct ipu_devtype ipu_type_imx53 = {
 907         .name = "IPUv3M",
 908         .cm_ofs = 0x06000000,
 909         .cpmem_ofs = 0x07000000,
 910         .srm_ofs = 0x07040000,
 911         .tpm_ofs = 0x07060000,
 912         .csi0_ofs = 0x07030000,
 913         .csi1_ofs = 0x07038000,
 914         .ic_ofs = 0x06020000,
 915         .disp0_ofs = 0x06040000,
 916         .disp1_ofs = 0x06048000,
 917         .dc_tmpl_ofs = 0x07080000,
 918         .vdi_ofs = 0x06068000,
 919         .type = IPUV3M,
 920 };
 921
 922 static struct ipu_devtype ipu_type_imx6q = {
 923         .name = "IPUv3H",
 924         .cm_ofs = 0x00200000,
 925         .cpmem_ofs = 0x00300000,
 926         .srm_ofs = 0x00340000,
 927         .tpm_ofs = 0x00360000,
 928         .csi0_ofs = 0x00230000,
 929         .csi1_ofs = 0x00238000,
 930         .ic_ofs = 0x00220000,
 931         .disp0_ofs = 0x00240000,
 932         .disp1_ofs = 0x00248000,
 933         .dc_tmpl_ofs = 0x00380000,
 934         .vdi_ofs = 0x00268000,
 935         .type = IPUV3H,
 936 };
 937
 938 static const struct of_device_id imx_ipu_dt_ids[] = {
 939         { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
 940         { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
 941         { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
 942         { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, },
 943         { /* sentinel */ }
 944 };
 945 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
 946
 947 static int ipu_submodules_init(struct ipu_soc *ipu,
 948                 struct platform_device *pdev, unsigned long ipu_base,
 949                 struct clk *ipu_clk)
 950 {
 951         char *unit;
 952         int ret;
 953         struct device *dev = &pdev->dev;
 954         const struct ipu_devtype *devtype = ipu->devtype;
 955
 956         ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
 957         if (ret) {
 958                 unit = "cpmem";
 959                 goto err_cpmem;
 960         }
 961
 962         ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
 963                            IPU_CONF_CSI0_EN, ipu_clk);
 964         if (ret) {
 965                 unit = "csi0";
 966                 goto err_csi_0;
 967         }
 968
 969         ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
 970                            IPU_CONF_CSI1_EN, ipu_clk);
 971         if (ret) {
 972                 unit = "csi1";
 973                 goto err_csi_1;
 974         }
 975
 976         ret = ipu_ic_init(ipu, dev,
 977                           ipu_base + devtype->ic_ofs,
 978                           ipu_base + devtype->tpm_ofs);
 979         if (ret) {
 980                 unit = "ic";
 981                 goto err_ic;
 982         }
 983
 984         ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
 985                            IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
 986                            IPU_CONF_IC_INPUT);
 987         if (ret) {
 988                 unit = "vdi";
 989                 goto err_vdi;
 990         }
 991
 992         ret = ipu_image_convert_init(ipu, dev);
 993         if (ret) {
 994                 unit = "image_convert";
 995                 goto err_image_convert;
 996         }
 997
 998         ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
 999                           IPU_CONF_DI0_EN, ipu_clk);
1000         if (ret) {
1001                 unit = "di0";
1002                 goto err_di_0;
1003         }
1004
1005         ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
1006                         IPU_CONF_DI1_EN, ipu_clk);
1007         if (ret) {
1008                 unit = "di1";
1009                 goto err_di_1;
1010         }
1011
1012         ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
1013                         IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
1014         if (ret) {
1015                 unit = "dc_template";
1016                 goto err_dc;
1017         }
1018
1019         ret = ipu_dmfc_init(ipu, dev, ipu_base +
1020                         devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
1021         if (ret) {
1022                 unit = "dmfc";
1023                 goto err_dmfc;
1024         }
1025
1026         ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
1027         if (ret) {
1028                 unit = "dp";
1029                 goto err_dp;
1030         }
1031
1032         ret = ipu_smfc_init(ipu, dev, ipu_base +
1033                         devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
1034         if (ret) {
1035                 unit = "smfc";
1036                 goto err_smfc;
1037         }
1038
1039         return 0;
1040
1041 err_smfc:
1042         ipu_dp_exit(ipu);
1043 err_dp:
1044         ipu_dmfc_exit(ipu);
1045 err_dmfc:
1046         ipu_dc_exit(ipu);
1047 err_dc:
1048         ipu_di_exit(ipu, 1);
1049 err_di_1:
1050         ipu_di_exit(ipu, 0);
1051 err_di_0:
1052         ipu_image_convert_exit(ipu);
1053 err_image_convert:
1054         ipu_vdi_exit(ipu);
1055 err_vdi:
1056         ipu_ic_exit(ipu);
1057 err_ic:
1058         ipu_csi_exit(ipu, 1);
1059 err_csi_1:
1060         ipu_csi_exit(ipu, 0);
1061 err_csi_0:
1062         ipu_cpmem_exit(ipu);
1063 err_cpmem:
1064         dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
1065         return ret;
1066 }
1067
1068 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
1069 {
1070         unsigned long status;
1071         int i, bit, irq;
1072
1073         for (i = 0; i < num_regs; i++) {
1074
1075                 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
1076                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
1077
1078                 for_each_set_bit(bit, &status, 32) {
1079                         irq = irq_linear_revmap(ipu->domain,
1080                                                 regs[i] * 32 + bit);
1081                         if (irq)
1082                                 generic_handle_irq(irq);
1083                 }
1084         }
1085 }
1086
1087 static void ipu_irq_handler(struct irq_desc *desc)
1088 {
1089         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1090         struct irq_chip *chip = irq_desc_get_chip(desc);
1091         const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
1092
1093         chained_irq_enter(chip, desc);
1094
1095         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1096
1097         chained_irq_exit(chip, desc);
1098 }
1099
1100 static void ipu_err_irq_handler(struct irq_desc *desc)
1101 {
1102         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1103         struct irq_chip *chip = irq_desc_get_chip(desc);
1104         const int int_reg[] = { 4, 5, 8, 9};
1105
1106         chained_irq_enter(chip, desc);
1107
1108         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1109
1110         chained_irq_exit(chip, desc);
1111 }
1112
1113 int ipu_map_irq(struct ipu_soc *ipu, int irq)
1114 {
1115         int virq;
1116
1117         virq = irq_linear_revmap(ipu->domain, irq);
1118         if (!virq)
1119                 virq = irq_create_mapping(ipu->domain, irq);
1120
1121         return virq;
1122 }
1123 EXPORT_SYMBOL_GPL(ipu_map_irq);
1124
1125 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
1126                 enum ipu_channel_irq irq_type)
1127 {
1128         return ipu_map_irq(ipu, irq_type + channel->num);
1129 }
1130 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
1131
1132 static void ipu_submodules_exit(struct ipu_soc *ipu)
1133 {
1134         ipu_smfc_exit(ipu);
1135         ipu_dp_exit(ipu);
1136         ipu_dmfc_exit(ipu);
1137         ipu_dc_exit(ipu);
1138         ipu_di_exit(ipu, 1);
1139         ipu_di_exit(ipu, 0);
1140         ipu_image_convert_exit(ipu);
1141         ipu_vdi_exit(ipu);
1142         ipu_ic_exit(ipu);
1143         ipu_csi_exit(ipu, 1);
1144         ipu_csi_exit(ipu, 0);
1145         ipu_cpmem_exit(ipu);
1146 }
1147
1148 static int platform_remove_devices_fn(struct device *dev, void *unused)
1149 {
1150         struct platform_device *pdev = to_platform_device(dev);
1151
1152         platform_device_unregister(pdev);
1153
1154         return 0;
1155 }
1156
1157 static void platform_device_unregister_children(struct platform_device *pdev)
1158 {
1159         device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
1160 }
1161
1162 struct ipu_platform_reg {
1163         struct ipu_client_platformdata pdata;
1164         const char *name;
1165 };
1166
1167 /* These must be in the order of the corresponding device tree port nodes */
1168 static struct ipu_platform_reg client_reg[] = {
1169         {
1170                 .pdata = {
1171                         .csi = 0,
1172                         .dma[0] = IPUV3_CHANNEL_CSI0,
1173                         .dma[1] = -EINVAL,
1174                 },
1175                 .name = "imx-ipuv3-csi",
1176         }, {
1177                 .pdata = {
1178                         .csi = 1,
1179                         .dma[0] = IPUV3_CHANNEL_CSI1,
1180                         .dma[1] = -EINVAL,
1181                 },
1182                 .name = "imx-ipuv3-csi",
1183         }, {
1184                 .pdata = {
1185                         .di = 0,
1186                         .dc = 5,
1187                         .dp = IPU_DP_FLOW_SYNC_BG,
1188                         .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1189                         .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1190                 },
1191                 .name = "imx-ipuv3-crtc",
1192         }, {
1193                 .pdata = {
1194                         .di = 1,
1195                         .dc = 1,
1196                         .dp = -EINVAL,
1197                         .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1198                         .dma[1] = -EINVAL,
1199                 },
1200                 .name = "imx-ipuv3-crtc",
1201         },
1202 };
1203
1204 static DEFINE_MUTEX(ipu_client_id_mutex);
1205 static int ipu_client_id;
1206
1207 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1208 {
1209         struct device *dev = ipu->dev;
1210         unsigned i;
1211         int id, ret;
1212
1213         mutex_lock(&ipu_client_id_mutex);
1214         id = ipu_client_id;
1215         ipu_client_id += ARRAY_SIZE(client_reg);
1216         mutex_unlock(&ipu_client_id_mutex);
1217
1218         for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1219                 struct ipu_platform_reg *reg = &client_reg[i];
1220                 struct platform_device *pdev;
1221                 struct device_node *of_node;
1222
1223                 /* Associate subdevice with the corresponding port node */
1224                 of_node = of_graph_get_port_by_id(dev->of_node, i);
1225                 if (!of_node) {
1226                         dev_info(dev,
1227                                  "no port@%d node in %s, not using %s%d\n",
1228                                  i, dev->of_node->full_name,
1229                                  (i / 2) ? "DI" : "CSI", i % 2);
1230                         continue;
1231                 }
1232
1233                 pdev = platform_device_alloc(reg->name, id++);
1234                 if (!pdev) {
1235                         ret = -ENOMEM;
1236                         goto err_register;
1237                 }
1238
1239                 pdev->dev.parent = dev;
1240
1241                 reg->pdata.of_node = of_node;
1242                 ret = platform_device_add_data(pdev, &reg->pdata,
1243                                                sizeof(reg->pdata));
1244                 if (!ret)
1245                         ret = platform_device_add(pdev);
1246                 if (ret) {
1247                         platform_device_put(pdev);
1248                         goto err_register;
1249                 }
1250         }
1251
1252         return 0;
1253
1254 err_register:
1255         platform_device_unregister_children(to_platform_device(dev));
1256
1257         return ret;
1258 }
1259
1260
1261 static int ipu_irq_init(struct ipu_soc *ipu)
1262 {
1263         struct irq_chip_generic *gc;
1264         struct irq_chip_type *ct;
1265         unsigned long unused[IPU_NUM_IRQS / 32] = {
1266                 0x400100d0, 0xffe000fd,
1267                 0x400100d0, 0xffe000fd,
1268                 0x400100d0, 0xffe000fd,
1269                 0x4077ffff, 0xffe7e1fd,
1270                 0x23fffffe, 0x8880fff0,
1271                 0xf98fe7d0, 0xfff81fff,
1272                 0x400100d0, 0xffe000fd,
1273                 0x00000000,
1274         };
1275         int ret, i;
1276
1277         ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1278                                             &irq_generic_chip_ops, ipu);
1279         if (!ipu->domain) {
1280                 dev_err(ipu->dev, "failed to add irq domain\n");
1281                 return -ENODEV;
1282         }
1283
1284         ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1285                                              handle_level_irq, 0, 0, 0);
1286         if (ret < 0) {
1287                 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1288                 irq_domain_remove(ipu->domain);
1289                 return ret;
1290         }
1291
1292         /* Mask and clear all interrupts */
1293         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1294                 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1295                 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32));
1296         }
1297
1298         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1299                 gc = irq_get_domain_generic_chip(ipu->domain, i);
1300                 gc->reg_base = ipu->cm_reg;
1301                 gc->unused = unused[i / 32];
1302                 ct = gc->chip_types;
1303                 ct->chip.irq_ack = irq_gc_ack_set_bit;
1304                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1305                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1306                 ct->regs.ack = IPU_INT_STAT(i / 32);
1307                 ct->regs.mask = IPU_INT_CTRL(i / 32);
1308         }
1309
1310         irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1311         irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1312                                          ipu);
1313
1314         return 0;
1315 }
1316
1317 static void ipu_irq_exit(struct ipu_soc *ipu)
1318 {
1319         int i, irq;
1320
1321         irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1322         irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1323
1324         /* TODO: remove irq_domain_generic_chips */
1325
1326         for (i = 0; i < IPU_NUM_IRQS; i++) {
1327                 irq = irq_linear_revmap(ipu->domain, i);
1328                 if (irq)
1329                         irq_dispose_mapping(irq);
1330         }
1331
1332         irq_domain_remove(ipu->domain);
1333 }
1334
1335 void ipu_dump(struct ipu_soc *ipu)
1336 {
1337         int i;
1338
1339         dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1340                 ipu_cm_read(ipu, IPU_CONF));
1341         dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1342                 ipu_idmac_read(ipu, IDMAC_CONF));
1343         dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1344                 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1345         dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1346                 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1347         dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1348                 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1349         dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1350                 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1351         dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1352                 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1353         dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1354                 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1355         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1356                 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1357         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1358                 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1359         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1360                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1361         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1362                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1363         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1364                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1365         dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1366                 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1367         for (i = 0; i < 15; i++)
1368                 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1369                         ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1370 }
1371 EXPORT_SYMBOL_GPL(ipu_dump);
1372
1373 static int ipu_probe(struct platform_device *pdev)
1374 {
1375         struct device_node *np = pdev->dev.of_node;
1376         struct ipu_soc *ipu;
1377         struct resource *res;
1378         unsigned long ipu_base;
1379         int i, ret, irq_sync, irq_err;
1380         const struct ipu_devtype *devtype;
1381
1382         devtype = of_device_get_match_data(&pdev->dev);
1383         if (!devtype)
1384                 return -EINVAL;
1385
1386         irq_sync = platform_get_irq(pdev, 0);
1387         irq_err = platform_get_irq(pdev, 1);
1388         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1389
1390         dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1391                         irq_sync, irq_err);
1392
1393         if (!res || irq_sync < 0 || irq_err < 0)
1394                 return -ENODEV;
1395
1396         ipu_base = res->start;
1397
1398         ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1399         if (!ipu)
1400                 return -ENODEV;
1401
1402         ipu->id = of_alias_get_id(np, "ipu");
1403
1404         if (of_device_is_compatible(np, "fsl,imx6qp-ipu") &&
1405             IS_ENABLED(CONFIG_DRM)) {
1406                 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev,
1407                                                           "fsl,prg", ipu->id);
1408                 if (!ipu->prg_priv)
1409                         return -EPROBE_DEFER;
1410         }
1411
1412         for (i = 0; i < 64; i++)
1413                 ipu->channel[i].ipu = ipu;
1414         ipu->devtype = devtype;
1415         ipu->ipu_type = devtype->type;
1416
1417         spin_lock_init(&ipu->lock);
1418         mutex_init(&ipu->channel_lock);
1419
1420         dev_dbg(&pdev->dev, "cm_reg:   0x%08lx\n",
1421                         ipu_base + devtype->cm_ofs);
1422         dev_dbg(&pdev->dev, "idmac:    0x%08lx\n",
1423                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1424         dev_dbg(&pdev->dev, "cpmem:    0x%08lx\n",
1425                         ipu_base + devtype->cpmem_ofs);
1426         dev_dbg(&pdev->dev, "csi0:    0x%08lx\n",
1427                         ipu_base + devtype->csi0_ofs);
1428         dev_dbg(&pdev->dev, "csi1:    0x%08lx\n",
1429                         ipu_base + devtype->csi1_ofs);
1430         dev_dbg(&pdev->dev, "ic:      0x%08lx\n",
1431                         ipu_base + devtype->ic_ofs);
1432         dev_dbg(&pdev->dev, "disp0:    0x%08lx\n",
1433                         ipu_base + devtype->disp0_ofs);
1434         dev_dbg(&pdev->dev, "disp1:    0x%08lx\n",
1435                         ipu_base + devtype->disp1_ofs);
1436         dev_dbg(&pdev->dev, "srm:      0x%08lx\n",
1437                         ipu_base + devtype->srm_ofs);
1438         dev_dbg(&pdev->dev, "tpm:      0x%08lx\n",
1439                         ipu_base + devtype->tpm_ofs);
1440         dev_dbg(&pdev->dev, "dc:       0x%08lx\n",
1441                         ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1442         dev_dbg(&pdev->dev, "ic:       0x%08lx\n",
1443                         ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1444         dev_dbg(&pdev->dev, "dmfc:     0x%08lx\n",
1445                         ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1446         dev_dbg(&pdev->dev, "vdi:      0x%08lx\n",
1447                         ipu_base + devtype->vdi_ofs);
1448
1449         ipu->cm_reg = devm_ioremap(&pdev->dev,
1450                         ipu_base + devtype->cm_ofs, PAGE_SIZE);
1451         ipu->idmac_reg = devm_ioremap(&pdev->dev,
1452                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1453                         PAGE_SIZE);
1454
1455         if (!ipu->cm_reg || !ipu->idmac_reg)
1456                 return -ENOMEM;
1457
1458         ipu->clk = devm_clk_get(&pdev->dev, "bus");
1459         if (IS_ERR(ipu->clk)) {
1460                 ret = PTR_ERR(ipu->clk);
1461                 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1462                 return ret;
1463         }
1464
1465         platform_set_drvdata(pdev, ipu);
1466
1467         ret = clk_prepare_enable(ipu->clk);
1468         if (ret) {
1469                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1470                 return ret;
1471         }
1472
1473         ipu->dev = &pdev->dev;
1474         ipu->irq_sync = irq_sync;
1475         ipu->irq_err = irq_err;
1476
1477         ret = device_reset(&pdev->dev);
1478         if (ret) {
1479                 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1480                 goto out_failed_reset;
1481         }
1482         ret = ipu_memory_reset(ipu);
1483         if (ret)
1484                 goto out_failed_reset;
1485
1486         ret = ipu_irq_init(ipu);
1487         if (ret)
1488                 goto out_failed_irq;
1489
1490         /* Set MCU_T to divide MCU access window into 2 */
1491         ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1492                         IPU_DISP_GEN);
1493
1494         ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1495         if (ret)
1496                 goto failed_submodules_init;
1497
1498         ret = ipu_add_client_devices(ipu, ipu_base);
1499         if (ret) {
1500                 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1501                                 ret);
1502                 goto failed_add_clients;
1503         }
1504
1505         dev_info(&pdev->dev, "%s probed\n", devtype->name);
1506
1507         return 0;
1508
1509 failed_add_clients:
1510         ipu_submodules_exit(ipu);
1511 failed_submodules_init:
1512         ipu_irq_exit(ipu);
1513 out_failed_irq:
1514 out_failed_reset:
1515         clk_disable_unprepare(ipu->clk);
1516         return ret;
1517 }
1518
1519 static int ipu_remove(struct platform_device *pdev)
1520 {
1521         struct ipu_soc *ipu = platform_get_drvdata(pdev);
1522
1523         platform_device_unregister_children(pdev);
1524         ipu_submodules_exit(ipu);
1525         ipu_irq_exit(ipu);
1526
1527         clk_disable_unprepare(ipu->clk);
1528
1529         return 0;
1530 }
1531
1532 static struct platform_driver imx_ipu_driver = {
1533         .driver = {
1534                 .name = "imx-ipuv3",
1535                 .of_match_table = imx_ipu_dt_ids,
1536         },
1537         .probe = ipu_probe,
1538         .remove = ipu_remove,
1539 };
1540
1541 static struct platform_driver * const drivers[] = {
1542 #if IS_ENABLED(CONFIG_DRM)
1543         &ipu_pre_drv,
1544         &ipu_prg_drv,
1545 #endif
1546         &imx_ipu_driver,
1547 };
1548
1549 static int __init imx_ipu_init(void)
1550 {
1551         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1552 }
1553 module_init(imx_ipu_init);
1554
1555 static void __exit imx_ipu_exit(void)
1556 {
1557         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1558 }
1559 module_exit(imx_ipu_exit);
1560
1561 MODULE_ALIAS("platform:imx-ipuv3");
1562 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1563 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1564 MODULE_LICENSE("GPL");