2 * Copyright (c) 2017 Lucas Stach, Pengutronix
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 #include <drm/drm_fourcc.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/genalloc.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <video/imx-ipu-v3.h>
25 #define IPU_PRE_MAX_WIDTH 2048
26 #define IPU_PRE_NUM_SCANLINES 8
28 #define IPU_PRE_CTRL 0x000
29 #define IPU_PRE_CTRL_SET 0x004
30 #define IPU_PRE_CTRL_ENABLE (1 << 0)
31 #define IPU_PRE_CTRL_BLOCK_EN (1 << 1)
32 #define IPU_PRE_CTRL_BLOCK_16 (1 << 2)
33 #define IPU_PRE_CTRL_SDW_UPDATE (1 << 4)
34 #define IPU_PRE_CTRL_VFLIP (1 << 5)
35 #define IPU_PRE_CTRL_SO (1 << 6)
36 #define IPU_PRE_CTRL_INTERLACED_FIELD (1 << 7)
37 #define IPU_PRE_CTRL_HANDSHAKE_EN (1 << 8)
38 #define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9)
39 #define IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN (1 << 11)
40 #define IPU_PRE_CTRL_EN_REPEAT (1 << 28)
41 #define IPU_PRE_CTRL_TPR_REST_SEL (1 << 29)
42 #define IPU_PRE_CTRL_CLKGATE (1 << 30)
43 #define IPU_PRE_CTRL_SFTRST (1 << 31)
45 #define IPU_PRE_CUR_BUF 0x030
47 #define IPU_PRE_NEXT_BUF 0x040
49 #define IPU_PRE_TPR_CTRL 0x070
50 #define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0)
51 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK 0xff
53 #define IPU_PRE_PREFETCH_ENG_CTRL 0x080
54 #define IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN (1 << 0)
55 #define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1)
56 #define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
57 #define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8)
58 #define IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS (1 << 11)
59 #define IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE (1 << 12)
60 #define IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP (1 << 14)
61 #define IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN (1 << 15)
63 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE 0x0a0
64 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0)
65 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16)
67 #define IPU_PRE_PREFETCH_ENG_PITCH 0x0d0
68 #define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0)
69 #define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16)
71 #define IPU_PRE_STORE_ENG_CTRL 0x110
72 #define IPU_PRE_STORE_ENG_CTRL_STORE_EN (1 << 0)
73 #define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1)
74 #define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
76 #define IPU_PRE_STORE_ENG_SIZE 0x130
77 #define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0)
78 #define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16)
80 #define IPU_PRE_STORE_ENG_PITCH 0x140
81 #define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0)
83 #define IPU_PRE_STORE_ENG_ADDR 0x150
86 struct list_head list;
91 struct gen_pool *iram;
93 dma_addr_t buffer_paddr;
98 static DEFINE_MUTEX(ipu_pre_list_mutex);
99 static LIST_HEAD(ipu_pre_list);
100 static int available_pres;
102 int ipu_pre_get_available_count(void)
104 return available_pres;
108 ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index)
110 struct device_node *pre_node = of_parse_phandle(dev->of_node,
114 mutex_lock(&ipu_pre_list_mutex);
115 list_for_each_entry(pre, &ipu_pre_list, list) {
116 if (pre_node == pre->dev->of_node) {
117 mutex_unlock(&ipu_pre_list_mutex);
118 device_link_add(dev, pre->dev, DL_FLAG_AUTOREMOVE);
122 mutex_unlock(&ipu_pre_list_mutex);
127 int ipu_pre_get(struct ipu_pre *pre)
134 clk_prepare_enable(pre->clk_axi);
136 /* first get the engine out of reset and remove clock gating */
137 writel(0, pre->regs + IPU_PRE_CTRL);
139 /* init defaults that should be applied to all streams */
140 val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN |
141 IPU_PRE_CTRL_HANDSHAKE_EN |
142 IPU_PRE_CTRL_TPR_REST_SEL |
143 IPU_PRE_CTRL_BLOCK_16 | IPU_PRE_CTRL_SDW_UPDATE;
144 writel(val, pre->regs + IPU_PRE_CTRL);
150 void ipu_pre_put(struct ipu_pre *pre)
154 val = IPU_PRE_CTRL_SFTRST | IPU_PRE_CTRL_CLKGATE;
155 writel(val, pre->regs + IPU_PRE_CTRL);
157 clk_disable_unprepare(pre->clk_axi);
162 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
163 unsigned int height, unsigned int stride, u32 format,
164 unsigned int bufaddr)
166 const struct drm_format_info *info = drm_format_info(format);
167 u32 active_bpp = info->cpp[0] >> 1;
170 writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
171 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
173 val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
174 IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
175 IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) |
176 IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS |
177 IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN;
178 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
180 val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) |
181 IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height);
182 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
184 val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride);
185 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
187 val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) |
188 IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) |
189 IPU_PRE_STORE_ENG_CTRL_STORE_EN;
190 writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
192 val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) |
193 IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height);
194 writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
196 val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride);
197 writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
199 writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
201 val = readl(pre->regs + IPU_PRE_CTRL);
202 val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE |
203 IPU_PRE_CTRL_SDW_UPDATE;
204 writel(val, pre->regs + IPU_PRE_CTRL);
207 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
209 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
210 writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
213 u32 ipu_pre_get_baddr(struct ipu_pre *pre)
215 return (u32)pre->buffer_paddr;
218 static int ipu_pre_probe(struct platform_device *pdev)
220 struct device *dev = &pdev->dev;
221 struct resource *res;
224 pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
228 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
229 pre->regs = devm_ioremap_resource(&pdev->dev, res);
230 if (IS_ERR(pre->regs))
231 return PTR_ERR(pre->regs);
233 pre->clk_axi = devm_clk_get(dev, "axi");
234 if (IS_ERR(pre->clk_axi))
235 return PTR_ERR(pre->clk_axi);
237 pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
239 return -EPROBE_DEFER;
242 * Allocate IRAM buffer with maximum size. This could be made dynamic,
243 * but as there is no other user of this IRAM region and we can fit all
244 * max sized buffers into it, there is no need yet.
246 pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
247 IPU_PRE_NUM_SCANLINES * 4,
249 if (!pre->buffer_virt)
253 platform_set_drvdata(pdev, pre);
254 mutex_lock(&ipu_pre_list_mutex);
255 list_add(&pre->list, &ipu_pre_list);
257 mutex_unlock(&ipu_pre_list_mutex);
262 static int ipu_pre_remove(struct platform_device *pdev)
264 struct ipu_pre *pre = platform_get_drvdata(pdev);
266 mutex_lock(&ipu_pre_list_mutex);
267 list_del(&pre->list);
269 mutex_unlock(&ipu_pre_list_mutex);
271 if (pre->buffer_virt)
272 gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
273 IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);
277 static const struct of_device_id ipu_pre_dt_ids[] = {
278 { .compatible = "fsl,imx6qp-pre", },
282 struct platform_driver ipu_pre_drv = {
283 .probe = ipu_pre_probe,
284 .remove = ipu_pre_remove,
286 .name = "imx-ipu-pre",
287 .of_match_table = ipu_pre_dt_ids,