1 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
3 * Description: CoreSight Trace Memory Controller driver
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/device.h>
20 #include <linux/err.h>
22 #include <linux/miscdevice.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/spinlock.h>
27 #include <linux/pm_runtime.h>
29 #include <linux/coresight.h>
30 #include <linux/amba/bus.h>
32 #include "coresight-priv.h"
33 #include "coresight-tmc.h"
35 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
37 /* Ensure formatter, unformatter and hardware fifo are empty */
38 if (coresight_timeout(drvdata->base,
39 TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
41 "timeout observed when probing at offset %#x\n",
46 void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
50 ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
51 ffcr |= TMC_FFCR_STOP_ON_FLUSH;
52 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
53 ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
54 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
55 /* Ensure flush completes */
56 if (coresight_timeout(drvdata->base,
57 TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
59 "timeout observed when probing at offset %#x\n",
63 tmc_wait_for_tmcready(drvdata);
66 void tmc_enable_hw(struct tmc_drvdata *drvdata)
68 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
71 void tmc_disable_hw(struct tmc_drvdata *drvdata)
73 writel_relaxed(0x0, drvdata->base + TMC_CTL);
76 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
80 switch (drvdata->config_type) {
81 case TMC_CONFIG_TYPE_ETB:
82 case TMC_CONFIG_TYPE_ETF:
83 ret = tmc_read_prepare_etb(drvdata);
85 case TMC_CONFIG_TYPE_ETR:
86 ret = tmc_read_prepare_etr(drvdata);
93 dev_info(drvdata->dev, "TMC read start\n");
98 static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
102 switch (drvdata->config_type) {
103 case TMC_CONFIG_TYPE_ETB:
104 case TMC_CONFIG_TYPE_ETF:
105 ret = tmc_read_unprepare_etb(drvdata);
107 case TMC_CONFIG_TYPE_ETR:
108 ret = tmc_read_unprepare_etr(drvdata);
115 dev_info(drvdata->dev, "TMC read end\n");
120 static int tmc_open(struct inode *inode, struct file *file)
123 struct tmc_drvdata *drvdata = container_of(file->private_data,
124 struct tmc_drvdata, miscdev);
126 ret = tmc_read_prepare(drvdata);
130 nonseekable_open(inode, file);
132 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
136 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
139 struct tmc_drvdata *drvdata = container_of(file->private_data,
140 struct tmc_drvdata, miscdev);
141 char *bufp = drvdata->buf + *ppos;
143 if (*ppos + len > drvdata->size)
144 len = drvdata->size - *ppos;
146 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
147 if (bufp == (char *)(drvdata->vaddr + drvdata->size))
148 bufp = drvdata->vaddr;
149 else if (bufp > (char *)(drvdata->vaddr + drvdata->size))
150 bufp -= drvdata->size;
151 if ((bufp + len) > (char *)(drvdata->vaddr + drvdata->size))
152 len = (char *)(drvdata->vaddr + drvdata->size) - bufp;
155 if (copy_to_user(data, bufp, len)) {
156 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
162 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
163 __func__, len, (int)(drvdata->size - *ppos));
167 static int tmc_release(struct inode *inode, struct file *file)
170 struct tmc_drvdata *drvdata = container_of(file->private_data,
171 struct tmc_drvdata, miscdev);
173 ret = tmc_read_unprepare(drvdata);
177 dev_dbg(drvdata->dev, "%s: released\n", __func__);
181 static const struct file_operations tmc_fops = {
182 .owner = THIS_MODULE,
185 .release = tmc_release,
189 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
191 enum tmc_mem_intf_width memwidth;
194 * Excerpt from the TRM:
196 * DEVID::MEMWIDTH[10:8]
197 * 0x2 Memory interface databus is 32 bits wide.
198 * 0x3 Memory interface databus is 64 bits wide.
199 * 0x4 Memory interface databus is 128 bits wide.
200 * 0x5 Memory interface databus is 256 bits wide.
202 switch (BMVAL(devid, 8, 10)) {
204 memwidth = TMC_MEM_INTF_WIDTH_32BITS;
207 memwidth = TMC_MEM_INTF_WIDTH_64BITS;
210 memwidth = TMC_MEM_INTF_WIDTH_128BITS;
213 memwidth = TMC_MEM_INTF_WIDTH_256BITS;
222 #define coresight_tmc_simple_func(name, offset) \
223 coresight_simple_func(struct tmc_drvdata, name, offset)
225 coresight_tmc_simple_func(rsz, TMC_RSZ);
226 coresight_tmc_simple_func(sts, TMC_STS);
227 coresight_tmc_simple_func(rrp, TMC_RRP);
228 coresight_tmc_simple_func(rwp, TMC_RWP);
229 coresight_tmc_simple_func(trg, TMC_TRG);
230 coresight_tmc_simple_func(ctl, TMC_CTL);
231 coresight_tmc_simple_func(ffsr, TMC_FFSR);
232 coresight_tmc_simple_func(ffcr, TMC_FFCR);
233 coresight_tmc_simple_func(mode, TMC_MODE);
234 coresight_tmc_simple_func(pscr, TMC_PSCR);
235 coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
237 static struct attribute *coresight_tmc_mgmt_attrs[] = {
248 &dev_attr_devid.attr,
252 ssize_t trigger_cntr_show(struct device *dev,
253 struct device_attribute *attr, char *buf)
255 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
256 unsigned long val = drvdata->trigger_cntr;
258 return sprintf(buf, "%#lx\n", val);
261 static ssize_t trigger_cntr_store(struct device *dev,
262 struct device_attribute *attr,
263 const char *buf, size_t size)
267 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
269 ret = kstrtoul(buf, 16, &val);
273 drvdata->trigger_cntr = val;
276 static DEVICE_ATTR_RW(trigger_cntr);
278 static struct attribute *coresight_tmc_attrs[] = {
279 &dev_attr_trigger_cntr.attr,
283 static const struct attribute_group coresight_tmc_group = {
284 .attrs = coresight_tmc_attrs,
287 static const struct attribute_group coresight_tmc_mgmt_group = {
288 .attrs = coresight_tmc_mgmt_attrs,
292 const struct attribute_group *coresight_tmc_groups[] = {
293 &coresight_tmc_group,
294 &coresight_tmc_mgmt_group,
298 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
303 struct device *dev = &adev->dev;
304 struct coresight_platform_data *pdata = NULL;
305 struct tmc_drvdata *drvdata;
306 struct resource *res = &adev->res;
307 struct coresight_desc *desc;
308 struct device_node *np = adev->dev.of_node;
311 pdata = of_get_coresight_platform_data(dev, np);
313 return PTR_ERR(pdata);
314 adev->dev.platform_data = pdata;
317 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
321 drvdata->dev = &adev->dev;
322 dev_set_drvdata(dev, drvdata);
324 /* Validity for the resource is already checked by the AMBA core */
325 base = devm_ioremap_resource(dev, res);
327 return PTR_ERR(base);
329 drvdata->base = base;
331 spin_lock_init(&drvdata->spinlock);
333 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
334 drvdata->config_type = BMVAL(devid, 6, 7);
335 drvdata->memwidth = tmc_get_memwidth(devid);
337 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
339 ret = of_property_read_u32(np,
343 drvdata->size = SZ_1M;
345 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
348 pm_runtime_put(&adev->dev);
350 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
353 goto err_devm_kzalloc;
358 desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
359 desc->groups = coresight_tmc_groups;
361 if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
362 desc->type = CORESIGHT_DEV_TYPE_SINK;
363 desc->ops = &tmc_etb_cs_ops;
364 } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
365 desc->type = CORESIGHT_DEV_TYPE_SINK;
366 desc->ops = &tmc_etr_cs_ops;
368 desc->type = CORESIGHT_DEV_TYPE_LINKSINK;
369 desc->subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
370 desc->ops = &tmc_etf_cs_ops;
373 drvdata->csdev = coresight_register(desc);
374 if (IS_ERR(drvdata->csdev)) {
375 ret = PTR_ERR(drvdata->csdev);
376 goto err_devm_kzalloc;
379 drvdata->miscdev.name = pdata->name;
380 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
381 drvdata->miscdev.fops = &tmc_fops;
382 ret = misc_register(&drvdata->miscdev);
384 goto err_misc_register;
389 coresight_unregister(drvdata->csdev);
391 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
392 dma_free_coherent(dev, drvdata->size,
393 drvdata->vaddr, drvdata->paddr);
397 static struct amba_id tmc_ids[] = {
405 static struct amba_driver tmc_driver = {
407 .name = "coresight-tmc",
408 .owner = THIS_MODULE,
409 .suppress_bind_attrs = true,
414 builtin_amba_driver(tmc_driver);