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[karo-tx-linux.git] / drivers / i2c / busses / i2c-at91.c
1 /*
2  *  i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
3  *
4  *  Copyright (C) 2011 Weinmann Medical GmbH
5  *  Author: Nikolaus Voss <n.voss@weinmann.de>
6  *
7  *  Evolved from original work by:
8  *  Copyright (C) 2004 Rick Bronson
9  *  Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
10  *
11  *  Borrowed heavily from original work by:
12  *  Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
13  *
14  *  This program is free software; you can redistribute it and/or modify
15  *  it under the terms of the GNU General Public License as published by
16  *  the Free Software Foundation; either version 2 of the License, or
17  *  (at your option) any later version.
18  */
19
20 #include <linux/clk.h>
21 #include <linux/completion.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/err.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
33 #include <linux/platform_data/dma-atmel.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/pinctrl/consumer.h>
36
37 #define DEFAULT_TWI_CLK_HZ              100000          /* max 400 Kbits/s */
38 #define AT91_I2C_TIMEOUT        msecs_to_jiffies(100)   /* transfer timeout */
39 #define AT91_I2C_DMA_THRESHOLD  8                       /* enable DMA if transfer size is bigger than this threshold */
40 #define AUTOSUSPEND_TIMEOUT             2000
41
42 /* AT91 TWI register definitions */
43 #define AT91_TWI_CR             0x0000  /* Control Register */
44 #define AT91_TWI_START          0x0001  /* Send a Start Condition */
45 #define AT91_TWI_STOP           0x0002  /* Send a Stop Condition */
46 #define AT91_TWI_MSEN           0x0004  /* Master Transfer Enable */
47 #define AT91_TWI_SVDIS          0x0020  /* Slave Transfer Disable */
48 #define AT91_TWI_QUICK          0x0040  /* SMBus quick command */
49 #define AT91_TWI_SWRST          0x0080  /* Software Reset */
50
51 #define AT91_TWI_MMR            0x0004  /* Master Mode Register */
52 #define AT91_TWI_IADRSZ_1       0x0100  /* Internal Device Address Size */
53 #define AT91_TWI_MREAD          0x1000  /* Master Read Direction */
54
55 #define AT91_TWI_IADR           0x000c  /* Internal Address Register */
56
57 #define AT91_TWI_CWGR           0x0010  /* Clock Waveform Generator Reg */
58
59 #define AT91_TWI_SR             0x0020  /* Status Register */
60 #define AT91_TWI_TXCOMP         0x0001  /* Transmission Complete */
61 #define AT91_TWI_RXRDY          0x0002  /* Receive Holding Register Ready */
62 #define AT91_TWI_TXRDY          0x0004  /* Transmit Holding Register Ready */
63
64 #define AT91_TWI_OVRE           0x0040  /* Overrun Error */
65 #define AT91_TWI_UNRE           0x0080  /* Underrun Error */
66 #define AT91_TWI_NACK           0x0100  /* Not Acknowledged */
67
68 #define AT91_TWI_IER            0x0024  /* Interrupt Enable Register */
69 #define AT91_TWI_IDR            0x0028  /* Interrupt Disable Register */
70 #define AT91_TWI_IMR            0x002c  /* Interrupt Mask Register */
71 #define AT91_TWI_RHR            0x0030  /* Receive Holding Register */
72 #define AT91_TWI_THR            0x0034  /* Transmit Holding Register */
73
74 struct at91_twi_pdata {
75         unsigned clk_max_div;
76         unsigned clk_offset;
77         bool has_unre_flag;
78         struct at_dma_slave dma_slave;
79 };
80
81 struct at91_twi_dma {
82         struct dma_chan *chan_rx;
83         struct dma_chan *chan_tx;
84         struct scatterlist sg;
85         struct dma_async_tx_descriptor *data_desc;
86         enum dma_data_direction direction;
87         bool buf_mapped;
88         bool xfer_in_progress;
89 };
90
91 struct at91_twi_dev {
92         struct device *dev;
93         void __iomem *base;
94         struct completion cmd_complete;
95         struct clk *clk;
96         u8 *buf;
97         size_t buf_len;
98         struct i2c_msg *msg;
99         int irq;
100         unsigned imr;
101         unsigned transfer_status;
102         struct i2c_adapter adapter;
103         unsigned twi_cwgr_reg;
104         struct at91_twi_pdata *pdata;
105         bool use_dma;
106         bool recv_len_abort;
107         struct at91_twi_dma dma;
108 };
109
110 static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
111 {
112         return readl_relaxed(dev->base + reg);
113 }
114
115 static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
116 {
117         writel_relaxed(val, dev->base + reg);
118 }
119
120 static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
121 {
122         at91_twi_write(dev, AT91_TWI_IDR,
123                        AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY);
124 }
125
126 static void at91_twi_irq_save(struct at91_twi_dev *dev)
127 {
128         dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & 0x7;
129         at91_disable_twi_interrupts(dev);
130 }
131
132 static void at91_twi_irq_restore(struct at91_twi_dev *dev)
133 {
134         at91_twi_write(dev, AT91_TWI_IER, dev->imr);
135 }
136
137 static void at91_init_twi_bus(struct at91_twi_dev *dev)
138 {
139         at91_disable_twi_interrupts(dev);
140         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
141         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
142         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
143         at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
144 }
145
146 /*
147  * Calculate symmetric clock as stated in datasheet:
148  * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
149  */
150 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
151 {
152         int ckdiv, cdiv, div;
153         struct at91_twi_pdata *pdata = dev->pdata;
154         int offset = pdata->clk_offset;
155         int max_ckdiv = pdata->clk_max_div;
156
157         div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
158                                        2 * twi_clk) - offset);
159         ckdiv = fls(div >> 8);
160         cdiv = div >> ckdiv;
161
162         if (ckdiv > max_ckdiv) {
163                 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
164                          ckdiv, max_ckdiv);
165                 ckdiv = max_ckdiv;
166                 cdiv = 255;
167         }
168
169         dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
170         dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
171 }
172
173 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
174 {
175         struct at91_twi_dma *dma = &dev->dma;
176
177         at91_twi_irq_save(dev);
178
179         if (dma->xfer_in_progress) {
180                 if (dma->direction == DMA_FROM_DEVICE)
181                         dmaengine_terminate_all(dma->chan_rx);
182                 else
183                         dmaengine_terminate_all(dma->chan_tx);
184                 dma->xfer_in_progress = false;
185         }
186         if (dma->buf_mapped) {
187                 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg),
188                                  dev->buf_len, dma->direction);
189                 dma->buf_mapped = false;
190         }
191
192         at91_twi_irq_restore(dev);
193 }
194
195 static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
196 {
197         if (dev->buf_len <= 0)
198                 return;
199
200         at91_twi_write(dev, AT91_TWI_THR, *dev->buf);
201
202         /* send stop when last byte has been written */
203         if (--dev->buf_len == 0)
204                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
205
206         dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
207
208         ++dev->buf;
209 }
210
211 static void at91_twi_write_data_dma_callback(void *data)
212 {
213         struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
214
215         dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
216                          dev->buf_len, DMA_TO_DEVICE);
217
218         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
219 }
220
221 static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
222 {
223         dma_addr_t dma_addr;
224         struct dma_async_tx_descriptor *txdesc;
225         struct at91_twi_dma *dma = &dev->dma;
226         struct dma_chan *chan_tx = dma->chan_tx;
227
228         if (dev->buf_len <= 0)
229                 return;
230
231         dma->direction = DMA_TO_DEVICE;
232
233         at91_twi_irq_save(dev);
234         dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
235                                   DMA_TO_DEVICE);
236         if (dma_mapping_error(dev->dev, dma_addr)) {
237                 dev_err(dev->dev, "dma map failed\n");
238                 return;
239         }
240         dma->buf_mapped = true;
241         at91_twi_irq_restore(dev);
242         sg_dma_len(&dma->sg) = dev->buf_len;
243         sg_dma_address(&dma->sg) = dma_addr;
244
245         txdesc = dmaengine_prep_slave_sg(chan_tx, &dma->sg, 1, DMA_MEM_TO_DEV,
246                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
247         if (!txdesc) {
248                 dev_err(dev->dev, "dma prep slave sg failed\n");
249                 goto error;
250         }
251
252         txdesc->callback = at91_twi_write_data_dma_callback;
253         txdesc->callback_param = dev;
254
255         dma->xfer_in_progress = true;
256         dmaengine_submit(txdesc);
257         dma_async_issue_pending(chan_tx);
258
259         return;
260
261 error:
262         at91_twi_dma_cleanup(dev);
263 }
264
265 static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
266 {
267         if (dev->buf_len <= 0)
268                 return;
269
270         *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff;
271         --dev->buf_len;
272
273         /* return if aborting, we only needed to read RHR to clear RXRDY*/
274         if (dev->recv_len_abort)
275                 return;
276
277         /* handle I2C_SMBUS_BLOCK_DATA */
278         if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
279                 /* ensure length byte is a valid value */
280                 if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) {
281                         dev->msg->flags &= ~I2C_M_RECV_LEN;
282                         dev->buf_len += *dev->buf;
283                         dev->msg->len = dev->buf_len + 1;
284                         dev_dbg(dev->dev, "received block length %d\n",
285                                          dev->buf_len);
286                 } else {
287                         /* abort and send the stop by reading one more byte */
288                         dev->recv_len_abort = true;
289                         dev->buf_len = 1;
290                 }
291         }
292
293         /* send stop if second but last byte has been read */
294         if (dev->buf_len == 1)
295                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
296
297         dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
298
299         ++dev->buf;
300 }
301
302 static void at91_twi_read_data_dma_callback(void *data)
303 {
304         struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
305
306         dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
307                          dev->buf_len, DMA_FROM_DEVICE);
308
309         /* The last two bytes have to be read without using dma */
310         dev->buf += dev->buf_len - 2;
311         dev->buf_len = 2;
312         at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_RXRDY);
313 }
314
315 static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
316 {
317         dma_addr_t dma_addr;
318         struct dma_async_tx_descriptor *rxdesc;
319         struct at91_twi_dma *dma = &dev->dma;
320         struct dma_chan *chan_rx = dma->chan_rx;
321
322         dma->direction = DMA_FROM_DEVICE;
323
324         /* Keep in mind that we won't use dma to read the last two bytes */
325         at91_twi_irq_save(dev);
326         dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len - 2,
327                                   DMA_FROM_DEVICE);
328         if (dma_mapping_error(dev->dev, dma_addr)) {
329                 dev_err(dev->dev, "dma map failed\n");
330                 return;
331         }
332         dma->buf_mapped = true;
333         at91_twi_irq_restore(dev);
334         dma->sg.dma_address = dma_addr;
335         sg_dma_len(&dma->sg) = dev->buf_len - 2;
336
337         rxdesc = dmaengine_prep_slave_sg(chan_rx, &dma->sg, 1, DMA_DEV_TO_MEM,
338                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
339         if (!rxdesc) {
340                 dev_err(dev->dev, "dma prep slave sg failed\n");
341                 goto error;
342         }
343
344         rxdesc->callback = at91_twi_read_data_dma_callback;
345         rxdesc->callback_param = dev;
346
347         dma->xfer_in_progress = true;
348         dmaengine_submit(rxdesc);
349         dma_async_issue_pending(dma->chan_rx);
350
351         return;
352
353 error:
354         at91_twi_dma_cleanup(dev);
355 }
356
357 static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
358 {
359         struct at91_twi_dev *dev = dev_id;
360         const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
361         const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
362
363         if (!irqstatus)
364                 return IRQ_NONE;
365         else if (irqstatus & AT91_TWI_RXRDY)
366                 at91_twi_read_next_byte(dev);
367         else if (irqstatus & AT91_TWI_TXRDY)
368                 at91_twi_write_next_byte(dev);
369
370         /* catch error flags */
371         dev->transfer_status |= status;
372
373         if (irqstatus & AT91_TWI_TXCOMP) {
374                 at91_disable_twi_interrupts(dev);
375                 complete(&dev->cmd_complete);
376         }
377
378         return IRQ_HANDLED;
379 }
380
381 static int at91_do_twi_transfer(struct at91_twi_dev *dev)
382 {
383         int ret;
384         unsigned long time_left;
385         bool has_unre_flag = dev->pdata->has_unre_flag;
386
387         dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
388                 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
389
390         reinit_completion(&dev->cmd_complete);
391         dev->transfer_status = 0;
392
393         if (!dev->buf_len) {
394                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
395                 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
396         } else if (dev->msg->flags & I2C_M_RD) {
397                 unsigned start_flags = AT91_TWI_START;
398
399                 if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
400                         dev_err(dev->dev, "RXRDY still set!");
401                         at91_twi_read(dev, AT91_TWI_RHR);
402                 }
403
404                 /* if only one byte is to be read, immediately stop transfer */
405                 if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
406                         start_flags |= AT91_TWI_STOP;
407                 at91_twi_write(dev, AT91_TWI_CR, start_flags);
408                 /*
409                  * When using dma, the last byte has to be read manually in
410                  * order to not send the stop command too late and then
411                  * to receive extra data. In practice, there are some issues
412                  * if you use the dma to read n-1 bytes because of latency.
413                  * Reading n-2 bytes with dma and the two last ones manually
414                  * seems to be the best solution.
415                  */
416                 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
417                         at91_twi_read_data_dma(dev);
418                         /*
419                          * It is important to enable TXCOMP irq here because
420                          * doing it only when transferring the last two bytes
421                          * will mask NACK errors since TXCOMP is set when a
422                          * NACK occurs.
423                          */
424                         at91_twi_write(dev, AT91_TWI_IER,
425                                AT91_TWI_TXCOMP);
426                 } else
427                         at91_twi_write(dev, AT91_TWI_IER,
428                                AT91_TWI_TXCOMP | AT91_TWI_RXRDY);
429         } else {
430                 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
431                         at91_twi_write_data_dma(dev);
432                         at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
433                 } else {
434                         at91_twi_write_next_byte(dev);
435                         at91_twi_write(dev, AT91_TWI_IER,
436                                 AT91_TWI_TXCOMP | AT91_TWI_TXRDY);
437                 }
438         }
439
440         time_left = wait_for_completion_timeout(&dev->cmd_complete,
441                                               dev->adapter.timeout);
442         if (time_left == 0) {
443                 dev_err(dev->dev, "controller timed out\n");
444                 at91_init_twi_bus(dev);
445                 ret = -ETIMEDOUT;
446                 goto error;
447         }
448         if (dev->transfer_status & AT91_TWI_NACK) {
449                 dev_dbg(dev->dev, "received nack\n");
450                 ret = -EREMOTEIO;
451                 goto error;
452         }
453         if (dev->transfer_status & AT91_TWI_OVRE) {
454                 dev_err(dev->dev, "overrun while reading\n");
455                 ret = -EIO;
456                 goto error;
457         }
458         if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
459                 dev_err(dev->dev, "underrun while writing\n");
460                 ret = -EIO;
461                 goto error;
462         }
463         if (dev->recv_len_abort) {
464                 dev_err(dev->dev, "invalid smbus block length recvd\n");
465                 ret = -EPROTO;
466                 goto error;
467         }
468
469         dev_dbg(dev->dev, "transfer complete\n");
470
471         return 0;
472
473 error:
474         at91_twi_dma_cleanup(dev);
475         return ret;
476 }
477
478 static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
479 {
480         struct at91_twi_dev *dev = i2c_get_adapdata(adap);
481         int ret;
482         unsigned int_addr_flag = 0;
483         struct i2c_msg *m_start = msg;
484
485         dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
486
487         ret = pm_runtime_get_sync(dev->dev);
488         if (ret < 0)
489                 goto out;
490
491         if (num == 2) {
492                 int internal_address = 0;
493                 int i;
494
495                 /* 1st msg is put into the internal address, start with 2nd */
496                 m_start = &msg[1];
497                 for (i = 0; i < msg->len; ++i) {
498                         const unsigned addr = msg->buf[msg->len - 1 - i];
499
500                         internal_address |= addr << (8 * i);
501                         int_addr_flag += AT91_TWI_IADRSZ_1;
502                 }
503                 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
504         }
505
506         at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag
507                        | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
508
509         dev->buf_len = m_start->len;
510         dev->buf = m_start->buf;
511         dev->msg = m_start;
512         dev->recv_len_abort = false;
513
514         ret = at91_do_twi_transfer(dev);
515
516         ret = (ret < 0) ? ret : num;
517 out:
518         pm_runtime_mark_last_busy(dev->dev);
519         pm_runtime_put_autosuspend(dev->dev);
520
521         return ret;
522 }
523
524 /*
525  * The hardware can handle at most two messages concatenated by a
526  * repeated start via it's internal address feature.
527  */
528 static struct i2c_adapter_quirks at91_twi_quirks = {
529         .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
530         .max_comb_1st_msg_len = 3,
531 };
532
533 static u32 at91_twi_func(struct i2c_adapter *adapter)
534 {
535         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
536                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
537 }
538
539 static struct i2c_algorithm at91_twi_algorithm = {
540         .master_xfer    = at91_twi_xfer,
541         .functionality  = at91_twi_func,
542 };
543
544 static struct at91_twi_pdata at91rm9200_config = {
545         .clk_max_div = 5,
546         .clk_offset = 3,
547         .has_unre_flag = true,
548 };
549
550 static struct at91_twi_pdata at91sam9261_config = {
551         .clk_max_div = 5,
552         .clk_offset = 4,
553         .has_unre_flag = false,
554 };
555
556 static struct at91_twi_pdata at91sam9260_config = {
557         .clk_max_div = 7,
558         .clk_offset = 4,
559         .has_unre_flag = false,
560 };
561
562 static struct at91_twi_pdata at91sam9g20_config = {
563         .clk_max_div = 7,
564         .clk_offset = 4,
565         .has_unre_flag = false,
566 };
567
568 static struct at91_twi_pdata at91sam9g10_config = {
569         .clk_max_div = 7,
570         .clk_offset = 4,
571         .has_unre_flag = false,
572 };
573
574 static const struct platform_device_id at91_twi_devtypes[] = {
575         {
576                 .name = "i2c-at91rm9200",
577                 .driver_data = (unsigned long) &at91rm9200_config,
578         }, {
579                 .name = "i2c-at91sam9261",
580                 .driver_data = (unsigned long) &at91sam9261_config,
581         }, {
582                 .name = "i2c-at91sam9260",
583                 .driver_data = (unsigned long) &at91sam9260_config,
584         }, {
585                 .name = "i2c-at91sam9g20",
586                 .driver_data = (unsigned long) &at91sam9g20_config,
587         }, {
588                 .name = "i2c-at91sam9g10",
589                 .driver_data = (unsigned long) &at91sam9g10_config,
590         }, {
591                 /* sentinel */
592         }
593 };
594
595 #if defined(CONFIG_OF)
596 static struct at91_twi_pdata at91sam9x5_config = {
597         .clk_max_div = 7,
598         .clk_offset = 4,
599         .has_unre_flag = false,
600 };
601
602 static const struct of_device_id atmel_twi_dt_ids[] = {
603         {
604                 .compatible = "atmel,at91rm9200-i2c",
605                 .data = &at91rm9200_config,
606         } , {
607                 .compatible = "atmel,at91sam9260-i2c",
608                 .data = &at91sam9260_config,
609         } , {
610                 .compatible = "atmel,at91sam9261-i2c",
611                 .data = &at91sam9261_config,
612         } , {
613                 .compatible = "atmel,at91sam9g20-i2c",
614                 .data = &at91sam9g20_config,
615         } , {
616                 .compatible = "atmel,at91sam9g10-i2c",
617                 .data = &at91sam9g10_config,
618         }, {
619                 .compatible = "atmel,at91sam9x5-i2c",
620                 .data = &at91sam9x5_config,
621         }, {
622                 /* sentinel */
623         }
624 };
625 MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
626 #endif
627
628 static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
629 {
630         int ret = 0;
631         struct dma_slave_config slave_config;
632         struct at91_twi_dma *dma = &dev->dma;
633
634         memset(&slave_config, 0, sizeof(slave_config));
635         slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
636         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
637         slave_config.src_maxburst = 1;
638         slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
639         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
640         slave_config.dst_maxburst = 1;
641         slave_config.device_fc = false;
642
643         dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx");
644         if (IS_ERR(dma->chan_tx)) {
645                 ret = PTR_ERR(dma->chan_tx);
646                 dma->chan_tx = NULL;
647                 goto error;
648         }
649
650         dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx");
651         if (IS_ERR(dma->chan_rx)) {
652                 ret = PTR_ERR(dma->chan_rx);
653                 dma->chan_rx = NULL;
654                 goto error;
655         }
656
657         slave_config.direction = DMA_MEM_TO_DEV;
658         if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
659                 dev_err(dev->dev, "failed to configure tx channel\n");
660                 ret = -EINVAL;
661                 goto error;
662         }
663
664         slave_config.direction = DMA_DEV_TO_MEM;
665         if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
666                 dev_err(dev->dev, "failed to configure rx channel\n");
667                 ret = -EINVAL;
668                 goto error;
669         }
670
671         sg_init_table(&dma->sg, 1);
672         dma->buf_mapped = false;
673         dma->xfer_in_progress = false;
674         dev->use_dma = true;
675
676         dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
677                  dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
678
679         return ret;
680
681 error:
682         if (ret != -EPROBE_DEFER)
683                 dev_info(dev->dev, "can't use DMA, error %d\n", ret);
684         if (dma->chan_rx)
685                 dma_release_channel(dma->chan_rx);
686         if (dma->chan_tx)
687                 dma_release_channel(dma->chan_tx);
688         return ret;
689 }
690
691 static struct at91_twi_pdata *at91_twi_get_driver_data(
692                                         struct platform_device *pdev)
693 {
694         if (pdev->dev.of_node) {
695                 const struct of_device_id *match;
696                 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
697                 if (!match)
698                         return NULL;
699                 return (struct at91_twi_pdata *)match->data;
700         }
701         return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
702 }
703
704 static int at91_twi_probe(struct platform_device *pdev)
705 {
706         struct at91_twi_dev *dev;
707         struct resource *mem;
708         int rc;
709         u32 phy_addr;
710         u32 bus_clk_rate;
711
712         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
713         if (!dev)
714                 return -ENOMEM;
715         init_completion(&dev->cmd_complete);
716         dev->dev = &pdev->dev;
717
718         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
719         if (!mem)
720                 return -ENODEV;
721         phy_addr = mem->start;
722
723         dev->pdata = at91_twi_get_driver_data(pdev);
724         if (!dev->pdata)
725                 return -ENODEV;
726
727         dev->base = devm_ioremap_resource(&pdev->dev, mem);
728         if (IS_ERR(dev->base))
729                 return PTR_ERR(dev->base);
730
731         dev->irq = platform_get_irq(pdev, 0);
732         if (dev->irq < 0)
733                 return dev->irq;
734
735         rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
736                          dev_name(dev->dev), dev);
737         if (rc) {
738                 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
739                 return rc;
740         }
741
742         platform_set_drvdata(pdev, dev);
743
744         dev->clk = devm_clk_get(dev->dev, NULL);
745         if (IS_ERR(dev->clk)) {
746                 dev_err(dev->dev, "no clock defined\n");
747                 return -ENODEV;
748         }
749         clk_prepare_enable(dev->clk);
750
751         if (dev->dev->of_node) {
752                 rc = at91_twi_configure_dma(dev, phy_addr);
753                 if (rc == -EPROBE_DEFER)
754                         return rc;
755         }
756
757         rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
758                         &bus_clk_rate);
759         if (rc)
760                 bus_clk_rate = DEFAULT_TWI_CLK_HZ;
761
762         at91_calc_twi_clock(dev, bus_clk_rate);
763         at91_init_twi_bus(dev);
764
765         snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
766         i2c_set_adapdata(&dev->adapter, dev);
767         dev->adapter.owner = THIS_MODULE;
768         dev->adapter.class = I2C_CLASS_DEPRECATED;
769         dev->adapter.algo = &at91_twi_algorithm;
770         dev->adapter.quirks = &at91_twi_quirks;
771         dev->adapter.dev.parent = dev->dev;
772         dev->adapter.nr = pdev->id;
773         dev->adapter.timeout = AT91_I2C_TIMEOUT;
774         dev->adapter.dev.of_node = pdev->dev.of_node;
775
776         pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
777         pm_runtime_use_autosuspend(dev->dev);
778         pm_runtime_set_active(dev->dev);
779         pm_runtime_enable(dev->dev);
780
781         rc = i2c_add_numbered_adapter(&dev->adapter);
782         if (rc) {
783                 dev_err(dev->dev, "Adapter %s registration failed\n",
784                         dev->adapter.name);
785                 clk_disable_unprepare(dev->clk);
786
787                 pm_runtime_disable(dev->dev);
788                 pm_runtime_set_suspended(dev->dev);
789
790                 return rc;
791         }
792
793         dev_info(dev->dev, "AT91 i2c bus driver.\n");
794         return 0;
795 }
796
797 static int at91_twi_remove(struct platform_device *pdev)
798 {
799         struct at91_twi_dev *dev = platform_get_drvdata(pdev);
800
801         i2c_del_adapter(&dev->adapter);
802         clk_disable_unprepare(dev->clk);
803
804         pm_runtime_disable(dev->dev);
805         pm_runtime_set_suspended(dev->dev);
806
807         return 0;
808 }
809
810 #ifdef CONFIG_PM
811
812 static int at91_twi_runtime_suspend(struct device *dev)
813 {
814         struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
815
816         clk_disable_unprepare(twi_dev->clk);
817
818         pinctrl_pm_select_sleep_state(dev);
819
820         return 0;
821 }
822
823 static int at91_twi_runtime_resume(struct device *dev)
824 {
825         struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
826
827         pinctrl_pm_select_default_state(dev);
828
829         return clk_prepare_enable(twi_dev->clk);
830 }
831
832 static int at91_twi_suspend_noirq(struct device *dev)
833 {
834         if (!pm_runtime_status_suspended(dev))
835                 at91_twi_runtime_suspend(dev);
836
837         return 0;
838 }
839
840 static int at91_twi_resume_noirq(struct device *dev)
841 {
842         int ret;
843
844         if (!pm_runtime_status_suspended(dev)) {
845                 ret = at91_twi_runtime_resume(dev);
846                 if (ret)
847                         return ret;
848         }
849
850         pm_runtime_mark_last_busy(dev);
851         pm_request_autosuspend(dev);
852
853         return 0;
854 }
855
856 static const struct dev_pm_ops at91_twi_pm = {
857         .suspend_noirq  = at91_twi_suspend_noirq,
858         .resume_noirq   = at91_twi_resume_noirq,
859         .runtime_suspend        = at91_twi_runtime_suspend,
860         .runtime_resume         = at91_twi_runtime_resume,
861 };
862
863 #define at91_twi_pm_ops (&at91_twi_pm)
864 #else
865 #define at91_twi_pm_ops NULL
866 #endif
867
868 static struct platform_driver at91_twi_driver = {
869         .probe          = at91_twi_probe,
870         .remove         = at91_twi_remove,
871         .id_table       = at91_twi_devtypes,
872         .driver         = {
873                 .name   = "at91_i2c",
874                 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
875                 .pm     = at91_twi_pm_ops,
876         },
877 };
878
879 static int __init at91_twi_init(void)
880 {
881         return platform_driver_register(&at91_twi_driver);
882 }
883
884 static void __exit at91_twi_exit(void)
885 {
886         platform_driver_unregister(&at91_twi_driver);
887 }
888
889 subsys_initcall(at91_twi_init);
890 module_exit(at91_twi_exit);
891
892 MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
893 MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
894 MODULE_LICENSE("GPL");
895 MODULE_ALIAS("platform:at91_i2c");