drivers/i2c/busses/i2c-eg20t.c

   1 /*
   2  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/i2c.h>
  24 #include <linux/fs.h>
  25 #include <linux/io.h>
  26 #include <linux/types.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/pci.h>
  30 #include <linux/mutex.h>
  31 #include <linux/ktime.h>
  32 #include <linux/slab.h>
  33
  34 #define PCH_EVENT_SET   0       /* I2C Interrupt Event Set Status */
  35 #define PCH_EVENT_NONE  1       /* I2C Interrupt Event Clear Status */
  36 #define PCH_MAX_CLK             100000  /* Maximum Clock speed in MHz */
  37 #define PCH_BUFFER_MODE_ENABLE  0x0002  /* flag for Buffer mode enable */
  38 #define PCH_EEPROM_SW_RST_MODE_ENABLE   0x0008  /* EEPROM SW RST enable flag */
  39
  40 #define PCH_I2CSADR     0x00    /* I2C slave address register */
  41 #define PCH_I2CCTL      0x04    /* I2C control register */
  42 #define PCH_I2CSR       0x08    /* I2C status register */
  43 #define PCH_I2CDR       0x0C    /* I2C data register */
  44 #define PCH_I2CMON      0x10    /* I2C bus monitor register */
  45 #define PCH_I2CBC       0x14    /* I2C bus transfer rate setup counter */
  46 #define PCH_I2CMOD      0x18    /* I2C mode register */
  47 #define PCH_I2CBUFSLV   0x1C    /* I2C buffer mode slave address register */
  48 #define PCH_I2CBUFSUB   0x20    /* I2C buffer mode subaddress register */
  49 #define PCH_I2CBUFFOR   0x24    /* I2C buffer mode format register */
  50 #define PCH_I2CBUFCTL   0x28    /* I2C buffer mode control register */
  51 #define PCH_I2CBUFMSK   0x2C    /* I2C buffer mode interrupt mask register */
  52 #define PCH_I2CBUFSTA   0x30    /* I2C buffer mode status register */
  53 #define PCH_I2CBUFLEV   0x34    /* I2C buffer mode level register */
  54 #define PCH_I2CESRFOR   0x38    /* EEPROM software reset mode format register */
  55 #define PCH_I2CESRCTL   0x3C    /* EEPROM software reset mode ctrl register */
  56 #define PCH_I2CESRMSK   0x40    /* EEPROM software reset mode */
  57 #define PCH_I2CESRSTA   0x44    /* EEPROM software reset mode status register */
  58 #define PCH_I2CTMR      0x48    /* I2C timer register */
  59 #define PCH_I2CSRST     0xFC    /* I2C reset register */
  60 #define PCH_I2CNF       0xF8    /* I2C noise filter register */
  61
  62 #define BUS_IDLE_TIMEOUT        20
  63 #define PCH_I2CCTL_I2CMEN       0x0080
  64 #define TEN_BIT_ADDR_DEFAULT    0xF000
  65 #define TEN_BIT_ADDR_MASK       0xF0
  66 #define PCH_START               0x0020
  67 #define PCH_RESTART             0x0004
  68 #define PCH_ESR_START           0x0001
  69 #define PCH_BUFF_START          0x1
  70 #define PCH_REPSTART            0x0004
  71 #define PCH_ACK                 0x0008
  72 #define PCH_GETACK              0x0001
  73 #define CLR_REG                 0x0
  74 #define I2C_RD                  0x1
  75 #define I2CMCF_BIT              0x0080
  76 #define I2CMIF_BIT              0x0002
  77 #define I2CMAL_BIT              0x0010
  78 #define I2CBMFI_BIT             0x0001
  79 #define I2CBMAL_BIT             0x0002
  80 #define I2CBMNA_BIT             0x0004
  81 #define I2CBMTO_BIT             0x0008
  82 #define I2CBMIS_BIT             0x0010
  83 #define I2CESRFI_BIT            0X0001
  84 #define I2CESRTO_BIT            0x0002
  85 #define I2CESRFIIE_BIT          0x1
  86 #define I2CESRTOIE_BIT          0x2
  87 #define I2CBMDZ_BIT             0x0040
  88 #define I2CBMAG_BIT             0x0020
  89 #define I2CMBB_BIT              0x0020
  90 #define BUFFER_MODE_MASK        (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
  91                                 I2CBMTO_BIT | I2CBMIS_BIT)
  92 #define I2C_ADDR_MSK            0xFF
  93 #define I2C_MSB_2B_MSK          0x300
  94 #define FAST_MODE_CLK           400
  95 #define FAST_MODE_EN            0x0001
  96 #define SUB_ADDR_LEN_MAX        4
  97 #define BUF_LEN_MAX             32
  98 #define PCH_BUFFER_MODE         0x1
  99 #define EEPROM_SW_RST_MODE      0x0002
 100 #define NORMAL_INTR_ENBL        0x0300
 101 #define EEPROM_RST_INTR_ENBL    (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
 102 #define EEPROM_RST_INTR_DISBL   0x0
 103 #define BUFFER_MODE_INTR_ENBL   0x001F
 104 #define BUFFER_MODE_INTR_DISBL  0x0
 105 #define NORMAL_MODE             0x0
 106 #define BUFFER_MODE             0x1
 107 #define EEPROM_SR_MODE          0x2
 108 #define I2C_TX_MODE             0x0010
 109 #define PCH_BUF_TX              0xFFF7
 110 #define PCH_BUF_RD              0x0008
 111 #define I2C_ERROR_MASK  (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
 112                         I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
 113 #define I2CMAL_EVENT            0x0001
 114 #define I2CMCF_EVENT            0x0002
 115 #define I2CBMFI_EVENT           0x0004
 116 #define I2CBMAL_EVENT           0x0008
 117 #define I2CBMNA_EVENT           0x0010
 118 #define I2CBMTO_EVENT           0x0020
 119 #define I2CBMIS_EVENT           0x0040
 120 #define I2CESRFI_EVENT          0x0080
 121 #define I2CESRTO_EVENT          0x0100
 122 #define PCI_DEVICE_ID_PCH_I2C   0x8817
 123
 124 #define pch_dbg(adap, fmt, arg...)  \
 125         dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 126
 127 #define pch_err(adap, fmt, arg...)  \
 128         dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 129
 130 #define pch_pci_err(pdev, fmt, arg...)  \
 131         dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
 132
 133 #define pch_pci_dbg(pdev, fmt, arg...)  \
 134         dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
 135
 136 /*
 137 Set the number of I2C instance max
 138 Intel EG20T PCH :               1ch
 139 LAPIS Semiconductor ML7213 IOH :        2ch
 140 LAPIS Semiconductor ML7831 IOH :        1ch
 141 */
 142 #define PCH_I2C_MAX_DEV                 2
 143
 144 /**
 145  * struct i2c_algo_pch_data - for I2C driver functionalities
 146  * @pch_adapter:                stores the reference to i2c_adapter structure
 147  * @p_adapter_info:             stores the reference to adapter_info structure
 148  * @pch_base_address:           specifies the remapped base address
 149  * @pch_buff_mode_en:           specifies if buffer mode is enabled
 150  * @pch_event_flag:             specifies occurrence of interrupt events
 151  * @pch_i2c_xfer_in_progress:   specifies whether the transfer is completed
 152  */
 153 struct i2c_algo_pch_data {
 154         struct i2c_adapter pch_adapter;
 155         struct adapter_info *p_adapter_info;
 156         void __iomem *pch_base_address;
 157         int pch_buff_mode_en;
 158         u32 pch_event_flag;
 159         bool pch_i2c_xfer_in_progress;
 160 };
 161
 162 /**
 163  * struct adapter_info - This structure holds the adapter information for the
 164                          PCH i2c controller
 165  * @pch_data:           stores a list of i2c_algo_pch_data
 166  * @pch_i2c_suspended:  specifies whether the system is suspended or not
 167  *                      perhaps with more lines and words.
 168  * @ch_num:             specifies the number of i2c instance
 169  *
 170  * pch_data has as many elements as maximum I2C channels
 171  */
 172 struct adapter_info {
 173         struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
 174         bool pch_i2c_suspended;
 175         int ch_num;
 176 };
 177
 178
 179 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
 180 static int pch_clk = 50000;     /* specifies I2C clock speed in KHz */
 181 static wait_queue_head_t pch_event;
 182 static DEFINE_MUTEX(pch_mutex);
 183
 184 /* Definition for ML7213 by LAPIS Semiconductor */
 185 #define PCI_VENDOR_ID_ROHM              0x10DB
 186 #define PCI_DEVICE_ID_ML7213_I2C        0x802D
 187 #define PCI_DEVICE_ID_ML7223_I2C        0x8010
 188 #define PCI_DEVICE_ID_ML7831_I2C        0x8817
 189
 190 static DEFINE_PCI_DEVICE_TABLE(pch_pcidev_id) = {
 191         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
 192         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
 193         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
 194         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
 195         {0,}
 196 };
 197
 198 static irqreturn_t pch_i2c_handler(int irq, void *pData);
 199
 200 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
 201 {
 202         u32 val;
 203         val = ioread32(addr + offset);
 204         val |= bitmask;
 205         iowrite32(val, addr + offset);
 206 }
 207
 208 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
 209 {
 210         u32 val;
 211         val = ioread32(addr + offset);
 212         val &= (~bitmask);
 213         iowrite32(val, addr + offset);
 214 }
 215
 216 /**
 217  * pch_i2c_init() - hardware initialization of I2C module
 218  * @adap:       Pointer to struct i2c_algo_pch_data.
 219  */
 220 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
 221 {
 222         void __iomem *p = adap->pch_base_address;
 223         u32 pch_i2cbc;
 224         u32 pch_i2ctmr;
 225         u32 reg_value;
 226
 227         /* reset I2C controller */
 228         iowrite32(0x01, p + PCH_I2CSRST);
 229         msleep(20);
 230         iowrite32(0x0, p + PCH_I2CSRST);
 231
 232         /* Initialize I2C registers */
 233         iowrite32(0x21, p + PCH_I2CNF);
 234
 235         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
 236
 237         if (pch_i2c_speed != 400)
 238                 pch_i2c_speed = 100;
 239
 240         reg_value = PCH_I2CCTL_I2CMEN;
 241         if (pch_i2c_speed == FAST_MODE_CLK) {
 242                 reg_value |= FAST_MODE_EN;
 243                 pch_dbg(adap, "Fast mode enabled\n");
 244         }
 245
 246         if (pch_clk > PCH_MAX_CLK)
 247                 pch_clk = 62500;
 248
 249         pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
 250         /* Set transfer speed in I2CBC */
 251         iowrite32(pch_i2cbc, p + PCH_I2CBC);
 252
 253         pch_i2ctmr = (pch_clk) / 8;
 254         iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
 255
 256         reg_value |= NORMAL_INTR_ENBL;  /* Enable interrupts in normal mode */
 257         iowrite32(reg_value, p + PCH_I2CCTL);
 258
 259         pch_dbg(adap,
 260                 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
 261                 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
 262
 263         init_waitqueue_head(&pch_event);
 264 }
 265
 266 static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
 267 {
 268         return cmp1.tv64 < cmp2.tv64;
 269 }
 270
 271 /**
 272  * pch_i2c_wait_for_bus_idle() - check the status of bus.
 273  * @adap:       Pointer to struct i2c_algo_pch_data.
 274  * @timeout:    waiting time counter (ms).
 275  */
 276 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
 277                                      s32 timeout)
 278 {
 279         void __iomem *p = adap->pch_base_address;
 280         int schedule = 0;
 281         unsigned long end = jiffies + msecs_to_jiffies(timeout);
 282
 283         while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
 284                 if (time_after(jiffies, end)) {
 285                         pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 286                         pch_err(adap, "%s: Timeout Error.return%d\n",
 287                                         __func__, -ETIME);
 288                         pch_i2c_init(adap);
 289
 290                         return -ETIME;
 291                 }
 292
 293                 if (!schedule)
 294                         /* Retry after some usecs */
 295                         udelay(5);
 296                 else
 297                         /* Wait a bit more without consuming CPU */
 298                         usleep_range(20, 1000);
 299
 300                 schedule = 1;
 301         }
 302
 303         return 0;
 304 }
 305
 306 /**
 307  * pch_i2c_start() - Generate I2C start condition in normal mode.
 308  * @adap:       Pointer to struct i2c_algo_pch_data.
 309  *
 310  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
 311  */
 312 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
 313 {
 314         void __iomem *p = adap->pch_base_address;
 315         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 316         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 317 }
 318
 319 /**
 320  * pch_i2c_getack() - to confirm ACK/NACK
 321  * @adap:       Pointer to struct i2c_algo_pch_data.
 322  */
 323 static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
 324 {
 325         u32 reg_val;
 326         void __iomem *p = adap->pch_base_address;
 327         reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
 328
 329         if (reg_val != 0) {
 330                 pch_err(adap, "return%d\n", -EPROTO);
 331                 return -EPROTO;
 332         }
 333
 334         return 0;
 335 }
 336
 337 /**
 338  * pch_i2c_stop() - generate stop condition in normal mode.
 339  * @adap:       Pointer to struct i2c_algo_pch_data.
 340  */
 341 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
 342 {
 343         void __iomem *p = adap->pch_base_address;
 344         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 345         /* clear the start bit */
 346         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 347 }
 348
 349 static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
 350 {
 351         long ret;
 352
 353         ret = wait_event_timeout(pch_event,
 354                         (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
 355         if (!ret) {
 356                 pch_err(adap, "%s:wait-event timeout\n", __func__);
 357                 adap->pch_event_flag = 0;
 358                 pch_i2c_stop(adap);
 359                 pch_i2c_init(adap);
 360                 return -ETIMEDOUT;
 361         }
 362
 363         if (adap->pch_event_flag & I2C_ERROR_MASK) {
 364                 pch_err(adap, "Lost Arbitration\n");
 365                 adap->pch_event_flag = 0;
 366                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
 367                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
 368                 pch_i2c_init(adap);
 369                 return -EAGAIN;
 370         }
 371
 372         adap->pch_event_flag = 0;
 373
 374         if (pch_i2c_getack(adap)) {
 375                 pch_dbg(adap, "Receive NACK for slave address"
 376                         "setting\n");
 377                 return -EIO;
 378         }
 379
 380         return 0;
 381 }
 382
 383 /**
 384  * pch_i2c_repstart() - generate repeated start condition in normal mode
 385  * @adap:       Pointer to struct i2c_algo_pch_data.
 386  */
 387 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
 388 {
 389         void __iomem *p = adap->pch_base_address;
 390         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 391         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
 392 }
 393
 394 /**
 395  * pch_i2c_writebytes() - write data to I2C bus in normal mode
 396  * @i2c_adap:   Pointer to the struct i2c_adapter.
 397  * @last:       specifies whether last message or not.
 398  *              In the case of compound mode it will be 1 for last message,
 399  *              otherwise 0.
 400  * @first:      specifies whether first message or not.
 401  *              1 for first message otherwise 0.
 402  */
 403 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
 404                               struct i2c_msg *msgs, u32 last, u32 first)
 405 {
 406         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 407         u8 *buf;
 408         u32 length;
 409         u32 addr;
 410         u32 addr_2_msb;
 411         u32 addr_8_lsb;
 412         s32 wrcount;
 413         s32 rtn;
 414         void __iomem *p = adap->pch_base_address;
 415
 416         length = msgs->len;
 417         buf = msgs->buf;
 418         addr = msgs->addr;
 419
 420         /* enable master tx */
 421         pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 422
 423         pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
 424                 length);
 425
 426         if (first) {
 427                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 428                         return -ETIME;
 429         }
 430
 431         if (msgs->flags & I2C_M_TEN) {
 432                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
 433                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 434                 if (first)
 435                         pch_i2c_start(adap);
 436
 437                 rtn = pch_i2c_wait_for_check_xfer(adap);
 438                 if (rtn)
 439                         return rtn;
 440
 441                 addr_8_lsb = (addr & I2C_ADDR_MSK);
 442                 iowrite32(addr_8_lsb, p + PCH_I2CDR);
 443         } else {
 444                 /* set 7 bit slave address and R/W bit as 0 */
 445                 iowrite32(addr << 1, p + PCH_I2CDR);
 446                 if (first)
 447                         pch_i2c_start(adap);
 448         }
 449
 450         rtn = pch_i2c_wait_for_check_xfer(adap);
 451         if (rtn)
 452                 return rtn;
 453
 454         for (wrcount = 0; wrcount < length; ++wrcount) {
 455                 /* write buffer value to I2C data register */
 456                 iowrite32(buf[wrcount], p + PCH_I2CDR);
 457                 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
 458
 459                 rtn = pch_i2c_wait_for_check_xfer(adap);
 460                 if (rtn)
 461                         return rtn;
 462
 463                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
 464                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
 465         }
 466
 467         /* check if this is the last message */
 468         if (last)
 469                 pch_i2c_stop(adap);
 470         else
 471                 pch_i2c_repstart(adap);
 472
 473         pch_dbg(adap, "return=%d\n", wrcount);
 474
 475         return wrcount;
 476 }
 477
 478 /**
 479  * pch_i2c_sendack() - send ACK
 480  * @adap:       Pointer to struct i2c_algo_pch_data.
 481  */
 482 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
 483 {
 484         void __iomem *p = adap->pch_base_address;
 485         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 486         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 487 }
 488
 489 /**
 490  * pch_i2c_sendnack() - send NACK
 491  * @adap:       Pointer to struct i2c_algo_pch_data.
 492  */
 493 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
 494 {
 495         void __iomem *p = adap->pch_base_address;
 496         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 497         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 498 }
 499
 500 /**
 501  * pch_i2c_restart() - Generate I2C restart condition in normal mode.
 502  * @adap:       Pointer to struct i2c_algo_pch_data.
 503  *
 504  * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
 505  */
 506 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
 507 {
 508         void __iomem *p = adap->pch_base_address;
 509         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 510         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
 511 }
 512
 513 /**
 514  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
 515  * @i2c_adap:   Pointer to the struct i2c_adapter.
 516  * @msgs:       Pointer to i2c_msg structure.
 517  * @last:       specifies whether last message or not.
 518  * @first:      specifies whether first message or not.
 519  */
 520 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
 521                              u32 last, u32 first)
 522 {
 523         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 524
 525         u8 *buf;
 526         u32 count;
 527         u32 length;
 528         u32 addr;
 529         u32 addr_2_msb;
 530         u32 addr_8_lsb;
 531         void __iomem *p = adap->pch_base_address;
 532         s32 rtn;
 533
 534         length = msgs->len;
 535         buf = msgs->buf;
 536         addr = msgs->addr;
 537
 538         /* enable master reception */
 539         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 540
 541         if (first) {
 542                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 543                         return -ETIME;
 544         }
 545
 546         if (msgs->flags & I2C_M_TEN) {
 547                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
 548                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 549                 if (first)
 550                         pch_i2c_start(adap);
 551
 552                 rtn = pch_i2c_wait_for_check_xfer(adap);
 553                 if (rtn)
 554                         return rtn;
 555
 556                 addr_8_lsb = (addr & I2C_ADDR_MSK);
 557                 iowrite32(addr_8_lsb, p + PCH_I2CDR);
 558
 559                 pch_i2c_restart(adap);
 560
 561                 rtn = pch_i2c_wait_for_check_xfer(adap);
 562                 if (rtn)
 563                         return rtn;
 564
 565                 addr_2_msb |= I2C_RD;
 566                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 567         } else {
 568                 /* 7 address bits + R/W bit */
 569                 addr = (((addr) << 1) | (I2C_RD));
 570                 iowrite32(addr, p + PCH_I2CDR);
 571         }
 572
 573         /* check if it is the first message */
 574         if (first)
 575                 pch_i2c_start(adap);
 576
 577         rtn = pch_i2c_wait_for_check_xfer(adap);
 578         if (rtn)
 579                 return rtn;
 580
 581         if (length == 0) {
 582                 pch_i2c_stop(adap);
 583                 ioread32(p + PCH_I2CDR); /* Dummy read needs */
 584
 585                 count = length;
 586         } else {
 587                 int read_index;
 588                 int loop;
 589                 pch_i2c_sendack(adap);
 590
 591                 /* Dummy read */
 592                 for (loop = 1, read_index = 0; loop < length; loop++) {
 593                         buf[read_index] = ioread32(p + PCH_I2CDR);
 594
 595                         if (loop != 1)
 596                                 read_index++;
 597
 598                         rtn = pch_i2c_wait_for_check_xfer(adap);
 599                         if (rtn)
 600                                 return rtn;
 601                 }       /* end for */
 602
 603                 pch_i2c_sendnack(adap);
 604
 605                 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
 606
 607                 if (length != 1)
 608                         read_index++;
 609
 610                 rtn = pch_i2c_wait_for_check_xfer(adap);
 611                 if (rtn)
 612                         return rtn;
 613
 614                 if (last)
 615                         pch_i2c_stop(adap);
 616                 else
 617                         pch_i2c_repstart(adap);
 618
 619                 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
 620                 count = read_index;
 621         }
 622
 623         return count;
 624 }
 625
 626 /**
 627  * pch_i2c_cb() - Interrupt handler Call back function
 628  * @adap:       Pointer to struct i2c_algo_pch_data.
 629  */
 630 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
 631 {
 632         u32 sts;
 633         void __iomem *p = adap->pch_base_address;
 634
 635         sts = ioread32(p + PCH_I2CSR);
 636         sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
 637         if (sts & I2CMAL_BIT)
 638                 adap->pch_event_flag |= I2CMAL_EVENT;
 639
 640         if (sts & I2CMCF_BIT)
 641                 adap->pch_event_flag |= I2CMCF_EVENT;
 642
 643         /* clear the applicable bits */
 644         pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
 645
 646         pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 647
 648         wake_up(&pch_event);
 649 }
 650
 651 /**
 652  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
 653  * @irq:        irq number.
 654  * @pData:      cookie passed back to the handler function.
 655  */
 656 static irqreturn_t pch_i2c_handler(int irq, void *pData)
 657 {
 658         u32 reg_val;
 659         int flag;
 660         int i;
 661         struct adapter_info *adap_info = pData;
 662         void __iomem *p;
 663         u32 mode;
 664
 665         for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
 666                 p = adap_info->pch_data[i].pch_base_address;
 667                 mode = ioread32(p + PCH_I2CMOD);
 668                 mode &= BUFFER_MODE | EEPROM_SR_MODE;
 669                 if (mode != NORMAL_MODE) {
 670                         pch_err(adap_info->pch_data,
 671                                 "I2C-%d mode(%d) is not supported\n", mode, i);
 672                         continue;
 673                 }
 674                 reg_val = ioread32(p + PCH_I2CSR);
 675                 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
 676                         pch_i2c_cb(&adap_info->pch_data[i]);
 677                         flag = 1;
 678                 }
 679         }
 680
 681         return flag ? IRQ_HANDLED : IRQ_NONE;
 682 }
 683
 684 /**
 685  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
 686  * @i2c_adap:   Pointer to the struct i2c_adapter.
 687  * @msgs:       Pointer to i2c_msg structure.
 688  * @num:        number of messages.
 689  */
 690 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
 691                         struct i2c_msg *msgs, s32 num)
 692 {
 693         struct i2c_msg *pmsg;
 694         u32 i = 0;
 695         u32 status;
 696         s32 ret;
 697
 698         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 699
 700         ret = mutex_lock_interruptible(&pch_mutex);
 701         if (ret)
 702                 return -ERESTARTSYS;
 703
 704         if (adap->p_adapter_info->pch_i2c_suspended) {
 705                 mutex_unlock(&pch_mutex);
 706                 return -EBUSY;
 707         }
 708
 709         pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
 710                 adap->p_adapter_info->pch_i2c_suspended);
 711         /* transfer not completed */
 712         adap->pch_i2c_xfer_in_progress = true;
 713
 714         for (i = 0; i < num && ret >= 0; i++) {
 715                 pmsg = &msgs[i];
 716                 pmsg->flags |= adap->pch_buff_mode_en;
 717                 status = pmsg->flags;
 718                 pch_dbg(adap,
 719                         "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
 720
 721                 if ((status & (I2C_M_RD)) != false) {
 722                         ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
 723                                                 (i == 0));
 724                 } else {
 725                         ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
 726                                                  (i == 0));
 727                 }
 728         }
 729
 730         adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
 731
 732         mutex_unlock(&pch_mutex);
 733
 734         return (ret < 0) ? ret : num;
 735 }
 736
 737 /**
 738  * pch_i2c_func() - return the functionality of the I2C driver
 739  * @adap:       Pointer to struct i2c_algo_pch_data.
 740  */
 741 static u32 pch_i2c_func(struct i2c_adapter *adap)
 742 {
 743         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 744 }
 745
 746 static struct i2c_algorithm pch_algorithm = {
 747         .master_xfer = pch_i2c_xfer,
 748         .functionality = pch_i2c_func
 749 };
 750
 751 /**
 752  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
 753  * @adap:       Pointer to struct i2c_algo_pch_data.
 754  */
 755 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
 756 {
 757         void __iomem *p = adap->pch_base_address;
 758
 759         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
 760
 761         iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
 762
 763         iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
 764 }
 765
 766 static int __devinit pch_i2c_probe(struct pci_dev *pdev,
 767                                    const struct pci_device_id *id)
 768 {
 769         void __iomem *base_addr;
 770         int ret;
 771         int i, j;
 772         struct adapter_info *adap_info;
 773         struct i2c_adapter *pch_adap;
 774
 775         pch_pci_dbg(pdev, "Entered.\n");
 776
 777         adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
 778         if (adap_info == NULL) {
 779                 pch_pci_err(pdev, "Memory allocation FAILED\n");
 780                 return -ENOMEM;
 781         }
 782
 783         ret = pci_enable_device(pdev);
 784         if (ret) {
 785                 pch_pci_err(pdev, "pci_enable_device FAILED\n");
 786                 goto err_pci_enable;
 787         }
 788
 789         ret = pci_request_regions(pdev, KBUILD_MODNAME);
 790         if (ret) {
 791                 pch_pci_err(pdev, "pci_request_regions FAILED\n");
 792                 goto err_pci_req;
 793         }
 794
 795         base_addr = pci_iomap(pdev, 1, 0);
 796
 797         if (base_addr == NULL) {
 798                 pch_pci_err(pdev, "pci_iomap FAILED\n");
 799                 ret = -ENOMEM;
 800                 goto err_pci_iomap;
 801         }
 802
 803         /* Set the number of I2C channel instance */
 804         adap_info->ch_num = id->driver_data;
 805
 806         ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
 807                   KBUILD_MODNAME, adap_info);
 808         if (ret) {
 809                 pch_pci_err(pdev, "request_irq FAILED\n");
 810                 goto err_request_irq;
 811         }
 812
 813         for (i = 0; i < adap_info->ch_num; i++) {
 814                 pch_adap = &adap_info->pch_data[i].pch_adapter;
 815                 adap_info->pch_i2c_suspended = false;
 816
 817                 adap_info->pch_data[i].p_adapter_info = adap_info;
 818
 819                 pch_adap->owner = THIS_MODULE;
 820                 pch_adap->class = I2C_CLASS_HWMON;
 821                 strcpy(pch_adap->name, KBUILD_MODNAME);
 822                 pch_adap->algo = &pch_algorithm;
 823                 pch_adap->algo_data = &adap_info->pch_data[i];
 824
 825                 /* base_addr + offset; */
 826                 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
 827
 828                 pch_adap->dev.parent = &pdev->dev;
 829
 830                 pch_i2c_init(&adap_info->pch_data[i]);
 831
 832                 pch_adap->nr = i;
 833                 ret = i2c_add_numbered_adapter(pch_adap);
 834                 if (ret) {
 835                         pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
 836                         goto err_add_adapter;
 837                 }
 838         }
 839
 840         pci_set_drvdata(pdev, adap_info);
 841         pch_pci_dbg(pdev, "returns %d.\n", ret);
 842         return 0;
 843
 844 err_add_adapter:
 845         for (j = 0; j < i; j++)
 846                 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
 847         free_irq(pdev->irq, adap_info);
 848 err_request_irq:
 849         pci_iounmap(pdev, base_addr);
 850 err_pci_iomap:
 851         pci_release_regions(pdev);
 852 err_pci_req:
 853         pci_disable_device(pdev);
 854 err_pci_enable:
 855         kfree(adap_info);
 856         return ret;
 857 }
 858
 859 static void __devexit pch_i2c_remove(struct pci_dev *pdev)
 860 {
 861         int i;
 862         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 863
 864         free_irq(pdev->irq, adap_info);
 865
 866         for (i = 0; i < adap_info->ch_num; i++) {
 867                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 868                 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
 869         }
 870
 871         if (adap_info->pch_data[0].pch_base_address)
 872                 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
 873
 874         for (i = 0; i < adap_info->ch_num; i++)
 875                 adap_info->pch_data[i].pch_base_address = 0;
 876
 877         pci_set_drvdata(pdev, NULL);
 878
 879         pci_release_regions(pdev);
 880
 881         pci_disable_device(pdev);
 882         kfree(adap_info);
 883 }
 884
 885 #ifdef CONFIG_PM
 886 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
 887 {
 888         int ret;
 889         int i;
 890         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 891         void __iomem *p = adap_info->pch_data[0].pch_base_address;
 892
 893         adap_info->pch_i2c_suspended = true;
 894
 895         for (i = 0; i < adap_info->ch_num; i++) {
 896                 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
 897                         /* Wait until all channel transfers are completed */
 898                         msleep(20);
 899                 }
 900         }
 901
 902         /* Disable the i2c interrupts */
 903         for (i = 0; i < adap_info->ch_num; i++)
 904                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 905
 906         pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
 907                 "invoked function pch_i2c_disbl_int successfully\n",
 908                 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
 909                 ioread32(p + PCH_I2CESRSTA));
 910
 911         ret = pci_save_state(pdev);
 912
 913         if (ret) {
 914                 pch_pci_err(pdev, "pci_save_state\n");
 915                 return ret;
 916         }
 917
 918         pci_enable_wake(pdev, PCI_D3hot, 0);
 919         pci_disable_device(pdev);
 920         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 921
 922         return 0;
 923 }
 924
 925 static int pch_i2c_resume(struct pci_dev *pdev)
 926 {
 927         int i;
 928         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 929
 930         pci_set_power_state(pdev, PCI_D0);
 931         pci_restore_state(pdev);
 932
 933         if (pci_enable_device(pdev) < 0) {
 934                 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
 935                 return -EIO;
 936         }
 937
 938         pci_enable_wake(pdev, PCI_D3hot, 0);
 939
 940         for (i = 0; i < adap_info->ch_num; i++)
 941                 pch_i2c_init(&adap_info->pch_data[i]);
 942
 943         adap_info->pch_i2c_suspended = false;
 944
 945         return 0;
 946 }
 947 #else
 948 #define pch_i2c_suspend NULL
 949 #define pch_i2c_resume NULL
 950 #endif
 951
 952 static struct pci_driver pch_pcidriver = {
 953         .name = KBUILD_MODNAME,
 954         .id_table = pch_pcidev_id,
 955         .probe = pch_i2c_probe,
 956         .remove = __devexit_p(pch_i2c_remove),
 957         .suspend = pch_i2c_suspend,
 958         .resume = pch_i2c_resume
 959 };
 960
 961 static int __init pch_pci_init(void)
 962 {
 963         return pci_register_driver(&pch_pcidriver);
 964 }
 965 module_init(pch_pci_init);
 966
 967 static void __exit pch_pci_exit(void)
 968 {
 969         pci_unregister_driver(&pch_pcidriver);
 970 }
 971 module_exit(pch_pci_exit);
 972
 973 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
 974 MODULE_LICENSE("GPL");
 975 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
 976 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
 977 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));