2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 * Supports the following Intel I/O Controller Hubs (ICH):
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
63 * DNV (SOC) 0x19df 32 hard yes yes yes
64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
66 * Features supported by this driver:
70 * Block process call transaction no
71 * I2C block read transaction yes (doesn't use the block buffer)
73 * Interrupt processing yes
75 * See the file Documentation/i2c/busses/i2c-i801 for details.
78 #include <linux/interrupt.h>
79 #include <linux/module.h>
80 #include <linux/pci.h>
81 #include <linux/kernel.h>
82 #include <linux/stddef.h>
83 #include <linux/delay.h>
84 #include <linux/ioport.h>
85 #include <linux/init.h>
86 #include <linux/i2c.h>
87 #include <linux/acpi.h>
89 #include <linux/dmi.h>
90 #include <linux/slab.h>
91 #include <linux/wait.h>
92 #include <linux/err.h>
93 #include <linux/platform_device.h>
94 #include <linux/platform_data/itco_wdt.h>
96 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
98 #include <linux/gpio.h>
99 #include <linux/i2c-mux-gpio.h>
102 /* I801 SMBus address offsets */
103 #define SMBHSTSTS(p) (0 + (p)->smba)
104 #define SMBHSTCNT(p) (2 + (p)->smba)
105 #define SMBHSTCMD(p) (3 + (p)->smba)
106 #define SMBHSTADD(p) (4 + (p)->smba)
107 #define SMBHSTDAT0(p) (5 + (p)->smba)
108 #define SMBHSTDAT1(p) (6 + (p)->smba)
109 #define SMBBLKDAT(p) (7 + (p)->smba)
110 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
111 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
112 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
114 /* PCI Address Constants */
116 #define SMBPCICTL 0x004
117 #define SMBPCISTS 0x006
118 #define SMBHSTCFG 0x040
119 #define TCOBASE 0x050
122 #define ACPIBASE 0x040
123 #define ACPIBASE_SMI_OFF 0x030
124 #define ACPICTRL 0x044
125 #define ACPICTRL_EN 0x080
127 #define SBREG_BAR 0x10
128 #define SBREG_SMBCTRL 0xc6000c
130 /* Host status bits for SMBPCISTS */
131 #define SMBPCISTS_INTS 0x08
133 /* Control bits for SMBPCICTL */
134 #define SMBPCICTL_INTDIS 0x0400
136 /* Host configuration bits for SMBHSTCFG */
137 #define SMBHSTCFG_HST_EN 1
138 #define SMBHSTCFG_SMB_SMI_EN 2
139 #define SMBHSTCFG_I2C_EN 4
141 /* TCO configuration bits for TCOCTL */
142 #define TCOCTL_EN 0x0100
144 /* Auxiliary control register bits, ICH4+ only */
145 #define SMBAUXCTL_CRC 1
146 #define SMBAUXCTL_E32B 2
149 #define MAX_RETRIES 400
151 /* I801 command constants */
152 #define I801_QUICK 0x00
153 #define I801_BYTE 0x04
154 #define I801_BYTE_DATA 0x08
155 #define I801_WORD_DATA 0x0C
156 #define I801_PROC_CALL 0x10 /* unimplemented */
157 #define I801_BLOCK_DATA 0x14
158 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
160 /* I801 Host Control register bits */
161 #define SMBHSTCNT_INTREN 0x01
162 #define SMBHSTCNT_KILL 0x02
163 #define SMBHSTCNT_LAST_BYTE 0x20
164 #define SMBHSTCNT_START 0x40
165 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
167 /* I801 Hosts Status register bits */
168 #define SMBHSTSTS_BYTE_DONE 0x80
169 #define SMBHSTSTS_INUSE_STS 0x40
170 #define SMBHSTSTS_SMBALERT_STS 0x20
171 #define SMBHSTSTS_FAILED 0x10
172 #define SMBHSTSTS_BUS_ERR 0x08
173 #define SMBHSTSTS_DEV_ERR 0x04
174 #define SMBHSTSTS_INTR 0x02
175 #define SMBHSTSTS_HOST_BUSY 0x01
177 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
180 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
183 /* Older devices have their ID defined in <linux/pci_ids.h> */
184 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
185 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
186 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
187 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
188 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
189 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
190 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
191 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
192 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
193 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
194 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
195 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
196 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
197 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
198 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
199 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
200 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
201 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
202 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
203 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
204 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
205 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
206 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
207 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
208 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
210 struct i801_mux_config {
215 unsigned gpios[2]; /* Relative to gpio_chip->base */
220 struct i2c_adapter adapter;
222 unsigned char original_hstcfg;
223 struct pci_dev *pci_dev;
224 unsigned int features;
227 wait_queue_head_t waitq;
230 /* Command state used by isr for byte-by-byte block transactions */
237 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
239 const struct i801_mux_config *mux_drvdata;
240 struct platform_device *mux_pdev;
242 struct platform_device *tco_pdev;
245 #define FEATURE_SMBUS_PEC (1 << 0)
246 #define FEATURE_BLOCK_BUFFER (1 << 1)
247 #define FEATURE_BLOCK_PROC (1 << 2)
248 #define FEATURE_I2C_BLOCK_READ (1 << 3)
249 #define FEATURE_IRQ (1 << 4)
250 /* Not really a feature, but it's convenient to handle it as such */
251 #define FEATURE_IDF (1 << 15)
252 #define FEATURE_TCO (1 << 16)
254 static const char *i801_feature_names[] = {
257 "Block process call",
262 static unsigned int disable_features;
263 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
264 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
265 "\t\t 0x01 disable SMBus PEC\n"
266 "\t\t 0x02 disable the block buffer\n"
267 "\t\t 0x08 disable the I2C block read functionality\n"
268 "\t\t 0x10 don't use interrupts ");
270 /* Make sure the SMBus host is ready to start transmitting.
271 Return 0 if it is, -EBUSY if it is not. */
272 static int i801_check_pre(struct i801_priv *priv)
276 status = inb_p(SMBHSTSTS(priv));
277 if (status & SMBHSTSTS_HOST_BUSY) {
278 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
282 status &= STATUS_FLAGS;
284 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
286 outb_p(status, SMBHSTSTS(priv));
287 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
289 dev_err(&priv->pci_dev->dev,
290 "Failed clearing status flags (%02x)\n",
300 * Convert the status register to an error code, and clear it.
301 * Note that status only contains the bits we want to clear, not the
302 * actual register value.
304 static int i801_check_post(struct i801_priv *priv, int status)
309 * If the SMBus is still busy, we give up
310 * Note: This timeout condition only happens when using polling
311 * transactions. For interrupt operation, NAK/timeout is indicated by
314 if (unlikely(status < 0)) {
315 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
316 /* try to stop the current command */
317 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
318 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
320 usleep_range(1000, 2000);
321 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
324 /* Check if it worked */
325 status = inb_p(SMBHSTSTS(priv));
326 if ((status & SMBHSTSTS_HOST_BUSY) ||
327 !(status & SMBHSTSTS_FAILED))
328 dev_err(&priv->pci_dev->dev,
329 "Failed terminating the transaction\n");
330 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
334 if (status & SMBHSTSTS_FAILED) {
336 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
338 if (status & SMBHSTSTS_DEV_ERR) {
340 dev_dbg(&priv->pci_dev->dev, "No response\n");
342 if (status & SMBHSTSTS_BUS_ERR) {
344 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
347 /* Clear status flags except BYTE_DONE, to be cleared by caller */
348 outb_p(status, SMBHSTSTS(priv));
353 /* Wait for BUSY being cleared and either INTR or an error flag being set */
354 static int i801_wait_intr(struct i801_priv *priv)
359 /* We will always wait for a fraction of a second! */
361 usleep_range(250, 500);
362 status = inb_p(SMBHSTSTS(priv));
363 } while (((status & SMBHSTSTS_HOST_BUSY) ||
364 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
365 (timeout++ < MAX_RETRIES));
367 if (timeout > MAX_RETRIES) {
368 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
371 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
374 /* Wait for either BYTE_DONE or an error flag being set */
375 static int i801_wait_byte_done(struct i801_priv *priv)
380 /* We will always wait for a fraction of a second! */
382 usleep_range(250, 500);
383 status = inb_p(SMBHSTSTS(priv));
384 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
385 (timeout++ < MAX_RETRIES));
387 if (timeout > MAX_RETRIES) {
388 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
391 return status & STATUS_ERROR_FLAGS;
394 static int i801_transaction(struct i801_priv *priv, int xact)
398 const struct i2c_adapter *adap = &priv->adapter;
400 result = i801_check_pre(priv);
404 if (priv->features & FEATURE_IRQ) {
405 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
407 result = wait_event_timeout(priv->waitq,
408 (status = priv->status),
412 dev_warn(&priv->pci_dev->dev,
413 "Timeout waiting for interrupt!\n");
416 return i801_check_post(priv, status);
419 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
420 * SMBSCMD are passed in xact */
421 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
423 status = i801_wait_intr(priv);
424 return i801_check_post(priv, status);
427 static int i801_block_transaction_by_block(struct i801_priv *priv,
428 union i2c_smbus_data *data,
429 char read_write, int hwpec)
434 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
436 /* Use 32-byte buffer to process this transaction */
437 if (read_write == I2C_SMBUS_WRITE) {
438 len = data->block[0];
439 outb_p(len, SMBHSTDAT0(priv));
440 for (i = 0; i < len; i++)
441 outb_p(data->block[i+1], SMBBLKDAT(priv));
444 status = i801_transaction(priv, I801_BLOCK_DATA |
445 (hwpec ? SMBHSTCNT_PEC_EN : 0));
449 if (read_write == I2C_SMBUS_READ) {
450 len = inb_p(SMBHSTDAT0(priv));
451 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
454 data->block[0] = len;
455 for (i = 0; i < len; i++)
456 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
461 static void i801_isr_byte_done(struct i801_priv *priv)
464 /* For SMBus block reads, length is received with first byte */
465 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
466 (priv->count == 0)) {
467 priv->len = inb_p(SMBHSTDAT0(priv));
468 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
469 dev_err(&priv->pci_dev->dev,
470 "Illegal SMBus block read size %d\n",
473 priv->len = I2C_SMBUS_BLOCK_MAX;
475 dev_dbg(&priv->pci_dev->dev,
476 "SMBus block read size is %d\n",
479 priv->data[-1] = priv->len;
483 if (priv->count < priv->len)
484 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
486 dev_dbg(&priv->pci_dev->dev,
487 "Discarding extra byte on block read\n");
489 /* Set LAST_BYTE for last byte of read transaction */
490 if (priv->count == priv->len - 1)
491 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
493 } else if (priv->count < priv->len - 1) {
494 /* Write next byte, except for IRQ after last byte */
495 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
498 /* Clear BYTE_DONE to continue with next byte */
499 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
503 * There are two kinds of interrupts:
505 * 1) i801 signals transaction completion with one of these interrupts:
507 * DEV_ERR - Invalid command, NAK or communication timeout
508 * BUS_ERR - SMI# transaction collision
509 * FAILED - transaction was canceled due to a KILL request
510 * When any of these occur, update ->status and wake up the waitq.
511 * ->status must be cleared before kicking off the next transaction.
513 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
514 * occurs for each byte of a byte-by-byte to prepare the next byte.
516 static irqreturn_t i801_isr(int irq, void *dev_id)
518 struct i801_priv *priv = dev_id;
522 /* Confirm this is our interrupt */
523 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
524 if (!(pcists & SMBPCISTS_INTS))
527 status = inb_p(SMBHSTSTS(priv));
528 if (status & SMBHSTSTS_BYTE_DONE)
529 i801_isr_byte_done(priv);
532 * Clear irq sources and report transaction result.
533 * ->status must be cleared before the next transaction is started.
535 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
537 outb_p(status, SMBHSTSTS(priv));
538 priv->status |= status;
539 wake_up(&priv->waitq);
546 * For "byte-by-byte" block transactions:
547 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
548 * I2C read uses cmd=I801_I2C_BLOCK_DATA
550 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
551 union i2c_smbus_data *data,
552 char read_write, int command,
559 const struct i2c_adapter *adap = &priv->adapter;
561 result = i801_check_pre(priv);
565 len = data->block[0];
567 if (read_write == I2C_SMBUS_WRITE) {
568 outb_p(len, SMBHSTDAT0(priv));
569 outb_p(data->block[1], SMBBLKDAT(priv));
572 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
573 read_write == I2C_SMBUS_READ)
574 smbcmd = I801_I2C_BLOCK_DATA;
576 smbcmd = I801_BLOCK_DATA;
578 if (priv->features & FEATURE_IRQ) {
579 priv->is_read = (read_write == I2C_SMBUS_READ);
580 if (len == 1 && priv->is_read)
581 smbcmd |= SMBHSTCNT_LAST_BYTE;
582 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
585 priv->data = &data->block[1];
587 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
588 result = wait_event_timeout(priv->waitq,
589 (status = priv->status),
593 dev_warn(&priv->pci_dev->dev,
594 "Timeout waiting for interrupt!\n");
597 return i801_check_post(priv, status);
600 for (i = 1; i <= len; i++) {
601 if (i == len && read_write == I2C_SMBUS_READ)
602 smbcmd |= SMBHSTCNT_LAST_BYTE;
603 outb_p(smbcmd, SMBHSTCNT(priv));
606 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
609 status = i801_wait_byte_done(priv);
613 if (i == 1 && read_write == I2C_SMBUS_READ
614 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
615 len = inb_p(SMBHSTDAT0(priv));
616 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
617 dev_err(&priv->pci_dev->dev,
618 "Illegal SMBus block read size %d\n",
621 while (inb_p(SMBHSTSTS(priv)) &
623 outb_p(SMBHSTSTS_BYTE_DONE,
625 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
628 data->block[0] = len;
631 /* Retrieve/store value in SMBBLKDAT */
632 if (read_write == I2C_SMBUS_READ)
633 data->block[i] = inb_p(SMBBLKDAT(priv));
634 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
635 outb_p(data->block[i+1], SMBBLKDAT(priv));
637 /* signals SMBBLKDAT ready */
638 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
641 status = i801_wait_intr(priv);
643 return i801_check_post(priv, status);
646 static int i801_set_block_buffer_mode(struct i801_priv *priv)
648 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
649 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
654 /* Block transaction function */
655 static int i801_block_transaction(struct i801_priv *priv,
656 union i2c_smbus_data *data, char read_write,
657 int command, int hwpec)
662 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
663 if (read_write == I2C_SMBUS_WRITE) {
664 /* set I2C_EN bit in configuration register */
665 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
666 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
667 hostc | SMBHSTCFG_I2C_EN);
668 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
669 dev_err(&priv->pci_dev->dev,
670 "I2C block read is unsupported!\n");
675 if (read_write == I2C_SMBUS_WRITE
676 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
677 if (data->block[0] < 1)
679 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
680 data->block[0] = I2C_SMBUS_BLOCK_MAX;
682 data->block[0] = 32; /* max for SMBus block reads */
685 /* Experience has shown that the block buffer can only be used for
686 SMBus (not I2C) block transactions, even though the datasheet
687 doesn't mention this limitation. */
688 if ((priv->features & FEATURE_BLOCK_BUFFER)
689 && command != I2C_SMBUS_I2C_BLOCK_DATA
690 && i801_set_block_buffer_mode(priv) == 0)
691 result = i801_block_transaction_by_block(priv, data,
694 result = i801_block_transaction_byte_by_byte(priv, data,
698 if (command == I2C_SMBUS_I2C_BLOCK_DATA
699 && read_write == I2C_SMBUS_WRITE) {
700 /* restore saved configuration register value */
701 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
706 /* Return negative errno on error. */
707 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
708 unsigned short flags, char read_write, u8 command,
709 int size, union i2c_smbus_data *data)
714 struct i801_priv *priv = i2c_get_adapdata(adap);
716 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
717 && size != I2C_SMBUS_QUICK
718 && size != I2C_SMBUS_I2C_BLOCK_DATA;
721 case I2C_SMBUS_QUICK:
722 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
727 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
729 if (read_write == I2C_SMBUS_WRITE)
730 outb_p(command, SMBHSTCMD(priv));
733 case I2C_SMBUS_BYTE_DATA:
734 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
736 outb_p(command, SMBHSTCMD(priv));
737 if (read_write == I2C_SMBUS_WRITE)
738 outb_p(data->byte, SMBHSTDAT0(priv));
739 xact = I801_BYTE_DATA;
741 case I2C_SMBUS_WORD_DATA:
742 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
744 outb_p(command, SMBHSTCMD(priv));
745 if (read_write == I2C_SMBUS_WRITE) {
746 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
747 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
749 xact = I801_WORD_DATA;
751 case I2C_SMBUS_BLOCK_DATA:
752 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
754 outb_p(command, SMBHSTCMD(priv));
757 case I2C_SMBUS_I2C_BLOCK_DATA:
758 /* NB: page 240 of ICH5 datasheet shows that the R/#W
759 * bit should be cleared here, even when reading */
760 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
761 if (read_write == I2C_SMBUS_READ) {
762 /* NB: page 240 of ICH5 datasheet also shows
763 * that DATA1 is the cmd field when reading */
764 outb_p(command, SMBHSTDAT1(priv));
766 outb_p(command, SMBHSTCMD(priv));
770 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
775 if (hwpec) /* enable/disable hardware PEC */
776 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
778 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
782 ret = i801_block_transaction(priv, data, read_write, size,
785 ret = i801_transaction(priv, xact);
787 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
788 time, so we forcibly disable it after every transaction. Turn off
789 E32B for the same reason. */
791 outb_p(inb_p(SMBAUXCTL(priv)) &
792 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
798 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
801 switch (xact & 0x7f) {
802 case I801_BYTE: /* Result put in SMBHSTDAT0 */
804 data->byte = inb_p(SMBHSTDAT0(priv));
807 data->word = inb_p(SMBHSTDAT0(priv)) +
808 (inb_p(SMBHSTDAT1(priv)) << 8);
815 static u32 i801_func(struct i2c_adapter *adapter)
817 struct i801_priv *priv = i2c_get_adapdata(adapter);
819 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
820 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
821 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
822 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
823 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
824 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
827 static const struct i2c_algorithm smbus_algorithm = {
828 .smbus_xfer = i801_access,
829 .functionality = i801_func,
832 static const struct pci_device_id i801_ids[] = {
833 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
834 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
835 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
836 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
837 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
838 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
839 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
840 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
841 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
842 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
843 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
844 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
845 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
846 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
847 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
848 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
849 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
850 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
851 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
852 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
853 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
854 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
855 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
856 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
857 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
858 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
859 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
860 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
861 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
862 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
863 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
864 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
865 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
866 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
867 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
868 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
869 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
870 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
871 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
875 MODULE_DEVICE_TABLE(pci, i801_ids);
877 #if defined CONFIG_X86 && defined CONFIG_DMI
878 static unsigned char apanel_addr;
880 /* Scan the system ROM for the signature "FJKEYINF" */
881 static __init const void __iomem *bios_signature(const void __iomem *bios)
884 const unsigned char signature[] = "FJKEYINF";
886 for (offset = 0; offset < 0x10000; offset += 0x10) {
887 if (check_signature(bios + offset, signature,
888 sizeof(signature)-1))
889 return bios + offset;
894 static void __init input_apanel_init(void)
897 const void __iomem *p;
899 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
900 p = bios_signature(bios);
902 /* just use the first address */
903 apanel_addr = readb(p + 8 + 3) >> 1;
908 struct dmi_onboard_device_info {
911 unsigned short i2c_addr;
912 const char *i2c_type;
915 static const struct dmi_onboard_device_info dmi_devices[] = {
916 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
917 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
918 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
921 static void dmi_check_onboard_device(u8 type, const char *name,
922 struct i2c_adapter *adap)
925 struct i2c_board_info info;
927 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
928 /* & ~0x80, ignore enabled/disabled bit */
929 if ((type & ~0x80) != dmi_devices[i].type)
931 if (strcasecmp(name, dmi_devices[i].name))
934 memset(&info, 0, sizeof(struct i2c_board_info));
935 info.addr = dmi_devices[i].i2c_addr;
936 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
937 i2c_new_device(adap, &info);
942 /* We use our own function to check for onboard devices instead of
943 dmi_find_device() as some buggy BIOS's have the devices we are interested
944 in marked as disabled */
945 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
952 count = (dm->length - sizeof(struct dmi_header)) / 2;
953 for (i = 0; i < count; i++) {
954 const u8 *d = (char *)(dm + 1) + (i * 2);
955 const char *name = ((char *) dm) + dm->length;
962 while (s > 0 && name[0]) {
963 name += strlen(name) + 1;
966 if (name[0] == 0) /* Bogus string reference */
969 dmi_check_onboard_device(type, name, adap);
973 /* Register optional slaves */
974 static void i801_probe_optional_slaves(struct i801_priv *priv)
976 /* Only register slaves on main SMBus channel */
977 if (priv->features & FEATURE_IDF)
981 struct i2c_board_info info;
983 memset(&info, 0, sizeof(struct i2c_board_info));
984 info.addr = apanel_addr;
985 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
986 i2c_new_device(&priv->adapter, &info);
989 if (dmi_name_in_vendors("FUJITSU"))
990 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
993 static void __init input_apanel_init(void) {}
994 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
995 #endif /* CONFIG_X86 && CONFIG_DMI */
997 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
999 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1000 .gpio_chip = "gpio_ich",
1001 .values = { 0x02, 0x03 },
1003 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1004 .gpios = { 52, 53 },
1008 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1009 .gpio_chip = "gpio_ich",
1010 .values = { 0x02, 0x03, 0x01 },
1012 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1013 .gpios = { 52, 53 },
1017 static const struct dmi_system_id mux_dmi_table[] = {
1020 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1021 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1023 .driver_data = &i801_mux_config_asus_z8_d12,
1027 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1028 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1030 .driver_data = &i801_mux_config_asus_z8_d12,
1034 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1035 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1037 .driver_data = &i801_mux_config_asus_z8_d12,
1041 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1042 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1044 .driver_data = &i801_mux_config_asus_z8_d12,
1048 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1049 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1051 .driver_data = &i801_mux_config_asus_z8_d12,
1055 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1056 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1058 .driver_data = &i801_mux_config_asus_z8_d12,
1062 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1063 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1065 .driver_data = &i801_mux_config_asus_z8_d18,
1069 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1070 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1072 .driver_data = &i801_mux_config_asus_z8_d18,
1076 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1077 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1079 .driver_data = &i801_mux_config_asus_z8_d12,
1084 /* Setup multiplexing if needed */
1085 static int i801_add_mux(struct i801_priv *priv)
1087 struct device *dev = &priv->adapter.dev;
1088 const struct i801_mux_config *mux_config;
1089 struct i2c_mux_gpio_platform_data gpio_data;
1092 if (!priv->mux_drvdata)
1094 mux_config = priv->mux_drvdata;
1096 /* Prepare the platform data */
1097 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1098 gpio_data.parent = priv->adapter.nr;
1099 gpio_data.values = mux_config->values;
1100 gpio_data.n_values = mux_config->n_values;
1101 gpio_data.classes = mux_config->classes;
1102 gpio_data.gpio_chip = mux_config->gpio_chip;
1103 gpio_data.gpios = mux_config->gpios;
1104 gpio_data.n_gpios = mux_config->n_gpios;
1105 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1107 /* Register the mux device */
1108 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1109 PLATFORM_DEVID_AUTO, &gpio_data,
1110 sizeof(struct i2c_mux_gpio_platform_data));
1111 if (IS_ERR(priv->mux_pdev)) {
1112 err = PTR_ERR(priv->mux_pdev);
1113 priv->mux_pdev = NULL;
1114 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1121 static void i801_del_mux(struct i801_priv *priv)
1124 platform_device_unregister(priv->mux_pdev);
1127 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1129 const struct dmi_system_id *id;
1130 const struct i801_mux_config *mux_config;
1131 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1134 id = dmi_first_match(mux_dmi_table);
1136 /* Remove branch classes from trunk */
1137 mux_config = id->driver_data;
1138 for (i = 0; i < mux_config->n_values; i++)
1139 class &= ~mux_config->classes[i];
1141 /* Remember for later */
1142 priv->mux_drvdata = mux_config;
1148 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1149 static inline void i801_del_mux(struct i801_priv *priv) { }
1151 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1153 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1157 static const struct itco_wdt_platform_data tco_platform_data = {
1158 .name = "Intel PCH",
1162 static DEFINE_SPINLOCK(p2sb_spinlock);
1164 static void i801_add_tco(struct i801_priv *priv)
1166 struct pci_dev *pci_dev = priv->pci_dev;
1167 struct resource tco_res[3], *res;
1168 struct platform_device *pdev;
1170 u32 tco_base, tco_ctl;
1171 u32 base_addr, ctrl_val;
1174 if (!(priv->features & FEATURE_TCO))
1177 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1178 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1179 if (!(tco_ctl & TCOCTL_EN))
1182 memset(tco_res, 0, sizeof(tco_res));
1184 res = &tco_res[ICH_RES_IO_TCO];
1185 res->start = tco_base & ~1;
1186 res->end = res->start + 32 - 1;
1187 res->flags = IORESOURCE_IO;
1190 * Power Management registers.
1192 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1193 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1195 res = &tco_res[ICH_RES_IO_SMI];
1196 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1197 res->end = res->start + 3;
1198 res->flags = IORESOURCE_IO;
1201 * Enable the ACPI I/O space.
1203 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1204 ctrl_val |= ACPICTRL_EN;
1205 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1208 * We must access the NO_REBOOT bit over the Primary to Sideband
1209 * bridge (P2SB). The BIOS prevents the P2SB device from being
1210 * enumerated by the PCI subsystem, so we need to unhide/hide it
1211 * to lookup the P2SB BAR.
1213 spin_lock(&p2sb_spinlock);
1215 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1217 /* Unhide the P2SB device */
1218 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1220 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1221 base64_addr = base_addr & 0xfffffff0;
1223 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1224 base64_addr |= (u64)base_addr << 32;
1226 /* Hide the P2SB device */
1227 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1228 spin_unlock(&p2sb_spinlock);
1230 res = &tco_res[ICH_RES_MEM_OFF];
1231 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1232 res->end = res->start + 3;
1233 res->flags = IORESOURCE_MEM;
1235 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1236 tco_res, 3, &tco_platform_data,
1237 sizeof(tco_platform_data));
1239 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1243 priv->tco_pdev = pdev;
1246 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1250 struct i801_priv *priv;
1252 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1256 i2c_set_adapdata(&priv->adapter, priv);
1257 priv->adapter.owner = THIS_MODULE;
1258 priv->adapter.class = i801_get_adapter_class(priv);
1259 priv->adapter.algo = &smbus_algorithm;
1260 priv->adapter.dev.parent = &dev->dev;
1261 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1262 priv->adapter.retries = 3;
1264 priv->pci_dev = dev;
1265 switch (dev->device) {
1266 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1267 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1268 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1269 priv->features |= FEATURE_I2C_BLOCK_READ;
1270 priv->features |= FEATURE_IRQ;
1271 priv->features |= FEATURE_SMBUS_PEC;
1272 priv->features |= FEATURE_BLOCK_BUFFER;
1273 priv->features |= FEATURE_TCO;
1276 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1277 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1278 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1279 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1280 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1281 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1282 priv->features |= FEATURE_IDF;
1285 priv->features |= FEATURE_I2C_BLOCK_READ;
1286 priv->features |= FEATURE_IRQ;
1288 case PCI_DEVICE_ID_INTEL_82801DB_3:
1289 priv->features |= FEATURE_SMBUS_PEC;
1290 priv->features |= FEATURE_BLOCK_BUFFER;
1292 case PCI_DEVICE_ID_INTEL_82801CA_3:
1293 case PCI_DEVICE_ID_INTEL_82801BA_2:
1294 case PCI_DEVICE_ID_INTEL_82801AB_3:
1295 case PCI_DEVICE_ID_INTEL_82801AA_3:
1299 /* Disable features on user request */
1300 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1301 if (priv->features & disable_features & (1 << i))
1302 dev_notice(&dev->dev, "%s disabled by user\n",
1303 i801_feature_names[i]);
1305 priv->features &= ~disable_features;
1307 err = pcim_enable_device(dev);
1309 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1313 pcim_pin_device(dev);
1315 /* Determine the address of the SMBus area */
1316 priv->smba = pci_resource_start(dev, SMBBAR);
1319 "SMBus base address uninitialized, upgrade BIOS\n");
1323 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1328 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1329 dev_driver_string(&dev->dev));
1332 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1334 (unsigned long long)pci_resource_end(dev, SMBBAR));
1338 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1339 priv->original_hstcfg = temp;
1340 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1341 if (!(temp & SMBHSTCFG_HST_EN)) {
1342 dev_info(&dev->dev, "Enabling SMBus device\n");
1343 temp |= SMBHSTCFG_HST_EN;
1345 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1347 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1348 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1349 /* Disable SMBus interrupt feature if SMBus using SMI# */
1350 priv->features &= ~FEATURE_IRQ;
1353 /* Clear special mode bits */
1354 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1355 outb_p(inb_p(SMBAUXCTL(priv)) &
1356 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1358 /* Default timeout in interrupt mode: 200 ms */
1359 priv->adapter.timeout = HZ / 5;
1361 if (priv->features & FEATURE_IRQ) {
1364 /* Complain if an interrupt is already pending */
1365 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1366 if (pcists & SMBPCISTS_INTS)
1367 dev_warn(&dev->dev, "An interrupt is pending!\n");
1369 /* Check if interrupts have been disabled */
1370 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1371 if (pcictl & SMBPCICTL_INTDIS) {
1372 dev_info(&dev->dev, "Interrupts are disabled\n");
1373 priv->features &= ~FEATURE_IRQ;
1377 if (priv->features & FEATURE_IRQ) {
1378 init_waitqueue_head(&priv->waitq);
1380 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1382 dev_driver_string(&dev->dev), priv);
1384 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1386 priv->features &= ~FEATURE_IRQ;
1389 dev_info(&dev->dev, "SMBus using %s\n",
1390 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1394 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1395 "SMBus I801 adapter at %04lx", priv->smba);
1396 err = i2c_add_adapter(&priv->adapter);
1398 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1402 i801_probe_optional_slaves(priv);
1403 /* We ignore errors - multiplexing is optional */
1406 pci_set_drvdata(dev, priv);
1411 static void i801_remove(struct pci_dev *dev)
1413 struct i801_priv *priv = pci_get_drvdata(dev);
1416 i2c_del_adapter(&priv->adapter);
1417 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1419 platform_device_unregister(priv->tco_pdev);
1422 * do not call pci_disable_device(dev) since it can cause hard hangs on
1423 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1428 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1430 struct i801_priv *priv = pci_get_drvdata(dev);
1432 pci_save_state(dev);
1433 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1434 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1438 static int i801_resume(struct pci_dev *dev)
1440 pci_set_power_state(dev, PCI_D0);
1441 pci_restore_state(dev);
1445 #define i801_suspend NULL
1446 #define i801_resume NULL
1449 static struct pci_driver i801_driver = {
1450 .name = "i801_smbus",
1451 .id_table = i801_ids,
1452 .probe = i801_probe,
1453 .remove = i801_remove,
1454 .suspend = i801_suspend,
1455 .resume = i801_resume,
1458 static int __init i2c_i801_init(void)
1460 if (dmi_name_in_vendors("FUJITSU"))
1461 input_apanel_init();
1462 return pci_register_driver(&i801_driver);
1465 static void __exit i2c_i801_exit(void)
1467 pci_unregister_driver(&i801_driver);
1470 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1471 MODULE_DESCRIPTION("I801 SMBus driver");
1472 MODULE_LICENSE("GPL");
1474 module_init(i2c_i801_init);
1475 module_exit(i2c_i801_exit);