2 * Copyright (C) 2002 Motorola GSG-China
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 * Darius Augulis, Teltonika Inc.
18 * Implementation of I2C Adapter/Algorithm Driver
19 * for I2C Bus integrated in Freescale i.MX/MXC processors
21 * Derived from Motorola GSG China I2C example driver
23 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
24 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
25 * Copyright (C) 2007 RightHand Technologies, Inc.
26 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
28 * Copyright 2013 Freescale Semiconductor, Inc.
32 /** Includes *******************************************************************
33 *******************************************************************************/
35 #include <linux/clk.h>
36 #include <linux/completion.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/dmapool.h>
41 #include <linux/err.h>
42 #include <linux/errno.h>
43 #include <linux/i2c.h>
44 #include <linux/init.h>
45 #include <linux/interrupt.h>
47 #include <linux/kernel.h>
48 #include <linux/module.h>
50 #include <linux/of_device.h>
51 #include <linux/of_dma.h>
52 #include <linux/of_gpio.h>
53 #include <linux/platform_data/i2c-imx.h>
54 #include <linux/platform_device.h>
55 #include <linux/sched.h>
56 #include <linux/slab.h>
58 /** Defines ********************************************************************
59 *******************************************************************************/
61 /* This will be the driver name the kernel reports */
62 #define DRIVER_NAME "imx-i2c"
65 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
68 * Enable DMA if transfer byte size is bigger than this threshold.
69 * As the hardware request, it must bigger than 4 bytes.\
70 * I have set '16' here, maybe it's not the best but I think it's
73 #define DMA_THRESHOLD 16
74 #define DMA_TIMEOUT 1000
77 * the I2C register offset is different between SoCs,
78 * to provid support for all these chips, split the
79 * register offset into a fixed base address and a
80 * variable shift value, then the full register offset
81 * will be calculated by
82 * reg_off = ( reg_base_addr << reg_shift)
84 #define IMX_I2C_IADR 0x00 /* i2c slave address */
85 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
86 #define IMX_I2C_I2CR 0x02 /* i2c control */
87 #define IMX_I2C_I2SR 0x03 /* i2c status */
88 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
90 #define IMX_I2C_REGSHIFT 2
91 #define VF610_I2C_REGSHIFT 0
93 /* Bits of IMX I2C registers */
94 #define I2SR_RXAK 0x01
99 #define I2SR_IAAS 0x40
100 #define I2SR_ICF 0x80
101 #define I2CR_DMAEN 0x02
102 #define I2CR_RSTA 0x04
103 #define I2CR_TXAK 0x08
104 #define I2CR_MTX 0x10
105 #define I2CR_MSTA 0x20
106 #define I2CR_IIEN 0x40
107 #define I2CR_IEN 0x80
109 /* register bits different operating codes definition:
110 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
111 * - write zero to clear(w0c) INT flag on i.MX,
112 * - but write one to clear(w1c) INT flag on Vybrid.
113 * 2) I2CR: I2C module enable operation also differ between SoCs:
114 * - set I2CR_IEN bit enable the module on i.MX,
115 * - but clear I2CR_IEN bit enable the module on Vybrid.
117 #define I2SR_CLR_OPCODE_W0C 0x0
118 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
119 #define I2CR_IEN_OPCODE_0 0x0
120 #define I2CR_IEN_OPCODE_1 I2CR_IEN
122 /** Variables ******************************************************************
123 *******************************************************************************/
126 * sorted list of clock divider, register value pairs
127 * taken from table 26-5, p.26-9, Freescale i.MX
128 * Integrated Portable System Processor Reference Manual
129 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
131 * Duplicated divider values removed from list
133 struct imx_i2c_clk_pair {
138 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
139 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
140 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
141 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
142 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
143 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
144 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
145 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
146 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
147 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
148 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
149 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
150 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
151 { 3072, 0x1E }, { 3840, 0x1F }
154 /* Vybrid VF610 clock divider, register value pairs */
155 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
156 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
157 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
158 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
159 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
160 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
161 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
162 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
163 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
164 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
165 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
166 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
167 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
168 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
169 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
170 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
179 struct imx_i2c_hwdata {
180 enum imx_i2c_type devtype;
182 struct imx_i2c_clk_pair *clk_div;
184 unsigned i2sr_clr_opcode;
185 unsigned i2cr_ien_opcode;
189 struct dma_chan *chan_tx;
190 struct dma_chan *chan_rx;
191 struct dma_chan *chan_using;
192 struct completion cmd_complete;
194 unsigned int dma_len;
195 enum dma_transfer_direction dma_transfer_dir;
196 enum dma_data_direction dma_data_dir;
199 struct imx_i2c_struct {
200 struct i2c_adapter adapter;
203 wait_queue_head_t queue;
205 unsigned int disable_delay;
207 unsigned int ifdr; /* IMX_I2C_IFDR */
208 unsigned int cur_clk;
209 unsigned int bitrate;
210 const struct imx_i2c_hwdata *hwdata;
211 struct i2c_bus_recovery_info rinfo;
213 struct pinctrl *pinctrl;
214 struct pinctrl_state *pinctrl_pins_default;
215 struct pinctrl_state *pinctrl_pins_gpio;
217 struct imx_i2c_dma *dma;
220 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
222 .regshift = IMX_I2C_REGSHIFT,
223 .clk_div = imx_i2c_clk_div,
224 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
225 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
226 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
230 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
231 .devtype = IMX21_I2C,
232 .regshift = IMX_I2C_REGSHIFT,
233 .clk_div = imx_i2c_clk_div,
234 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
235 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
236 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
240 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
241 .devtype = VF610_I2C,
242 .regshift = VF610_I2C_REGSHIFT,
243 .clk_div = vf610_i2c_clk_div,
244 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
245 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
246 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
250 static const struct platform_device_id imx_i2c_devtype[] = {
253 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
256 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
261 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
263 static const struct of_device_id i2c_imx_dt_ids[] = {
264 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
265 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
266 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
269 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
271 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
273 return i2c_imx->hwdata->devtype == IMX1_I2C;
276 static inline void imx_i2c_write_reg(unsigned int val,
277 struct imx_i2c_struct *i2c_imx, unsigned int reg)
279 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
282 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
285 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
288 /* Functions for DMA support */
289 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
292 struct imx_i2c_dma *dma;
293 struct dma_slave_config dma_sconfig;
294 struct device *dev = &i2c_imx->adapter.dev;
297 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
301 dma->chan_tx = dma_request_slave_channel(dev, "tx");
303 dev_dbg(dev, "can't request DMA tx channel\n");
307 dma_sconfig.dst_addr = phy_addr +
308 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
309 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
310 dma_sconfig.dst_maxburst = 1;
311 dma_sconfig.direction = DMA_MEM_TO_DEV;
312 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
314 dev_dbg(dev, "can't configure tx channel\n");
318 dma->chan_rx = dma_request_slave_channel(dev, "rx");
320 dev_dbg(dev, "can't request DMA rx channel\n");
324 dma_sconfig.src_addr = phy_addr +
325 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
326 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
327 dma_sconfig.src_maxburst = 1;
328 dma_sconfig.direction = DMA_DEV_TO_MEM;
329 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
331 dev_dbg(dev, "can't configure rx channel\n");
336 init_completion(&dma->cmd_complete);
337 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
338 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
343 dma_release_channel(dma->chan_rx);
345 dma_release_channel(dma->chan_tx);
347 devm_kfree(dev, dma);
348 dev_info(dev, "can't use DMA\n");
351 static void i2c_imx_dma_callback(void *arg)
353 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
354 struct imx_i2c_dma *dma = i2c_imx->dma;
356 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
357 dma->dma_len, dma->dma_data_dir);
358 complete(&dma->cmd_complete);
361 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
362 struct i2c_msg *msgs)
364 struct imx_i2c_dma *dma = i2c_imx->dma;
365 struct dma_async_tx_descriptor *txdesc;
366 struct device *dev = &i2c_imx->adapter.dev;
367 struct device *chan_dev = dma->chan_using->device->dev;
369 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
370 dma->dma_len, dma->dma_data_dir);
371 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
372 dev_err(dev, "DMA mapping failed\n");
376 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
377 dma->dma_len, dma->dma_transfer_dir,
378 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
380 dev_err(dev, "Not able to get desc for DMA xfer\n");
384 txdesc->callback = i2c_imx_dma_callback;
385 txdesc->callback_param = i2c_imx;
386 if (dma_submit_error(dmaengine_submit(txdesc))) {
387 dev_err(dev, "DMA submit failed\n");
391 dma_async_issue_pending(dma->chan_using);
396 dma_unmap_single(chan_dev, dma->dma_buf,
397 dma->dma_len, dma->dma_data_dir);
402 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
404 struct imx_i2c_dma *dma = i2c_imx->dma;
409 dma_release_channel(dma->chan_tx);
412 dma_release_channel(dma->chan_rx);
415 dma->chan_using = NULL;
418 /** Functions for IMX I2C adapter driver ***************************************
419 *******************************************************************************/
421 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
423 unsigned long orig_jiffies = jiffies;
426 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
429 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
431 /* check for arbitration lost */
432 if (temp & I2SR_IAL) {
434 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
438 if (for_busy && (temp & I2SR_IBB))
440 if (!for_busy && !(temp & I2SR_IBB))
442 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
443 dev_dbg(&i2c_imx->adapter.dev,
444 "<%s> I2C bus is busy\n", __func__);
453 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
455 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
457 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
458 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
461 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
466 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
468 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
469 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
470 return -ENXIO; /* No ACK */
473 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
477 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
479 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
480 unsigned int i2c_clk_rate;
484 /* Divider value calculation */
485 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
486 if (i2c_imx->cur_clk == i2c_clk_rate)
489 i2c_imx->cur_clk = i2c_clk_rate;
491 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
492 if (div < i2c_clk_div[0].div)
494 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
495 i = i2c_imx->hwdata->ndivs - 1;
497 for (i = 0; i2c_clk_div[i].div < div; i++)
500 /* Store divider value */
501 i2c_imx->ifdr = i2c_clk_div[i].val;
504 * There dummy delay is calculated.
505 * It should be about one I2C clock period long.
506 * This delay is used in I2C bus disable function
507 * to fix chip hardware bug.
509 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
510 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
512 #ifdef CONFIG_I2C_DEBUG_BUS
513 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
515 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
516 i2c_clk_div[i].val, i2c_clk_div[i].div);
520 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
522 unsigned int temp = 0;
525 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
527 i2c_imx_set_clk(i2c_imx);
529 result = clk_prepare_enable(i2c_imx->clk);
532 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
533 /* Enable I2C controller */
534 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
535 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
537 /* Wait controller to be stable */
540 /* Start I2C transaction */
541 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
543 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
544 result = i2c_imx_bus_busy(i2c_imx, 1);
547 i2c_imx->stopped = 0;
549 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
551 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
555 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
557 unsigned int temp = 0;
559 if (!i2c_imx->stopped) {
560 /* Stop I2C transaction */
561 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
562 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
563 temp &= ~(I2CR_MSTA | I2CR_MTX);
566 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
568 if (is_imx1_i2c(i2c_imx)) {
570 * This delay caused by an i.MXL hardware bug.
571 * If no (or too short) delay, no "STOP" bit will be generated.
573 udelay(i2c_imx->disable_delay);
576 if (!i2c_imx->stopped) {
577 i2c_imx_bus_busy(i2c_imx, 0);
578 i2c_imx->stopped = 1;
581 /* Disable I2C controller */
582 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
583 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
584 clk_disable_unprepare(i2c_imx->clk);
587 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
589 struct imx_i2c_struct *i2c_imx = dev_id;
592 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
593 if (temp & I2SR_IIF) {
594 /* save status register */
595 i2c_imx->i2csr = temp;
597 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
598 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
599 wake_up(&i2c_imx->queue);
606 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
607 struct i2c_msg *msgs)
610 unsigned long time_left;
611 unsigned int temp = 0;
612 unsigned long orig_jiffies = jiffies;
613 struct imx_i2c_dma *dma = i2c_imx->dma;
614 struct device *dev = &i2c_imx->adapter.dev;
616 dma->chan_using = dma->chan_tx;
617 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
618 dma->dma_data_dir = DMA_TO_DEVICE;
619 dma->dma_len = msgs->len - 1;
620 result = i2c_imx_dma_xfer(i2c_imx, msgs);
624 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
626 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
629 * Write slave address.
630 * The first byte must be transmitted by the CPU.
632 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
633 reinit_completion(&i2c_imx->dma->cmd_complete);
634 time_left = wait_for_completion_timeout(
635 &i2c_imx->dma->cmd_complete,
636 msecs_to_jiffies(DMA_TIMEOUT));
637 if (time_left == 0) {
638 dmaengine_terminate_all(dma->chan_using);
642 /* Waiting for transfer complete. */
644 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
647 if (time_after(jiffies, orig_jiffies +
648 msecs_to_jiffies(DMA_TIMEOUT))) {
649 dev_dbg(dev, "<%s> Timeout\n", __func__);
655 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
657 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
659 /* The last data byte must be transferred by the CPU. */
660 imx_i2c_write_reg(msgs->buf[msgs->len-1],
661 i2c_imx, IMX_I2C_I2DR);
662 result = i2c_imx_trx_complete(i2c_imx);
666 return i2c_imx_acked(i2c_imx);
669 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
670 struct i2c_msg *msgs, bool is_lastmsg)
673 unsigned long time_left;
675 unsigned long orig_jiffies = jiffies;
676 struct imx_i2c_dma *dma = i2c_imx->dma;
677 struct device *dev = &i2c_imx->adapter.dev;
679 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
681 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
683 dma->chan_using = dma->chan_rx;
684 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
685 dma->dma_data_dir = DMA_FROM_DEVICE;
686 /* The last two data bytes must be transferred by the CPU. */
687 dma->dma_len = msgs->len - 2;
688 result = i2c_imx_dma_xfer(i2c_imx, msgs);
692 reinit_completion(&i2c_imx->dma->cmd_complete);
693 time_left = wait_for_completion_timeout(
694 &i2c_imx->dma->cmd_complete,
695 msecs_to_jiffies(DMA_TIMEOUT));
696 if (time_left == 0) {
697 dmaengine_terminate_all(dma->chan_using);
701 /* waiting for transfer complete. */
703 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
706 if (time_after(jiffies, orig_jiffies +
707 msecs_to_jiffies(DMA_TIMEOUT))) {
708 dev_dbg(dev, "<%s> Timeout\n", __func__);
714 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
716 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
718 /* read n-1 byte data */
719 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
721 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
723 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
724 /* read n byte data */
725 result = i2c_imx_trx_complete(i2c_imx);
731 * It must generate STOP before read I2DR to prevent
732 * controller from generating another clock cycle
734 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
735 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
736 temp &= ~(I2CR_MSTA | I2CR_MTX);
737 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
738 i2c_imx_bus_busy(i2c_imx, 0);
739 i2c_imx->stopped = 1;
742 * For i2c master receiver repeat restart operation like:
743 * read -> repeat MSTA -> read/write
744 * The controller must set MTX before read the last byte in
745 * the first read operation, otherwise the first read cost
746 * one extra clock cycle.
748 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
750 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
752 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
757 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
761 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
762 __func__, msgs->addr << 1);
764 /* write slave address */
765 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
766 result = i2c_imx_trx_complete(i2c_imx);
769 result = i2c_imx_acked(i2c_imx);
772 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
775 for (i = 0; i < msgs->len; i++) {
776 dev_dbg(&i2c_imx->adapter.dev,
777 "<%s> write byte: B%d=0x%X\n",
778 __func__, i, msgs->buf[i]);
779 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
780 result = i2c_imx_trx_complete(i2c_imx);
783 result = i2c_imx_acked(i2c_imx);
790 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
794 int block_data = msgs->flags & I2C_M_RECV_LEN;
796 dev_dbg(&i2c_imx->adapter.dev,
797 "<%s> write slave address: addr=0x%x\n",
798 __func__, (msgs->addr << 1) | 0x01);
800 /* write slave address */
801 imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
802 result = i2c_imx_trx_complete(i2c_imx);
805 result = i2c_imx_acked(i2c_imx);
809 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
811 /* setup bus to read data */
812 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
816 * Reset the I2CR_TXAK flag initially for SMBus block read since the
819 if ((msgs->len - 1) || block_data)
821 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
822 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
824 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
826 if (i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data)
827 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
830 for (i = 0; i < msgs->len; i++) {
833 result = i2c_imx_trx_complete(i2c_imx);
837 * First byte is the length of remaining packet
838 * in the SMBus block data read. Add it to
841 if ((!i) && block_data) {
842 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
843 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
845 dev_dbg(&i2c_imx->adapter.dev,
846 "<%s> read length: 0x%X\n",
850 if (i == (msgs->len - 1)) {
853 * It must generate STOP before read I2DR to prevent
854 * controller from generating another clock cycle
856 dev_dbg(&i2c_imx->adapter.dev,
857 "<%s> clear MSTA\n", __func__);
858 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
859 temp &= ~(I2CR_MSTA | I2CR_MTX);
860 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
861 i2c_imx_bus_busy(i2c_imx, 0);
862 i2c_imx->stopped = 1;
865 * For i2c master receiver repeat restart operation like:
866 * read -> repeat MSTA -> read/write
867 * The controller must set MTX before read the last byte in
868 * the first read operation, otherwise the first read cost
869 * one extra clock cycle.
871 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
873 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
875 } else if (i == (msgs->len - 2)) {
876 dev_dbg(&i2c_imx->adapter.dev,
877 "<%s> set TXAK\n", __func__);
878 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
880 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
882 if ((!i) && block_data)
885 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
886 dev_dbg(&i2c_imx->adapter.dev,
887 "<%s> read byte: B%d=0x%X\n",
888 __func__, i, msgs->buf[i]);
893 static int i2c_imx_xfer(struct i2c_adapter *adapter,
894 struct i2c_msg *msgs, int num)
896 unsigned int i, temp;
898 bool is_lastmsg = false;
899 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
901 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
903 /* Start I2C transfer */
904 result = i2c_imx_start(i2c_imx);
906 if (i2c_imx->adapter.bus_recovery_info) {
907 i2c_recover_bus(&i2c_imx->adapter);
908 result = i2c_imx_start(i2c_imx);
915 /* read/write data */
916 for (i = 0; i < num; i++) {
921 dev_dbg(&i2c_imx->adapter.dev,
922 "<%s> repeated start\n", __func__);
923 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
925 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
926 result = i2c_imx_bus_busy(i2c_imx, 1);
930 dev_dbg(&i2c_imx->adapter.dev,
931 "<%s> transfer message: %d\n", __func__, i);
932 /* write/read data */
933 #ifdef CONFIG_I2C_DEBUG_BUS
934 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
935 dev_dbg(&i2c_imx->adapter.dev,
936 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
938 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
939 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
940 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
941 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
942 dev_dbg(&i2c_imx->adapter.dev,
943 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
945 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
946 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
947 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
948 (temp & I2SR_RXAK ? 1 : 0));
950 if (msgs[i].flags & I2C_M_RD)
951 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
953 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
954 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
956 result = i2c_imx_write(i2c_imx, &msgs[i]);
963 /* Stop I2C transfer */
964 i2c_imx_stop(i2c_imx);
966 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
967 (result < 0) ? "error" : "success msg",
968 (result < 0) ? result : num);
969 return (result < 0) ? result : num;
972 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
974 struct imx_i2c_struct *i2c_imx;
976 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
978 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
981 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
983 struct imx_i2c_struct *i2c_imx;
985 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
987 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
990 static void i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
991 struct platform_device *pdev)
993 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
995 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
996 PINCTRL_STATE_DEFAULT);
997 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
999 rinfo->sda_gpio = of_get_named_gpio_flags(pdev->dev.of_node,
1000 "sda-gpios", 0, NULL);
1001 rinfo->scl_gpio = of_get_named_gpio_flags(pdev->dev.of_node,
1002 "scl-gpios", 0, NULL);
1004 if (!gpio_is_valid(rinfo->sda_gpio) ||
1005 !gpio_is_valid(rinfo->scl_gpio) ||
1006 IS_ERR(i2c_imx->pinctrl_pins_default) ||
1007 IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1008 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1012 dev_dbg(&pdev->dev, "using scl-gpio %d and sda-gpio %d for recovery\n",
1013 rinfo->sda_gpio, rinfo->scl_gpio);
1015 rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1016 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1017 rinfo->recover_bus = i2c_generic_gpio_recovery;
1018 i2c_imx->adapter.bus_recovery_info = rinfo;
1021 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1023 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1024 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1027 static struct i2c_algorithm i2c_imx_algo = {
1028 .master_xfer = i2c_imx_xfer,
1029 .functionality = i2c_imx_func,
1032 static int i2c_imx_probe(struct platform_device *pdev)
1034 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
1036 struct imx_i2c_struct *i2c_imx;
1037 struct resource *res;
1038 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1041 dma_addr_t phy_addr;
1043 dev_dbg(&pdev->dev, "<%s>\n", __func__);
1045 irq = platform_get_irq(pdev, 0);
1047 dev_err(&pdev->dev, "can't get irq number\n");
1051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1052 base = devm_ioremap_resource(&pdev->dev, res);
1054 return PTR_ERR(base);
1056 phy_addr = (dma_addr_t)res->start;
1057 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1062 i2c_imx->hwdata = of_id->data;
1064 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1065 platform_get_device_id(pdev)->driver_data;
1067 /* Setup i2c_imx driver structure */
1068 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1069 i2c_imx->adapter.owner = THIS_MODULE;
1070 i2c_imx->adapter.algo = &i2c_imx_algo;
1071 i2c_imx->adapter.dev.parent = &pdev->dev;
1072 i2c_imx->adapter.nr = pdev->id;
1073 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1074 i2c_imx->base = base;
1077 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1078 if (IS_ERR(i2c_imx->clk)) {
1079 dev_err(&pdev->dev, "can't get I2C clock\n");
1080 return PTR_ERR(i2c_imx->clk);
1083 ret = clk_prepare_enable(i2c_imx->clk);
1085 dev_err(&pdev->dev, "can't enable I2C clock\n");
1089 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1090 if (IS_ERR(i2c_imx->pinctrl)) {
1091 ret = PTR_ERR(i2c_imx->pinctrl);
1096 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
1097 pdev->name, i2c_imx);
1099 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1104 init_waitqueue_head(&i2c_imx->queue);
1106 /* Set up adapter data */
1107 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1109 /* Set up clock divider */
1110 i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1111 ret = of_property_read_u32(pdev->dev.of_node,
1112 "clock-frequency", &i2c_imx->bitrate);
1113 if (ret < 0 && pdata && pdata->bitrate)
1114 i2c_imx->bitrate = pdata->bitrate;
1116 /* Set up chip registers to defaults */
1117 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1118 i2c_imx, IMX_I2C_I2CR);
1119 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1121 /* Add I2C adapter */
1122 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1124 dev_err(&pdev->dev, "registration failed\n");
1128 i2c_imx_init_recovery_info(i2c_imx, pdev);
1130 /* Set up platform driver data */
1131 platform_set_drvdata(pdev, i2c_imx);
1132 clk_disable_unprepare(i2c_imx->clk);
1134 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1135 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1136 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1137 i2c_imx->adapter.name);
1138 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1140 /* Init DMA config if supported */
1141 i2c_imx_dma_request(i2c_imx, phy_addr);
1143 return 0; /* Return OK */
1146 clk_disable_unprepare(i2c_imx->clk);
1150 static int i2c_imx_remove(struct platform_device *pdev)
1152 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1154 /* remove adapter */
1155 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1156 i2c_del_adapter(&i2c_imx->adapter);
1159 i2c_imx_dma_free(i2c_imx);
1161 /* setup chip registers to defaults */
1162 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1163 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1164 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1165 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1170 static struct platform_driver i2c_imx_driver = {
1171 .probe = i2c_imx_probe,
1172 .remove = i2c_imx_remove,
1174 .name = DRIVER_NAME,
1175 .of_match_table = i2c_imx_dt_ids,
1177 .id_table = imx_i2c_devtype,
1180 static int __init i2c_adap_imx_init(void)
1182 return platform_driver_register(&i2c_imx_driver);
1184 subsys_initcall(i2c_adap_imx_init);
1186 static void __exit i2c_adap_imx_exit(void)
1188 platform_driver_unregister(&i2c_imx_driver);
1190 module_exit(i2c_adap_imx_exit);
1192 MODULE_LICENSE("GPL");
1193 MODULE_AUTHOR("Darius Augulis");
1194 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1195 MODULE_ALIAS("platform:" DRIVER_NAME);