1 /* ------------------------------------------------------------------------- */
2 /* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
3 /* ------------------------------------------------------------------------- */
4 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
5 * <Peter dot Milne at D hyphen TACQ dot com>
7 * With acknowledgements to i2c-algo-ibm_ocp.c by
8 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
10 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
17 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
19 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
20 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
21 * - Make it work with IXP46x chips
22 * - Cleanup function names, coding style, etc
24 * - writing to slave address causes latchup on iop331.
25 * fix: driver refuses to address self.
27 * This program is free software; you can redistribute it and/or modify
28 * it under the terms of the GNU General Public License as published by
29 * the Free Software Foundation, version 2.
32 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/platform_device.h>
39 #include <linux/i2c.h>
41 #include <linux/gpio.h>
43 #include "i2c-iop3xx.h"
45 /* global unit counter */
48 static inline unsigned char
49 iic_cook_addr(struct i2c_msg *msg)
53 addr = (msg->addr << 1);
55 if (msg->flags & I2C_M_RD)
62 iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
64 /* Follows devman 9.3 */
65 __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
66 __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
67 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
71 iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
73 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
76 * Every time unit enable is asserted, GPOD needs to be cleared
77 * on IOP3XX to avoid data corruption on the bus.
79 #if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
80 if (iop3xx_adap->id == 0) {
88 /* NB SR bits not same position as CR IE bits :-( */
89 iop3xx_adap->SR_enabled =
90 IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
91 IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
93 cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
94 IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;
96 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
100 iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
102 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
104 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
105 IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
107 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
111 * NB: the handler has to clear the source of the interrupt!
112 * Then it passes the SR flags of interest to BH via adap data
115 iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
117 struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
118 u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
120 if ((sr &= iop3xx_adap->SR_enabled)) {
121 __raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
122 iop3xx_adap->SR_received |= sr;
123 wake_up_interruptible(&iop3xx_adap->waitq);
128 /* check all error conditions, clear them , report most important */
130 iop3xx_i2c_error(u32 sr)
134 if ((sr & IOP3XX_ISR_BERRD)) {
135 if ( !rc ) rc = -I2C_ERR_BERR;
137 if ((sr & IOP3XX_ISR_ALD)) {
138 if ( !rc ) rc = -I2C_ERR_ALD;
144 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
149 spin_lock_irqsave(&iop3xx_adap->lock, flags);
150 sr = iop3xx_adap->SR_received;
151 iop3xx_adap->SR_received = 0;
152 spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
158 * sleep until interrupted, then recover and analyse the SR
161 typedef int (* compare_func)(unsigned test, unsigned mask);
162 /* returns 1 on correct comparison */
165 iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
166 unsigned flags, unsigned* status,
167 compare_func compare)
175 interrupted = wait_event_interruptible_timeout (
177 (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
180 if ((rc = iop3xx_i2c_error(sr)) < 0) {
183 } else if (!interrupted) {
195 * Concrete compare_funcs
198 all_bits_clear(unsigned test, unsigned mask)
200 return (test & mask) == 0;
204 any_bits_set(unsigned test, unsigned mask)
206 return (test & mask) != 0;
210 iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
212 return iop3xx_i2c_wait_event(
214 IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
215 status, any_bits_set);
219 iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
221 return iop3xx_i2c_wait_event(
223 IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
224 status, any_bits_set);
228 iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
230 return iop3xx_i2c_wait_event(
231 iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
235 iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
238 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
242 /* avoid writing to my slave address (hangs on 80331),
243 * forbidden in Intel developer manual
245 if (msg->addr == MYSAR) {
249 __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
251 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
252 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
254 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
255 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
261 iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
264 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
268 __raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
269 cr &= ~IOP3XX_ICR_MSTART;
271 cr |= IOP3XX_ICR_MSTOP;
273 cr &= ~IOP3XX_ICR_MSTOP;
275 cr |= IOP3XX_ICR_TBYTE;
276 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
277 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
283 iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
286 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
290 cr &= ~IOP3XX_ICR_MSTART;
293 cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
295 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
297 cr |= IOP3XX_ICR_TBYTE;
298 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
300 rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
302 *byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
308 iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
310 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
314 for (ii = 0; rc == 0 && ii != count; ++ii)
315 rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
320 iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
322 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
326 for (ii = 0; rc == 0 && ii != count; ++ii)
327 rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
333 * Description: This function implements combined transactions. Combined
334 * transactions consist of combinations of reading and writing blocks of data.
335 * FROM THE SAME ADDRESS
336 * Each transfer (i.e. a read or a write) is separated by a repeated start
340 iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
342 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
345 rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
350 if ((pmsg->flags&I2C_M_RD)) {
351 return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
353 return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
358 * master_xfer() - main read/write entry
361 iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
364 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
369 iop3xx_i2c_wait_idle(iop3xx_adap, &status);
370 iop3xx_i2c_reset(iop3xx_adap);
371 iop3xx_i2c_enable(iop3xx_adap);
373 for (im = 0; ret == 0 && im != num; im++) {
374 ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
377 iop3xx_i2c_transaction_cleanup(iop3xx_adap);
386 iop3xx_i2c_func(struct i2c_adapter *adap)
388 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
391 static const struct i2c_algorithm iop3xx_i2c_algo = {
392 .master_xfer = iop3xx_i2c_master_xfer,
393 .functionality = iop3xx_i2c_func,
397 iop3xx_i2c_remove(struct platform_device *pdev)
399 struct i2c_adapter *padapter = platform_get_drvdata(pdev);
400 struct i2c_algo_iop3xx_data *adapter_data =
401 (struct i2c_algo_iop3xx_data *)padapter->algo_data;
402 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
403 unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
406 * Disable the actual HW unit
408 cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
409 IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
410 __raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
412 iounmap(adapter_data->ioaddr);
413 release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
421 iop3xx_i2c_probe(struct platform_device *pdev)
423 struct resource *res;
425 struct i2c_adapter *new_adapter;
426 struct i2c_algo_iop3xx_data *adapter_data;
428 new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
434 adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
440 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
446 if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
451 /* set the adapter enumeration # */
452 adapter_data->id = i2c_id++;
454 adapter_data->ioaddr = ioremap(res->start, IOP3XX_I2C_IO_SIZE);
455 if (!adapter_data->ioaddr) {
460 irq = platform_get_irq(pdev, 0);
465 ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
466 pdev->name, adapter_data);
473 memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
474 new_adapter->owner = THIS_MODULE;
475 new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
476 new_adapter->dev.parent = &pdev->dev;
477 new_adapter->nr = pdev->id;
480 * Default values...should these come in from board code?
482 new_adapter->timeout = HZ;
483 new_adapter->algo = &iop3xx_i2c_algo;
485 init_waitqueue_head(&adapter_data->waitq);
486 spin_lock_init(&adapter_data->lock);
488 iop3xx_i2c_reset(adapter_data);
489 iop3xx_i2c_enable(adapter_data);
491 platform_set_drvdata(pdev, new_adapter);
492 new_adapter->algo_data = adapter_data;
494 i2c_add_numbered_adapter(new_adapter);
499 iounmap(adapter_data->ioaddr);
502 release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
515 static struct platform_driver iop3xx_i2c_driver = {
516 .probe = iop3xx_i2c_probe,
517 .remove = iop3xx_i2c_remove,
519 .name = "IOP3xx-I2C",
523 module_platform_driver(iop3xx_i2c_driver);
525 MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
526 MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
527 MODULE_LICENSE("GPL");
528 MODULE_ALIAS("platform:IOP3xx-I2C");