2 * I2C bus driver for Amlogic Meson SoCs
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/i2c.h>
14 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/types.h>
22 /* Meson I2C register map */
24 #define REG_SLAVE_ADDR 0x04
25 #define REG_TOK_LIST0 0x08
26 #define REG_TOK_LIST1 0x0c
27 #define REG_TOK_WDATA0 0x10
28 #define REG_TOK_WDATA1 0x14
29 #define REG_TOK_RDATA0 0x18
30 #define REG_TOK_RDATA1 0x1c
32 /* Control register fields */
33 #define REG_CTRL_START BIT(0)
34 #define REG_CTRL_ACK_IGNORE BIT(1)
35 #define REG_CTRL_STATUS BIT(2)
36 #define REG_CTRL_ERROR BIT(3)
37 #define REG_CTRL_CLKDIV_SHIFT 12
38 #define REG_CTRL_CLKDIV_MASK GENMASK(21, 12)
39 #define REG_CTRL_CLKDIVEXT_SHIFT 28
40 #define REG_CTRL_CLKDIVEXT_MASK GENMASK(29, 28)
42 #define I2C_TIMEOUT_MS 500
47 TOKEN_SLAVE_ADDR_WRITE,
48 TOKEN_SLAVE_ADDR_READ,
61 * struct meson_i2c - Meson I2C device private data
63 * @adap: I2C adapter instance
64 * @dev: Pointer to device structure
65 * @regs: Base address of the device memory mapped registers
66 * @clk: Pointer to clock structure
68 * @msg: Pointer to the current I2C message
69 * @state: Current state in the driver state machine
70 * @last: Flag set for the last message in the transfer
71 * @count: Number of bytes to be sent/received in current transfer
72 * @pos: Current position in the send/receive buffer
73 * @error: Flag set when an error is received
74 * @lock: To avoid race conditions between irq handler and xfer code
75 * @done: Completion used to wait for transfer termination
76 * @tokens: Sequence of tokens to be written to the device
77 * @num_tokens: Number of tokens
80 struct i2c_adapter adap;
93 struct completion done;
98 static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
103 data = readl(i2c->regs + reg);
106 writel(data, i2c->regs + reg);
109 static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
116 static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
118 if (i2c->num_tokens < 8)
119 i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
121 i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
126 static void meson_i2c_write_tokens(struct meson_i2c *i2c)
128 writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
129 writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
132 static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
134 unsigned long clk_rate = clk_get_rate(i2c->clk);
137 div = DIV_ROUND_UP(clk_rate, freq * 4);
139 /* clock divider has 12 bits */
140 if (div >= (1 << 12)) {
141 dev_err(i2c->dev, "requested bus frequency too low\n");
145 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
146 (div & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT);
148 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
149 (div >> 10) << REG_CTRL_CLKDIVEXT_SHIFT);
151 dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
152 clk_rate, freq, div);
155 static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
160 rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
161 rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
163 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
164 rdata0, rdata1, len);
166 for (i = 0; i < min(4, len); i++)
167 *buf++ = (rdata0 >> i * 8) & 0xff;
169 for (i = 4; i < min(8, len); i++)
170 *buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
173 static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
175 u32 wdata0 = 0, wdata1 = 0;
178 for (i = 0; i < min(4, len); i++)
179 wdata0 |= *buf++ << (i * 8);
181 for (i = 4; i < min(8, len); i++)
182 wdata1 |= *buf++ << ((i - 4) * 8);
184 writel(wdata0, i2c->regs + REG_TOK_WDATA0);
185 writel(wdata1, i2c->regs + REG_TOK_WDATA1);
187 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
188 wdata0, wdata1, len);
191 static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
193 bool write = !(i2c->msg->flags & I2C_M_RD);
196 i2c->count = min(i2c->msg->len - i2c->pos, 8);
198 for (i = 0; i < i2c->count - 1; i++)
199 meson_i2c_add_token(i2c, TOKEN_DATA);
202 if (write || i2c->pos + i2c->count < i2c->msg->len)
203 meson_i2c_add_token(i2c, TOKEN_DATA);
205 meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
209 meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
211 if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
212 meson_i2c_add_token(i2c, TOKEN_STOP);
215 static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
217 struct meson_i2c *i2c = dev_id;
220 spin_lock(&i2c->lock);
222 meson_i2c_reset_tokens(i2c);
223 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
224 ctrl = readl(i2c->regs + REG_CTRL);
226 dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
227 i2c->state, i2c->pos, i2c->count, ctrl);
229 if (i2c->state == STATE_IDLE) {
230 spin_unlock(&i2c->lock);
234 if (ctrl & REG_CTRL_ERROR) {
236 * The bit is set when the IGNORE_NAK bit is cleared
237 * and the device didn't respond. In this case, the
238 * I2C controller automatically generates a STOP
241 dev_dbg(i2c->dev, "error bit set\n");
243 i2c->state = STATE_IDLE;
244 complete(&i2c->done);
248 switch (i2c->state) {
250 if (i2c->count > 0) {
251 meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos,
253 i2c->pos += i2c->count;
256 if (i2c->pos >= i2c->msg->len) {
257 i2c->state = STATE_IDLE;
258 complete(&i2c->done);
262 meson_i2c_prepare_xfer(i2c);
265 i2c->pos += i2c->count;
267 if (i2c->pos >= i2c->msg->len) {
268 i2c->state = STATE_IDLE;
269 complete(&i2c->done);
273 meson_i2c_prepare_xfer(i2c);
278 if (i2c->state != STATE_IDLE) {
279 /* Restart the processing */
280 meson_i2c_write_tokens(i2c);
281 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START,
285 spin_unlock(&i2c->lock);
290 static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
294 token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
295 TOKEN_SLAVE_ADDR_WRITE;
297 writel(msg->addr << 1, i2c->regs + REG_SLAVE_ADDR);
298 meson_i2c_add_token(i2c, TOKEN_START);
299 meson_i2c_add_token(i2c, token);
302 static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
305 unsigned long time_left, flags;
314 meson_i2c_reset_tokens(i2c);
316 flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
317 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
319 if (!(msg->flags & I2C_M_NOSTART))
320 meson_i2c_do_start(i2c, msg);
322 i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
323 meson_i2c_prepare_xfer(i2c);
324 meson_i2c_write_tokens(i2c);
325 reinit_completion(&i2c->done);
327 /* Start the transfer */
328 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
330 time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
331 time_left = wait_for_completion_timeout(&i2c->done, time_left);
334 * Protect access to i2c struct and registers from interrupt
335 * handlers triggered by a transfer terminated after the
338 spin_lock_irqsave(&i2c->lock, flags);
340 /* Abort any active operation */
341 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
344 i2c->state = STATE_IDLE;
351 spin_unlock_irqrestore(&i2c->lock, flags);
356 static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
359 struct meson_i2c *i2c = adap->algo_data;
362 clk_enable(i2c->clk);
364 for (i = 0; i < num; i++) {
365 ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1);
370 clk_disable(i2c->clk);
375 static u32 meson_i2c_func(struct i2c_adapter *adap)
377 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
380 static const struct i2c_algorithm meson_i2c_algorithm = {
381 .master_xfer = meson_i2c_xfer,
382 .functionality = meson_i2c_func,
385 static int meson_i2c_probe(struct platform_device *pdev)
387 struct device_node *np = pdev->dev.of_node;
388 struct meson_i2c *i2c;
389 struct resource *mem;
390 struct i2c_timings timings;
393 i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
397 i2c_parse_fw_timings(&pdev->dev, &timings, true);
399 i2c->dev = &pdev->dev;
400 platform_set_drvdata(pdev, i2c);
402 spin_lock_init(&i2c->lock);
403 init_completion(&i2c->done);
405 i2c->clk = devm_clk_get(&pdev->dev, NULL);
406 if (IS_ERR(i2c->clk)) {
407 dev_err(&pdev->dev, "can't get device clock\n");
408 return PTR_ERR(i2c->clk);
411 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
412 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
413 if (IS_ERR(i2c->regs))
414 return PTR_ERR(i2c->regs);
416 irq = platform_get_irq(pdev, 0);
418 dev_err(&pdev->dev, "can't find IRQ\n");
422 ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
424 dev_err(&pdev->dev, "can't request IRQ\n");
428 ret = clk_prepare(i2c->clk);
430 dev_err(&pdev->dev, "can't prepare clock\n");
434 strlcpy(i2c->adap.name, "Meson I2C adapter",
435 sizeof(i2c->adap.name));
436 i2c->adap.owner = THIS_MODULE;
437 i2c->adap.algo = &meson_i2c_algorithm;
438 i2c->adap.dev.parent = &pdev->dev;
439 i2c->adap.dev.of_node = np;
440 i2c->adap.algo_data = i2c;
443 * A transfer is triggered when START bit changes from 0 to 1.
444 * Ensure that the bit is set to 0 after probe
446 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
448 ret = i2c_add_adapter(&i2c->adap);
450 clk_unprepare(i2c->clk);
454 meson_i2c_set_clk_div(i2c, timings.bus_freq_hz);
459 static int meson_i2c_remove(struct platform_device *pdev)
461 struct meson_i2c *i2c = platform_get_drvdata(pdev);
463 i2c_del_adapter(&i2c->adap);
464 clk_unprepare(i2c->clk);
469 static const struct of_device_id meson_i2c_match[] = {
470 { .compatible = "amlogic,meson6-i2c" },
471 { .compatible = "amlogic,meson-gxbb-i2c" },
474 MODULE_DEVICE_TABLE(of, meson_i2c_match);
476 static struct platform_driver meson_i2c_driver = {
477 .probe = meson_i2c_probe,
478 .remove = meson_i2c_remove,
481 .of_match_table = meson_i2c_match,
485 module_platform_driver(meson_i2c_driver);
487 MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
488 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
489 MODULE_LICENSE("GPL v2");