drivers/i2c/busses/i2c-mt65xx.c

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Xudong Chen <xudong.chen@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/completion.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/err.h>
  21 #include <linux/errno.h>
  22 #include <linux/i2c.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/module.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/scatterlist.h>
  33 #include <linux/sched.h>
  34 #include <linux/slab.h>
  35
  36 #define I2C_RS_TRANSFER                 (1 << 4)
  37 #define I2C_HS_NACKERR                  (1 << 2)
  38 #define I2C_ACKERR                      (1 << 1)
  39 #define I2C_TRANSAC_COMP                (1 << 0)
  40 #define I2C_TRANSAC_START               (1 << 0)
  41 #define I2C_RS_MUL_CNFG                 (1 << 15)
  42 #define I2C_RS_MUL_TRIG                 (1 << 14)
  43 #define I2C_DCM_DISABLE                 0x0000
  44 #define I2C_IO_CONFIG_OPEN_DRAIN        0x0003
  45 #define I2C_IO_CONFIG_PUSH_PULL         0x0000
  46 #define I2C_SOFT_RST                    0x0001
  47 #define I2C_FIFO_ADDR_CLR               0x0001
  48 #define I2C_DELAY_LEN                   0x0002
  49 #define I2C_ST_START_CON                0x8001
  50 #define I2C_FS_START_CON                0x1800
  51 #define I2C_TIME_CLR_VALUE              0x0000
  52 #define I2C_TIME_DEFAULT_VALUE          0x0003
  53 #define I2C_FS_TIME_INIT_VALUE          0x1303
  54 #define I2C_WRRD_TRANAC_VALUE           0x0002
  55 #define I2C_RD_TRANAC_VALUE             0x0001
  56
  57 #define I2C_DMA_CON_TX                  0x0000
  58 #define I2C_DMA_CON_RX                  0x0001
  59 #define I2C_DMA_START_EN                0x0001
  60 #define I2C_DMA_INT_FLAG_NONE           0x0000
  61 #define I2C_DMA_CLR_FLAG                0x0000
  62 #define I2C_DMA_HARD_RST                0x0002
  63
  64 #define I2C_DEFAULT_SPEED               100000  /* hz */
  65 #define MAX_FS_MODE_SPEED               400000
  66 #define MAX_HS_MODE_SPEED               3400000
  67 #define MAX_SAMPLE_CNT_DIV              8
  68 #define MAX_STEP_CNT_DIV                64
  69 #define MAX_HS_STEP_CNT_DIV             8
  70
  71 #define I2C_CONTROL_RS                  (0x1 << 1)
  72 #define I2C_CONTROL_DMA_EN              (0x1 << 2)
  73 #define I2C_CONTROL_CLK_EXT_EN          (0x1 << 3)
  74 #define I2C_CONTROL_DIR_CHANGE          (0x1 << 4)
  75 #define I2C_CONTROL_ACKERR_DET_EN       (0x1 << 5)
  76 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
  77 #define I2C_CONTROL_WRAPPER             (0x1 << 0)
  78
  79 #define I2C_DRV_NAME            "i2c-mt65xx"
  80
  81 enum DMA_REGS_OFFSET {
  82         OFFSET_INT_FLAG = 0x0,
  83         OFFSET_INT_EN = 0x04,
  84         OFFSET_EN = 0x08,
  85         OFFSET_RST = 0x0c,
  86         OFFSET_CON = 0x18,
  87         OFFSET_TX_MEM_ADDR = 0x1c,
  88         OFFSET_RX_MEM_ADDR = 0x20,
  89         OFFSET_TX_LEN = 0x24,
  90         OFFSET_RX_LEN = 0x28,
  91 };
  92
  93 enum i2c_trans_st_rs {
  94         I2C_TRANS_STOP = 0,
  95         I2C_TRANS_REPEATED_START,
  96 };
  97
  98 enum mtk_trans_op {
  99         I2C_MASTER_WR = 1,
 100         I2C_MASTER_RD,
 101         I2C_MASTER_WRRD,
 102 };
 103
 104 enum I2C_REGS_OFFSET {
 105         OFFSET_DATA_PORT = 0x0,
 106         OFFSET_SLAVE_ADDR = 0x04,
 107         OFFSET_INTR_MASK = 0x08,
 108         OFFSET_INTR_STAT = 0x0c,
 109         OFFSET_CONTROL = 0x10,
 110         OFFSET_TRANSFER_LEN = 0x14,
 111         OFFSET_TRANSAC_LEN = 0x18,
 112         OFFSET_DELAY_LEN = 0x1c,
 113         OFFSET_TIMING = 0x20,
 114         OFFSET_START = 0x24,
 115         OFFSET_EXT_CONF = 0x28,
 116         OFFSET_FIFO_STAT = 0x30,
 117         OFFSET_FIFO_THRESH = 0x34,
 118         OFFSET_FIFO_ADDR_CLR = 0x38,
 119         OFFSET_IO_CONFIG = 0x40,
 120         OFFSET_RSV_DEBUG = 0x44,
 121         OFFSET_HS = 0x48,
 122         OFFSET_SOFTRESET = 0x50,
 123         OFFSET_DCM_EN = 0x54,
 124         OFFSET_PATH_DIR = 0x60,
 125         OFFSET_DEBUGSTAT = 0x64,
 126         OFFSET_DEBUGCTRL = 0x68,
 127         OFFSET_TRANSFER_LEN_AUX = 0x6c,
 128 };
 129
 130 struct mtk_i2c_compatible {
 131         const struct i2c_adapter_quirks *quirks;
 132         unsigned char pmic_i2c: 1;
 133         unsigned char dcm: 1;
 134         unsigned char auto_restart: 1;
 135         unsigned char aux_len_reg: 1;
 136 };
 137
 138 struct mtk_i2c {
 139         struct i2c_adapter adap;        /* i2c host adapter */
 140         struct device *dev;
 141         struct completion msg_complete;
 142
 143         /* set in i2c probe */
 144         void __iomem *base;             /* i2c base addr */
 145         void __iomem *pdmabase;         /* dma base address*/
 146         struct clk *clk_main;           /* main clock for i2c bus */
 147         struct clk *clk_dma;            /* DMA clock for i2c via DMA */
 148         struct clk *clk_pmic;           /* PMIC clock for i2c from PMIC */
 149         bool have_pmic;                 /* can use i2c pins from PMIC */
 150         bool use_push_pull;             /* IO config push-pull mode */
 151
 152         u16 irq_stat;                   /* interrupt status */
 153         unsigned int speed_hz;          /* The speed in transfer */
 154         enum mtk_trans_op op;
 155         u16 timing_reg;
 156         u16 high_speed_reg;
 157         unsigned char auto_restart;
 158         bool ignore_restart_irq;
 159         const struct mtk_i2c_compatible *dev_comp;
 160 };
 161
 162 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
 163         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 164         .max_num_msgs = 1,
 165         .max_write_len = 255,
 166         .max_read_len = 255,
 167         .max_comb_1st_msg_len = 255,
 168         .max_comb_2nd_msg_len = 31,
 169 };
 170
 171 static const struct i2c_adapter_quirks mt8173_i2c_quirks = {
 172         .max_num_msgs = 65535,
 173         .max_write_len = 65535,
 174         .max_read_len = 65535,
 175         .max_comb_1st_msg_len = 65535,
 176         .max_comb_2nd_msg_len = 65535,
 177 };
 178
 179 static const struct mtk_i2c_compatible mt6577_compat = {
 180         .quirks = &mt6577_i2c_quirks,
 181         .pmic_i2c = 0,
 182         .dcm = 1,
 183         .auto_restart = 0,
 184         .aux_len_reg = 0,
 185 };
 186
 187 static const struct mtk_i2c_compatible mt6589_compat = {
 188         .quirks = &mt6577_i2c_quirks,
 189         .pmic_i2c = 1,
 190         .dcm = 0,
 191         .auto_restart = 0,
 192         .aux_len_reg = 0,
 193 };
 194
 195 static const struct mtk_i2c_compatible mt8173_compat = {
 196         .quirks = &mt8173_i2c_quirks,
 197         .pmic_i2c = 0,
 198         .dcm = 1,
 199         .auto_restart = 1,
 200         .aux_len_reg = 1,
 201 };
 202
 203 static const struct of_device_id mtk_i2c_of_match[] = {
 204         { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
 205         { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
 206         { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
 207         {}
 208 };
 209 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
 210
 211 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
 212 {
 213         int ret;
 214
 215         ret = clk_prepare_enable(i2c->clk_dma);
 216         if (ret)
 217                 return ret;
 218
 219         ret = clk_prepare_enable(i2c->clk_main);
 220         if (ret)
 221                 goto err_main;
 222
 223         if (i2c->have_pmic) {
 224                 ret = clk_prepare_enable(i2c->clk_pmic);
 225                 if (ret)
 226                         goto err_pmic;
 227         }
 228         return 0;
 229
 230 err_pmic:
 231         clk_disable_unprepare(i2c->clk_main);
 232 err_main:
 233         clk_disable_unprepare(i2c->clk_dma);
 234
 235         return ret;
 236 }
 237
 238 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
 239 {
 240         if (i2c->have_pmic)
 241                 clk_disable_unprepare(i2c->clk_pmic);
 242
 243         clk_disable_unprepare(i2c->clk_main);
 244         clk_disable_unprepare(i2c->clk_dma);
 245 }
 246
 247 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 248 {
 249         u16 control_reg;
 250
 251         writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
 252
 253         /* Set ioconfig */
 254         if (i2c->use_push_pull)
 255                 writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
 256         else
 257                 writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
 258
 259         if (i2c->dev_comp->dcm)
 260                 writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
 261
 262         writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
 263         writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
 264
 265         /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
 266         if (i2c->have_pmic)
 267                 writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
 268
 269         control_reg = I2C_CONTROL_ACKERR_DET_EN |
 270                       I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
 271         writew(control_reg, i2c->base + OFFSET_CONTROL);
 272         writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
 273
 274         writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
 275         udelay(50);
 276         writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 277 }
 278
 279 /*
 280  * Calculate i2c port speed
 281  *
 282  * Hardware design:
 283  * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
 284  * clock_div: fixed in hardware, but may be various in different SoCs
 285  *
 286  * The calculation want to pick the highest bus frequency that is still
 287  * less than or equal to i2c->speed_hz. The calculation try to get
 288  * sample_cnt and step_cn
 289  */
 290 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk,
 291                              unsigned int clock_div)
 292 {
 293         unsigned int clk_src;
 294         unsigned int step_cnt;
 295         unsigned int sample_cnt;
 296         unsigned int max_step_cnt;
 297         unsigned int target_speed;
 298         unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
 299         unsigned int base_step_cnt;
 300         unsigned int opt_div;
 301         unsigned int best_mul;
 302         unsigned int cnt_mul;
 303
 304         clk_src = parent_clk / clock_div;
 305         target_speed = i2c->speed_hz;
 306
 307         if (target_speed > MAX_HS_MODE_SPEED)
 308                 target_speed = MAX_HS_MODE_SPEED;
 309
 310         if (target_speed > MAX_FS_MODE_SPEED)
 311                 max_step_cnt = MAX_HS_STEP_CNT_DIV;
 312         else
 313                 max_step_cnt = MAX_STEP_CNT_DIV;
 314
 315         base_step_cnt = max_step_cnt;
 316         /* Find the best combination */
 317         opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
 318         best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
 319
 320         /* Search for the best pair (sample_cnt, step_cnt) with
 321          * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
 322          * 0 < step_cnt < max_step_cnt
 323          * sample_cnt * step_cnt >= opt_div
 324          * optimizing for sample_cnt * step_cnt being minimal
 325          */
 326         for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
 327                 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
 328                 cnt_mul = step_cnt * sample_cnt;
 329                 if (step_cnt > max_step_cnt)
 330                         continue;
 331
 332                 if (cnt_mul < best_mul) {
 333                         best_mul = cnt_mul;
 334                         base_sample_cnt = sample_cnt;
 335                         base_step_cnt = step_cnt;
 336                         if (best_mul == opt_div)
 337                                 break;
 338                 }
 339         }
 340
 341         sample_cnt = base_sample_cnt;
 342         step_cnt = base_step_cnt;
 343
 344         if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
 345                 /* In this case, hardware can't support such
 346                  * low i2c_bus_freq
 347                  */
 348                 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
 349                 return -EINVAL;
 350         }
 351
 352         step_cnt--;
 353         sample_cnt--;
 354
 355         if (target_speed > MAX_FS_MODE_SPEED) {
 356                 /* Set the high speed mode register */
 357                 i2c->timing_reg = I2C_FS_TIME_INIT_VALUE;
 358                 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
 359                         (sample_cnt << 12) | (step_cnt << 8);
 360         } else {
 361                 i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0);
 362                 /* Disable the high speed transaction */
 363                 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
 370                                int num, int left_num)
 371 {
 372         u16 addr_reg;
 373         u16 start_reg;
 374         u16 control_reg;
 375         u16 restart_flag = 0;
 376         dma_addr_t rpaddr = 0;
 377         dma_addr_t wpaddr = 0;
 378         int ret;
 379
 380         i2c->irq_stat = 0;
 381
 382         if (i2c->auto_restart)
 383                 restart_flag = I2C_RS_TRANSFER;
 384
 385         reinit_completion(&i2c->msg_complete);
 386
 387         control_reg = readw(i2c->base + OFFSET_CONTROL) &
 388                         ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
 389         if ((i2c->speed_hz > 400000) || (left_num >= 1))
 390                 control_reg |= I2C_CONTROL_RS;
 391
 392         if (i2c->op == I2C_MASTER_WRRD)
 393                 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
 394
 395         writew(control_reg, i2c->base + OFFSET_CONTROL);
 396
 397         /* set start condition */
 398         if (i2c->speed_hz <= 100000)
 399                 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
 400         else
 401                 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
 402
 403         addr_reg = msgs->addr << 1;
 404         if (i2c->op == I2C_MASTER_RD)
 405                 addr_reg |= 0x1;
 406
 407         writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
 408
 409         /* Clear interrupt status */
 410         writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 411                I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
 412         writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
 413
 414         /* Enable interrupt */
 415         writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 416                I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
 417
 418         /* Set transfer and transaction len */
 419         if (i2c->op == I2C_MASTER_WRRD) {
 420                 if (i2c->dev_comp->aux_len_reg) {
 421                         writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
 422                         writew((msgs + 1)->len, i2c->base +
 423                                OFFSET_TRANSFER_LEN_AUX);
 424                 } else {
 425                         writew(msgs->len | ((msgs + 1)->len) << 8,
 426                                i2c->base + OFFSET_TRANSFER_LEN);
 427                 }
 428                 writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
 429         } else {
 430                 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
 431                 writew(num, i2c->base + OFFSET_TRANSAC_LEN);
 432         }
 433
 434         /* Prepare buffer data to start transfer */
 435         if (i2c->op == I2C_MASTER_RD) {
 436                 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
 437                 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
 438                 rpaddr = dma_map_single(i2c->dev, msgs->buf,
 439                                         msgs->len, DMA_FROM_DEVICE);
 440                 if (dma_mapping_error(i2c->dev, rpaddr))
 441                         return -ENOMEM;
 442                 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
 443                 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
 444         } else if (i2c->op == I2C_MASTER_WR) {
 445                 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
 446                 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
 447                 wpaddr = dma_map_single(i2c->dev, msgs->buf,
 448                                         msgs->len, DMA_TO_DEVICE);
 449                 if (dma_mapping_error(i2c->dev, wpaddr))
 450                         return -ENOMEM;
 451                 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
 452                 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
 453         } else {
 454                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
 455                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
 456                 wpaddr = dma_map_single(i2c->dev, msgs->buf,
 457                                         msgs->len, DMA_TO_DEVICE);
 458                 if (dma_mapping_error(i2c->dev, wpaddr))
 459                         return -ENOMEM;
 460                 rpaddr = dma_map_single(i2c->dev, (msgs + 1)->buf,
 461                                         (msgs + 1)->len,
 462                                         DMA_FROM_DEVICE);
 463                 if (dma_mapping_error(i2c->dev, rpaddr)) {
 464                         dma_unmap_single(i2c->dev, wpaddr,
 465                                          msgs->len, DMA_TO_DEVICE);
 466                         return -ENOMEM;
 467                 }
 468                 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
 469                 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
 470                 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
 471                 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
 472         }
 473
 474         writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
 475
 476         if (!i2c->auto_restart) {
 477                 start_reg = I2C_TRANSAC_START;
 478         } else {
 479                 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
 480                 if (left_num >= 1)
 481                         start_reg |= I2C_RS_MUL_CNFG;
 482         }
 483         writew(start_reg, i2c->base + OFFSET_START);
 484
 485         ret = wait_for_completion_timeout(&i2c->msg_complete,
 486                                           i2c->adap.timeout);
 487
 488         /* Clear interrupt mask */
 489         writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 490                I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
 491
 492         if (i2c->op == I2C_MASTER_WR) {
 493                 dma_unmap_single(i2c->dev, wpaddr,
 494                                  msgs->len, DMA_TO_DEVICE);
 495         } else if (i2c->op == I2C_MASTER_RD) {
 496                 dma_unmap_single(i2c->dev, rpaddr,
 497                                  msgs->len, DMA_FROM_DEVICE);
 498         } else {
 499                 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
 500                                  DMA_TO_DEVICE);
 501                 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
 502                                  DMA_FROM_DEVICE);
 503         }
 504
 505         if (ret == 0) {
 506                 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
 507                 mtk_i2c_init_hw(i2c);
 508                 return -ETIMEDOUT;
 509         }
 510
 511         completion_done(&i2c->msg_complete);
 512
 513         if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
 514                 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
 515                 mtk_i2c_init_hw(i2c);
 516                 return -ENXIO;
 517         }
 518
 519         return 0;
 520 }
 521
 522 static int mtk_i2c_transfer(struct i2c_adapter *adap,
 523                             struct i2c_msg msgs[], int num)
 524 {
 525         int ret;
 526         int left_num = num;
 527         struct mtk_i2c *i2c = i2c_get_adapdata(adap);
 528
 529         ret = mtk_i2c_clock_enable(i2c);
 530         if (ret)
 531                 return ret;
 532
 533         i2c->auto_restart = i2c->dev_comp->auto_restart;
 534
 535         /* checking if we can skip restart and optimize using WRRD mode */
 536         if (i2c->auto_restart && num == 2) {
 537                 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
 538                     msgs[0].addr == msgs[1].addr) {
 539                         i2c->auto_restart = 0;
 540                 }
 541         }
 542
 543         if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED)
 544                 /* ignore the first restart irq after the master code,
 545                  * otherwise the first transfer will be discarded.
 546                  */
 547                 i2c->ignore_restart_irq = true;
 548         else
 549                 i2c->ignore_restart_irq = false;
 550
 551         while (left_num--) {
 552                 if (!msgs->buf) {
 553                         dev_dbg(i2c->dev, "data buffer is NULL.\n");
 554                         ret = -EINVAL;
 555                         goto err_exit;
 556                 }
 557
 558                 if (msgs->flags & I2C_M_RD)
 559                         i2c->op = I2C_MASTER_RD;
 560                 else
 561                         i2c->op = I2C_MASTER_WR;
 562
 563                 if (!i2c->auto_restart) {
 564                         if (num > 1) {
 565                                 /* combined two messages into one transaction */
 566                                 i2c->op = I2C_MASTER_WRRD;
 567                                 left_num--;
 568                         }
 569                 }
 570
 571                 /* always use DMA mode. */
 572                 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
 573                 if (ret < 0)
 574                         goto err_exit;
 575
 576                 msgs++;
 577         }
 578         /* the return value is number of executed messages */
 579         ret = num;
 580
 581 err_exit:
 582         mtk_i2c_clock_disable(i2c);
 583         return ret;
 584 }
 585
 586 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
 587 {
 588         struct mtk_i2c *i2c = dev_id;
 589         u16 restart_flag = 0;
 590         u16 intr_stat;
 591
 592         if (i2c->auto_restart)
 593                 restart_flag = I2C_RS_TRANSFER;
 594
 595         intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
 596         writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
 597
 598         /*
 599          * when occurs ack error, i2c controller generate two interrupts
 600          * first is the ack error interrupt, then the complete interrupt
 601          * i2c->irq_stat need keep the two interrupt value.
 602          */
 603         i2c->irq_stat |= intr_stat;
 604
 605         if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
 606                 i2c->ignore_restart_irq = false;
 607                 i2c->irq_stat = 0;
 608                 writew(I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | I2C_TRANSAC_START,
 609                        i2c->base + OFFSET_START);
 610         } else {
 611                 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
 612                         complete(&i2c->msg_complete);
 613         }
 614
 615         return IRQ_HANDLED;
 616 }
 617
 618 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
 619 {
 620         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 621 }
 622
 623 static const struct i2c_algorithm mtk_i2c_algorithm = {
 624         .master_xfer = mtk_i2c_transfer,
 625         .functionality = mtk_i2c_functionality,
 626 };
 627
 628 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c,
 629                             unsigned int *clk_src_div)
 630 {
 631         int ret;
 632
 633         ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
 634         if (ret < 0)
 635                 i2c->speed_hz = I2C_DEFAULT_SPEED;
 636
 637         ret = of_property_read_u32(np, "clock-div", clk_src_div);
 638         if (ret < 0)
 639                 return ret;
 640
 641         if (*clk_src_div == 0)
 642                 return -EINVAL;
 643
 644         i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
 645         i2c->use_push_pull =
 646                 of_property_read_bool(np, "mediatek,use-push-pull");
 647
 648         return 0;
 649 }
 650
 651 static int mtk_i2c_probe(struct platform_device *pdev)
 652 {
 653         const struct of_device_id *of_id;
 654         int ret = 0;
 655         struct mtk_i2c *i2c;
 656         struct clk *clk;
 657         unsigned int clk_src_div;
 658         struct resource *res;
 659         int irq;
 660
 661         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 662         if (!i2c)
 663                 return -ENOMEM;
 664
 665         ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div);
 666         if (ret)
 667                 return -EINVAL;
 668
 669         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 670         i2c->base = devm_ioremap_resource(&pdev->dev, res);
 671         if (IS_ERR(i2c->base))
 672                 return PTR_ERR(i2c->base);
 673
 674         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 675         i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
 676         if (IS_ERR(i2c->pdmabase))
 677                 return PTR_ERR(i2c->pdmabase);
 678
 679         irq = platform_get_irq(pdev, 0);
 680         if (irq <= 0)
 681                 return irq;
 682
 683         init_completion(&i2c->msg_complete);
 684
 685         of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node);
 686         if (!of_id)
 687                 return -EINVAL;
 688
 689         i2c->dev_comp = of_id->data;
 690         i2c->adap.dev.of_node = pdev->dev.of_node;
 691         i2c->dev = &pdev->dev;
 692         i2c->adap.dev.parent = &pdev->dev;
 693         i2c->adap.owner = THIS_MODULE;
 694         i2c->adap.algo = &mtk_i2c_algorithm;
 695         i2c->adap.quirks = i2c->dev_comp->quirks;
 696         i2c->adap.timeout = 2 * HZ;
 697         i2c->adap.retries = 1;
 698
 699         if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
 700                 return -EINVAL;
 701
 702         i2c->clk_main = devm_clk_get(&pdev->dev, "main");
 703         if (IS_ERR(i2c->clk_main)) {
 704                 dev_err(&pdev->dev, "cannot get main clock\n");
 705                 return PTR_ERR(i2c->clk_main);
 706         }
 707
 708         i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
 709         if (IS_ERR(i2c->clk_dma)) {
 710                 dev_err(&pdev->dev, "cannot get dma clock\n");
 711                 return PTR_ERR(i2c->clk_dma);
 712         }
 713
 714         clk = i2c->clk_main;
 715         if (i2c->have_pmic) {
 716                 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
 717                 if (IS_ERR(i2c->clk_pmic)) {
 718                         dev_err(&pdev->dev, "cannot get pmic clock\n");
 719                         return PTR_ERR(i2c->clk_pmic);
 720                 }
 721                 clk = i2c->clk_pmic;
 722         }
 723
 724         strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
 725
 726         ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk), clk_src_div);
 727         if (ret) {
 728                 dev_err(&pdev->dev, "Failed to set the speed.\n");
 729                 return -EINVAL;
 730         }
 731
 732         ret = mtk_i2c_clock_enable(i2c);
 733         if (ret) {
 734                 dev_err(&pdev->dev, "clock enable failed!\n");
 735                 return ret;
 736         }
 737         mtk_i2c_init_hw(i2c);
 738         mtk_i2c_clock_disable(i2c);
 739
 740         ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
 741                                IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
 742         if (ret < 0) {
 743                 dev_err(&pdev->dev,
 744                         "Request I2C IRQ %d fail\n", irq);
 745                 return ret;
 746         }
 747
 748         i2c_set_adapdata(&i2c->adap, i2c);
 749         ret = i2c_add_adapter(&i2c->adap);
 750         if (ret) {
 751                 dev_err(&pdev->dev, "Failed to add i2c bus to i2c core\n");
 752                 return ret;
 753         }
 754
 755         platform_set_drvdata(pdev, i2c);
 756
 757         return 0;
 758 }
 759
 760 static int mtk_i2c_remove(struct platform_device *pdev)
 761 {
 762         struct mtk_i2c *i2c = platform_get_drvdata(pdev);
 763
 764         i2c_del_adapter(&i2c->adap);
 765
 766         return 0;
 767 }
 768
 769 #ifdef CONFIG_PM_SLEEP
 770 static int mtk_i2c_resume(struct device *dev)
 771 {
 772         struct mtk_i2c *i2c = dev_get_drvdata(dev);
 773
 774         mtk_i2c_init_hw(i2c);
 775
 776         return 0;
 777 }
 778 #endif
 779
 780 static const struct dev_pm_ops mtk_i2c_pm = {
 781         SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
 782 };
 783
 784 static struct platform_driver mtk_i2c_driver = {
 785         .probe = mtk_i2c_probe,
 786         .remove = mtk_i2c_remove,
 787         .driver = {
 788                 .name = I2C_DRV_NAME,
 789                 .pm = &mtk_i2c_pm,
 790                 .of_match_table = of_match_ptr(mtk_i2c_of_match),
 791         },
 792 };
 793
 794 module_platform_driver(mtk_i2c_driver);
 795
 796 MODULE_LICENSE("GPL v2");
 797 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
 798 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");