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Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...
[karo-tx-linux.git] / drivers / i2c / busses / i2c-mxs.c
1 /*
2  * Freescale MXS I2C bus driver
3  *
4  * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
5  *
6  * based on a (non-working) driver which was:
7  *
8  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  */
16
17 #include <linux/slab.h>
18 #include <linux/device.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/completion.h>
24 #include <linux/platform_device.h>
25 #include <linux/jiffies.h>
26 #include <linux/io.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/stmp_device.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <linux/of_i2c.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dmaengine.h>
34 #include <linux/fsl/mxs-dma.h>
35
36 #define DRIVER_NAME "mxs-i2c"
37
38 #define MXS_I2C_CTRL0           (0x00)
39 #define MXS_I2C_CTRL0_SET       (0x04)
40
41 #define MXS_I2C_CTRL0_SFTRST                    0x80000000
42 #define MXS_I2C_CTRL0_RUN                       0x20000000
43 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST          0x02000000
44 #define MXS_I2C_CTRL0_RETAIN_CLOCK              0x00200000
45 #define MXS_I2C_CTRL0_POST_SEND_STOP            0x00100000
46 #define MXS_I2C_CTRL0_PRE_SEND_START            0x00080000
47 #define MXS_I2C_CTRL0_MASTER_MODE               0x00020000
48 #define MXS_I2C_CTRL0_DIRECTION                 0x00010000
49 #define MXS_I2C_CTRL0_XFER_COUNT(v)             ((v) & 0x0000FFFF)
50
51 #define MXS_I2C_TIMING0         (0x10)
52 #define MXS_I2C_TIMING1         (0x20)
53 #define MXS_I2C_TIMING2         (0x30)
54
55 #define MXS_I2C_CTRL1           (0x40)
56 #define MXS_I2C_CTRL1_SET       (0x44)
57 #define MXS_I2C_CTRL1_CLR       (0x48)
58
59 #define MXS_I2C_CTRL1_CLR_GOT_A_NAK             0x10000000
60 #define MXS_I2C_CTRL1_BUS_FREE_IRQ              0x80
61 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ     0x40
62 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ          0x20
63 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ    0x10
64 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ            0x08
65 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ           0x04
66 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ            0x02
67 #define MXS_I2C_CTRL1_SLAVE_IRQ                 0x01
68
69 #define MXS_I2C_STAT            (0x50)
70 #define MXS_I2C_STAT_BUS_BUSY                   0x00000800
71 #define MXS_I2C_STAT_CLK_GEN_BUSY               0x00000400
72
73 #define MXS_I2C_DATA            (0xa0)
74
75 #define MXS_I2C_DEBUG0          (0xb0)
76 #define MXS_I2C_DEBUG0_CLR      (0xb8)
77
78 #define MXS_I2C_DEBUG0_DMAREQ   0x80000000
79
80 #define MXS_I2C_IRQ_MASK        (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
81                                  MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
82                                  MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
83                                  MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
84                                  MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
85                                  MXS_I2C_CTRL1_SLAVE_IRQ)
86
87
88 #define MXS_CMD_I2C_SELECT      (MXS_I2C_CTRL0_RETAIN_CLOCK |   \
89                                  MXS_I2C_CTRL0_PRE_SEND_START | \
90                                  MXS_I2C_CTRL0_MASTER_MODE |    \
91                                  MXS_I2C_CTRL0_DIRECTION |      \
92                                  MXS_I2C_CTRL0_XFER_COUNT(1))
93
94 #define MXS_CMD_I2C_WRITE       (MXS_I2C_CTRL0_PRE_SEND_START | \
95                                  MXS_I2C_CTRL0_MASTER_MODE |    \
96                                  MXS_I2C_CTRL0_DIRECTION)
97
98 #define MXS_CMD_I2C_READ        (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
99                                  MXS_I2C_CTRL0_MASTER_MODE)
100
101 /**
102  * struct mxs_i2c_dev - per device, private MXS-I2C data
103  *
104  * @dev: driver model device node
105  * @regs: IO registers pointer
106  * @cmd_complete: completion object for transaction wait
107  * @cmd_err: error code for last transaction
108  * @adapter: i2c subsystem adapter node
109  */
110 struct mxs_i2c_dev {
111         struct device *dev;
112         void __iomem *regs;
113         struct completion cmd_complete;
114         int cmd_err;
115         struct i2c_adapter adapter;
116
117         uint32_t timing0;
118         uint32_t timing1;
119
120         /* DMA support components */
121         int                             dma_channel;
122         struct dma_chan                 *dmach;
123         struct mxs_dma_data             dma_data;
124         uint32_t                        pio_data[2];
125         uint32_t                        addr_data;
126         struct scatterlist              sg_io[2];
127         bool                            dma_read;
128 };
129
130 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
131 {
132         stmp_reset_block(i2c->regs);
133
134         /*
135          * Configure timing for the I2C block. The I2C TIMING2 register has to
136          * be programmed with this particular magic number. The rest is derived
137          * from the XTAL speed and requested I2C speed.
138          *
139          * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
140          */
141         writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
142         writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
143         writel(0x00300030, i2c->regs + MXS_I2C_TIMING2);
144
145         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
146 }
147
148 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
149 {
150         if (i2c->dma_read) {
151                 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
152                 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
153         } else {
154                 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
155         }
156 }
157
158 static void mxs_i2c_dma_irq_callback(void *param)
159 {
160         struct mxs_i2c_dev *i2c = param;
161
162         complete(&i2c->cmd_complete);
163         mxs_i2c_dma_finish(i2c);
164 }
165
166 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
167                         struct i2c_msg *msg, uint32_t flags)
168 {
169         struct dma_async_tx_descriptor *desc;
170         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
171
172         if (msg->flags & I2C_M_RD) {
173                 i2c->dma_read = 1;
174                 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
175
176                 /*
177                  * SELECT command.
178                  */
179
180                 /* Queue the PIO register write transfer. */
181                 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
182                 desc = dmaengine_prep_slave_sg(i2c->dmach,
183                                         (struct scatterlist *)&i2c->pio_data[0],
184                                         1, DMA_TRANS_NONE, 0);
185                 if (!desc) {
186                         dev_err(i2c->dev,
187                                 "Failed to get PIO reg. write descriptor.\n");
188                         goto select_init_pio_fail;
189                 }
190
191                 /* Queue the DMA data transfer. */
192                 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
193                 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
194                 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
195                                         DMA_MEM_TO_DEV,
196                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
197                 if (!desc) {
198                         dev_err(i2c->dev,
199                                 "Failed to get DMA data write descriptor.\n");
200                         goto select_init_dma_fail;
201                 }
202
203                 /*
204                  * READ command.
205                  */
206
207                 /* Queue the PIO register write transfer. */
208                 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
209                                 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
210                 desc = dmaengine_prep_slave_sg(i2c->dmach,
211                                         (struct scatterlist *)&i2c->pio_data[1],
212                                         1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
213                 if (!desc) {
214                         dev_err(i2c->dev,
215                                 "Failed to get PIO reg. write descriptor.\n");
216                         goto select_init_dma_fail;
217                 }
218
219                 /* Queue the DMA data transfer. */
220                 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
221                 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
222                 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
223                                         DMA_DEV_TO_MEM,
224                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
225                 if (!desc) {
226                         dev_err(i2c->dev,
227                                 "Failed to get DMA data write descriptor.\n");
228                         goto read_init_dma_fail;
229                 }
230         } else {
231                 i2c->dma_read = 0;
232                 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
233
234                 /*
235                  * WRITE command.
236                  */
237
238                 /* Queue the PIO register write transfer. */
239                 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
240                                 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
241                 desc = dmaengine_prep_slave_sg(i2c->dmach,
242                                         (struct scatterlist *)&i2c->pio_data[0],
243                                         1, DMA_TRANS_NONE, 0);
244                 if (!desc) {
245                         dev_err(i2c->dev,
246                                 "Failed to get PIO reg. write descriptor.\n");
247                         goto write_init_pio_fail;
248                 }
249
250                 /* Queue the DMA data transfer. */
251                 sg_init_table(i2c->sg_io, 2);
252                 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
253                 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
254                 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
255                 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
256                                         DMA_MEM_TO_DEV,
257                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
258                 if (!desc) {
259                         dev_err(i2c->dev,
260                                 "Failed to get DMA data write descriptor.\n");
261                         goto write_init_dma_fail;
262                 }
263         }
264
265         /*
266          * The last descriptor must have this callback,
267          * to finish the DMA transaction.
268          */
269         desc->callback = mxs_i2c_dma_irq_callback;
270         desc->callback_param = i2c;
271
272         /* Start the transfer. */
273         dmaengine_submit(desc);
274         dma_async_issue_pending(i2c->dmach);
275         return 0;
276
277 /* Read failpath. */
278 read_init_dma_fail:
279         dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
280 select_init_dma_fail:
281         dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
282 select_init_pio_fail:
283         dmaengine_terminate_all(i2c->dmach);
284         return -EINVAL;
285
286 /* Write failpath. */
287 write_init_dma_fail:
288         dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
289 write_init_pio_fail:
290         dmaengine_terminate_all(i2c->dmach);
291         return -EINVAL;
292 }
293
294 static int mxs_i2c_pio_wait_dmareq(struct mxs_i2c_dev *i2c)
295 {
296         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
297
298         while (!(readl(i2c->regs + MXS_I2C_DEBUG0) &
299                 MXS_I2C_DEBUG0_DMAREQ)) {
300                 if (time_after(jiffies, timeout))
301                         return -ETIMEDOUT;
302                 cond_resched();
303         }
304
305         return 0;
306 }
307
308 static int mxs_i2c_pio_wait_cplt(struct mxs_i2c_dev *i2c, int last)
309 {
310         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
311
312         /*
313          * We do not use interrupts in the PIO mode. Due to the
314          * maximum transfer length being 8 bytes in PIO mode, the
315          * overhead of interrupt would be too large and this would
316          * neglect the gain from using the PIO mode.
317          */
318
319         while (!(readl(i2c->regs + MXS_I2C_CTRL1) &
320                 MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)) {
321                 if (time_after(jiffies, timeout))
322                         return -ETIMEDOUT;
323                 cond_resched();
324         }
325
326         writel(MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ,
327                 i2c->regs + MXS_I2C_CTRL1_CLR);
328
329         /*
330          * When ending a transfer with a stop, we have to wait for the bus to
331          * go idle before we report the transfer as completed. Otherwise the
332          * start of the next transfer may race with the end of the current one.
333          */
334         while (last && (readl(i2c->regs + MXS_I2C_STAT) &
335                         (MXS_I2C_STAT_BUS_BUSY | MXS_I2C_STAT_CLK_GEN_BUSY))) {
336                 if (time_after(jiffies, timeout))
337                         return -ETIMEDOUT;
338                 cond_resched();
339         }
340
341         return 0;
342 }
343
344 static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
345 {
346         u32 state;
347
348         state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
349
350         if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
351                 i2c->cmd_err = -ENXIO;
352         else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
353                           MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
354                           MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
355                           MXS_I2C_CTRL1_SLAVE_IRQ))
356                 i2c->cmd_err = -EIO;
357
358         return i2c->cmd_err;
359 }
360
361 static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
362 {
363         u32 reg;
364
365         writel(cmd, i2c->regs + MXS_I2C_CTRL0);
366
367         /* readback makes sure the write is latched into hardware */
368         reg = readl(i2c->regs + MXS_I2C_CTRL0);
369         reg |= MXS_I2C_CTRL0_RUN;
370         writel(reg, i2c->regs + MXS_I2C_CTRL0);
371 }
372
373 static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
374                         struct i2c_msg *msg, uint32_t flags)
375 {
376         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
377         uint32_t addr_data = msg->addr << 1;
378         uint32_t data = 0;
379         int i, shifts_left, ret;
380
381         /* Mute IRQs coming from this block. */
382         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
383
384         if (msg->flags & I2C_M_RD) {
385                 addr_data |= I2C_SMBUS_READ;
386
387                 /* SELECT command. */
388                 mxs_i2c_pio_trigger_cmd(i2c, MXS_CMD_I2C_SELECT);
389
390                 ret = mxs_i2c_pio_wait_dmareq(i2c);
391                 if (ret)
392                         return ret;
393
394                 writel(addr_data, i2c->regs + MXS_I2C_DATA);
395                 writel(MXS_I2C_DEBUG0_DMAREQ, i2c->regs + MXS_I2C_DEBUG0_CLR);
396
397                 ret = mxs_i2c_pio_wait_cplt(i2c, 0);
398                 if (ret)
399                         return ret;
400
401                 if (mxs_i2c_pio_check_error_state(i2c))
402                         goto cleanup;
403
404                 /* READ command. */
405                 mxs_i2c_pio_trigger_cmd(i2c,
406                                         MXS_CMD_I2C_READ | flags |
407                                         MXS_I2C_CTRL0_XFER_COUNT(msg->len));
408
409                 for (i = 0; i < msg->len; i++) {
410                         if ((i & 3) == 0) {
411                                 ret = mxs_i2c_pio_wait_dmareq(i2c);
412                                 if (ret)
413                                         return ret;
414                                 data = readl(i2c->regs + MXS_I2C_DATA);
415                                 writel(MXS_I2C_DEBUG0_DMAREQ,
416                                        i2c->regs + MXS_I2C_DEBUG0_CLR);
417                         }
418                         msg->buf[i] = data & 0xff;
419                         data >>= 8;
420                 }
421         } else {
422                 addr_data |= I2C_SMBUS_WRITE;
423
424                 /* WRITE command. */
425                 mxs_i2c_pio_trigger_cmd(i2c,
426                                         MXS_CMD_I2C_WRITE | flags |
427                                         MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1));
428
429                 /*
430                  * The LSB of data buffer is the first byte blasted across
431                  * the bus. Higher order bytes follow. Thus the following
432                  * filling schematic.
433                  */
434                 data = addr_data << 24;
435                 for (i = 0; i < msg->len; i++) {
436                         data >>= 8;
437                         data |= (msg->buf[i] << 24);
438                         if ((i & 3) == 2) {
439                                 ret = mxs_i2c_pio_wait_dmareq(i2c);
440                                 if (ret)
441                                         return ret;
442                                 writel(data, i2c->regs + MXS_I2C_DATA);
443                                 writel(MXS_I2C_DEBUG0_DMAREQ,
444                                        i2c->regs + MXS_I2C_DEBUG0_CLR);
445                         }
446                 }
447
448                 shifts_left = 24 - (i & 3) * 8;
449                 if (shifts_left) {
450                         data >>= shifts_left;
451                         ret = mxs_i2c_pio_wait_dmareq(i2c);
452                         if (ret)
453                                 return ret;
454                         writel(data, i2c->regs + MXS_I2C_DATA);
455                         writel(MXS_I2C_DEBUG0_DMAREQ,
456                                i2c->regs + MXS_I2C_DEBUG0_CLR);
457                 }
458         }
459
460         ret = mxs_i2c_pio_wait_cplt(i2c, flags & MXS_I2C_CTRL0_POST_SEND_STOP);
461         if (ret)
462                 return ret;
463
464         /* make sure we capture any occurred error into cmd_err */
465         mxs_i2c_pio_check_error_state(i2c);
466
467 cleanup:
468         /* Clear any dangling IRQs and re-enable interrupts. */
469         writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
470         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
471
472         return 0;
473 }
474
475 /*
476  * Low level master read/write transaction.
477  */
478 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
479                                 int stop)
480 {
481         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
482         int ret;
483         int flags;
484
485         flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
486
487         dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
488                 msg->addr, msg->len, msg->flags, stop);
489
490         if (msg->len == 0)
491                 return -EINVAL;
492
493         /*
494          * The current boundary to select between PIO/DMA transfer method
495          * is set to 8 bytes, transfers shorter than 8 bytes are transfered
496          * using PIO mode while longer transfers use DMA. The 8 byte border is
497          * based on this empirical measurement and a lot of previous frobbing.
498          */
499         i2c->cmd_err = 0;
500         if (msg->len < 8) {
501                 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
502                 if (ret)
503                         mxs_i2c_reset(i2c);
504         } else {
505                 INIT_COMPLETION(i2c->cmd_complete);
506                 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
507                 if (ret)
508                         return ret;
509
510                 ret = wait_for_completion_timeout(&i2c->cmd_complete,
511                                                 msecs_to_jiffies(1000));
512                 if (ret == 0)
513                         goto timeout;
514         }
515
516         if (i2c->cmd_err == -ENXIO) {
517                 /*
518                  * If the transfer fails with a NAK from the slave the
519                  * controller halts until it gets told to return to idle state.
520                  */
521                 writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
522                        i2c->regs + MXS_I2C_CTRL1_SET);
523         }
524
525         ret = i2c->cmd_err;
526
527         dev_dbg(i2c->dev, "Done with err=%d\n", ret);
528
529         return ret;
530
531 timeout:
532         dev_dbg(i2c->dev, "Timeout!\n");
533         mxs_i2c_dma_finish(i2c);
534         mxs_i2c_reset(i2c);
535         return -ETIMEDOUT;
536 }
537
538 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
539                         int num)
540 {
541         int i;
542         int err;
543
544         for (i = 0; i < num; i++) {
545                 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
546                 if (err)
547                         return err;
548         }
549
550         return num;
551 }
552
553 static u32 mxs_i2c_func(struct i2c_adapter *adap)
554 {
555         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
556 }
557
558 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
559 {
560         struct mxs_i2c_dev *i2c = dev_id;
561         u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
562
563         if (!stat)
564                 return IRQ_NONE;
565
566         if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
567                 i2c->cmd_err = -ENXIO;
568         else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
569                     MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
570                     MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
571                 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
572                 i2c->cmd_err = -EIO;
573
574         writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
575
576         return IRQ_HANDLED;
577 }
578
579 static const struct i2c_algorithm mxs_i2c_algo = {
580         .master_xfer = mxs_i2c_xfer,
581         .functionality = mxs_i2c_func,
582 };
583
584 static bool mxs_i2c_dma_filter(struct dma_chan *chan, void *param)
585 {
586         struct mxs_i2c_dev *i2c = param;
587
588         if (!mxs_dma_is_apbx(chan))
589                 return false;
590
591         if (chan->chan_id != i2c->dma_channel)
592                 return false;
593
594         chan->private = &i2c->dma_data;
595
596         return true;
597 }
598
599 static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, int speed)
600 {
601         /* The I2C block clock run at 24MHz */
602         const uint32_t clk = 24000000;
603         uint32_t base;
604         uint16_t high_count, low_count, rcv_count, xmit_count;
605         struct device *dev = i2c->dev;
606
607         if (speed > 540000) {
608                 dev_warn(dev, "Speed too high (%d Hz), using 540 kHz\n", speed);
609                 speed = 540000;
610         } else if (speed < 12000) {
611                 dev_warn(dev, "Speed too low (%d Hz), using 12 kHz\n", speed);
612                 speed = 12000;
613         }
614
615         /*
616          * The timing derivation algorithm. There is no documentation for this
617          * algorithm available, it was derived by using the scope and fiddling
618          * with constants until the result observed on the scope was good enough
619          * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
620          * possible to assume the algorithm works for other frequencies as well.
621          *
622          * Note it was necessary to cap the frequency on both ends as it's not
623          * possible to configure completely arbitrary frequency for the I2C bus
624          * clock.
625          */
626         base = ((clk / speed) - 38) / 2;
627         high_count = base + 3;
628         low_count = base - 3;
629         rcv_count = (high_count * 3) / 4;
630         xmit_count = low_count / 4;
631
632         i2c->timing0 = (high_count << 16) | rcv_count;
633         i2c->timing1 = (low_count << 16) | xmit_count;
634 }
635
636 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
637 {
638         uint32_t speed;
639         struct device *dev = i2c->dev;
640         struct device_node *node = dev->of_node;
641         int ret;
642
643         /*
644          * TODO: This is a temporary solution and should be changed
645          * to use generic DMA binding later when the helpers get in.
646          */
647         ret = of_property_read_u32(node, "fsl,i2c-dma-channel",
648                                    &i2c->dma_channel);
649         if (ret) {
650                 dev_err(dev, "Failed to get DMA channel!\n");
651                 return -ENODEV;
652         }
653
654         ret = of_property_read_u32(node, "clock-frequency", &speed);
655         if (ret) {
656                 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
657                 speed = 100000;
658         }
659
660         mxs_i2c_derive_timing(i2c, speed);
661
662         return 0;
663 }
664
665 static int mxs_i2c_probe(struct platform_device *pdev)
666 {
667         struct device *dev = &pdev->dev;
668         struct mxs_i2c_dev *i2c;
669         struct i2c_adapter *adap;
670         struct pinctrl *pinctrl;
671         struct resource *res;
672         resource_size_t res_size;
673         int err, irq, dmairq;
674         dma_cap_mask_t mask;
675
676         pinctrl = devm_pinctrl_get_select_default(dev);
677         if (IS_ERR(pinctrl))
678                 return PTR_ERR(pinctrl);
679
680         i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
681         if (!i2c)
682                 return -ENOMEM;
683
684         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
685         irq = platform_get_irq(pdev, 0);
686         dmairq = platform_get_irq(pdev, 1);
687
688         if (!res || irq < 0 || dmairq < 0)
689                 return -ENOENT;
690
691         res_size = resource_size(res);
692         if (!devm_request_mem_region(dev, res->start, res_size, res->name))
693                 return -EBUSY;
694
695         i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
696         if (!i2c->regs)
697                 return -EBUSY;
698
699         err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
700         if (err)
701                 return err;
702
703         i2c->dev = dev;
704
705         init_completion(&i2c->cmd_complete);
706
707         if (dev->of_node) {
708                 err = mxs_i2c_get_ofdata(i2c);
709                 if (err)
710                         return err;
711         }
712
713         /* Setup the DMA */
714         dma_cap_zero(mask);
715         dma_cap_set(DMA_SLAVE, mask);
716         i2c->dma_data.chan_irq = dmairq;
717         i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c);
718         if (!i2c->dmach) {
719                 dev_err(dev, "Failed to request dma\n");
720                 return -ENODEV;
721         }
722
723         platform_set_drvdata(pdev, i2c);
724
725         /* Do reset to enforce correct startup after pinmuxing */
726         mxs_i2c_reset(i2c);
727
728         adap = &i2c->adapter;
729         strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
730         adap->owner = THIS_MODULE;
731         adap->algo = &mxs_i2c_algo;
732         adap->dev.parent = dev;
733         adap->nr = pdev->id;
734         adap->dev.of_node = pdev->dev.of_node;
735         i2c_set_adapdata(adap, i2c);
736         err = i2c_add_numbered_adapter(adap);
737         if (err) {
738                 dev_err(dev, "Failed to add adapter (%d)\n", err);
739                 writel(MXS_I2C_CTRL0_SFTRST,
740                                 i2c->regs + MXS_I2C_CTRL0_SET);
741                 return err;
742         }
743
744         of_i2c_register_devices(adap);
745
746         return 0;
747 }
748
749 static int mxs_i2c_remove(struct platform_device *pdev)
750 {
751         struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
752
753         i2c_del_adapter(&i2c->adapter);
754
755         if (i2c->dmach)
756                 dma_release_channel(i2c->dmach);
757
758         writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
759
760         return 0;
761 }
762
763 static const struct of_device_id mxs_i2c_dt_ids[] = {
764         { .compatible = "fsl,imx28-i2c", },
765         { /* sentinel */ }
766 };
767 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
768
769 static struct platform_driver mxs_i2c_driver = {
770         .driver = {
771                    .name = DRIVER_NAME,
772                    .owner = THIS_MODULE,
773                    .of_match_table = mxs_i2c_dt_ids,
774                    },
775         .remove = mxs_i2c_remove,
776 };
777
778 static int __init mxs_i2c_init(void)
779 {
780         return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
781 }
782 subsys_initcall(mxs_i2c_init);
783
784 static void __exit mxs_i2c_exit(void)
785 {
786         platform_driver_unregister(&mxs_i2c_driver);
787 }
788 module_exit(mxs_i2c_exit);
789
790 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
791 MODULE_DESCRIPTION("MXS I2C Bus Driver");
792 MODULE_LICENSE("GPL");
793 MODULE_ALIAS("platform:" DRIVER_NAME);