2 * Freescale MXS I2C bus driver
4 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
6 * based on a (non-working) driver which was:
8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
17 #include <linux/slab.h>
18 #include <linux/device.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/completion.h>
24 #include <linux/platform_device.h>
25 #include <linux/jiffies.h>
27 #include <linux/stmp_device.h>
29 #include <linux/of_device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
33 #define DRIVER_NAME "mxs-i2c"
35 #define MXS_I2C_CTRL0 (0x00)
36 #define MXS_I2C_CTRL0_SET (0x04)
38 #define MXS_I2C_CTRL0_SFTRST 0x80000000
39 #define MXS_I2C_CTRL0_RUN 0x20000000
40 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
41 #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
42 #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
43 #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
44 #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
45 #define MXS_I2C_CTRL0_DIRECTION 0x00010000
46 #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
48 #define MXS_I2C_TIMING0 (0x10)
49 #define MXS_I2C_TIMING1 (0x20)
50 #define MXS_I2C_TIMING2 (0x30)
52 #define MXS_I2C_CTRL1 (0x40)
53 #define MXS_I2C_CTRL1_SET (0x44)
54 #define MXS_I2C_CTRL1_CLR (0x48)
56 #define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
57 #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
58 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
59 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
60 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
61 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
62 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
63 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
64 #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
66 #define MXS_I2C_STAT (0x50)
67 #define MXS_I2C_STAT_BUS_BUSY 0x00000800
68 #define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400
70 #define MXS_I2C_DATA (0xa0)
72 #define MXS_I2C_DEBUG0 (0xb0)
73 #define MXS_I2C_DEBUG0_CLR (0xb8)
75 #define MXS_I2C_DEBUG0_DMAREQ 0x80000000
77 #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
78 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
79 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
80 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
81 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
82 MXS_I2C_CTRL1_SLAVE_IRQ)
85 #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
86 MXS_I2C_CTRL0_PRE_SEND_START | \
87 MXS_I2C_CTRL0_MASTER_MODE | \
88 MXS_I2C_CTRL0_DIRECTION | \
89 MXS_I2C_CTRL0_XFER_COUNT(1))
91 #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
92 MXS_I2C_CTRL0_MASTER_MODE | \
93 MXS_I2C_CTRL0_DIRECTION)
95 #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
96 MXS_I2C_CTRL0_MASTER_MODE)
99 * struct mxs_i2c_dev - per device, private MXS-I2C data
101 * @dev: driver model device node
102 * @regs: IO registers pointer
103 * @cmd_complete: completion object for transaction wait
104 * @cmd_err: error code for last transaction
105 * @adapter: i2c subsystem adapter node
110 struct completion cmd_complete;
112 struct i2c_adapter adapter;
118 /* DMA support components */
119 struct dma_chan *dmach;
120 uint32_t pio_data[2];
122 struct scatterlist sg_io[2];
126 static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)
128 int ret = stmp_reset_block(i2c->regs);
133 * Configure timing for the I2C block. The I2C TIMING2 register has to
134 * be programmed with this particular magic number. The rest is derived
135 * from the XTAL speed and requested I2C speed.
137 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
139 writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
140 writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
141 writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
143 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
148 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
151 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
152 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
154 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
158 static void mxs_i2c_dma_irq_callback(void *param)
160 struct mxs_i2c_dev *i2c = param;
162 complete(&i2c->cmd_complete);
163 mxs_i2c_dma_finish(i2c);
166 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
167 struct i2c_msg *msg, uint32_t flags)
169 struct dma_async_tx_descriptor *desc;
170 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
172 if (msg->flags & I2C_M_RD) {
174 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
180 /* Queue the PIO register write transfer. */
181 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
182 desc = dmaengine_prep_slave_sg(i2c->dmach,
183 (struct scatterlist *)&i2c->pio_data[0],
184 1, DMA_TRANS_NONE, 0);
187 "Failed to get PIO reg. write descriptor.\n");
188 goto select_init_pio_fail;
191 /* Queue the DMA data transfer. */
192 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
193 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
194 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
196 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
199 "Failed to get DMA data write descriptor.\n");
200 goto select_init_dma_fail;
207 /* Queue the PIO register write transfer. */
208 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
209 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
210 desc = dmaengine_prep_slave_sg(i2c->dmach,
211 (struct scatterlist *)&i2c->pio_data[1],
212 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
215 "Failed to get PIO reg. write descriptor.\n");
216 goto select_init_dma_fail;
219 /* Queue the DMA data transfer. */
220 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
221 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
222 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
224 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
227 "Failed to get DMA data write descriptor.\n");
228 goto read_init_dma_fail;
232 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
238 /* Queue the PIO register write transfer. */
239 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
240 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
241 desc = dmaengine_prep_slave_sg(i2c->dmach,
242 (struct scatterlist *)&i2c->pio_data[0],
243 1, DMA_TRANS_NONE, 0);
246 "Failed to get PIO reg. write descriptor.\n");
247 goto write_init_pio_fail;
250 /* Queue the DMA data transfer. */
251 sg_init_table(i2c->sg_io, 2);
252 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
253 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
254 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
255 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
257 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
260 "Failed to get DMA data write descriptor.\n");
261 goto write_init_dma_fail;
266 * The last descriptor must have this callback,
267 * to finish the DMA transaction.
269 desc->callback = mxs_i2c_dma_irq_callback;
270 desc->callback_param = i2c;
272 /* Start the transfer. */
273 dmaengine_submit(desc);
274 dma_async_issue_pending(i2c->dmach);
279 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
280 select_init_dma_fail:
281 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
282 select_init_pio_fail:
283 dmaengine_terminate_all(i2c->dmach);
286 /* Write failpath. */
288 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
290 dmaengine_terminate_all(i2c->dmach);
294 static int mxs_i2c_pio_wait_dmareq(struct mxs_i2c_dev *i2c)
296 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
298 while (!(readl(i2c->regs + MXS_I2C_DEBUG0) &
299 MXS_I2C_DEBUG0_DMAREQ)) {
300 if (time_after(jiffies, timeout))
308 static int mxs_i2c_pio_wait_cplt(struct mxs_i2c_dev *i2c, int last)
310 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
313 * We do not use interrupts in the PIO mode. Due to the
314 * maximum transfer length being 8 bytes in PIO mode, the
315 * overhead of interrupt would be too large and this would
316 * neglect the gain from using the PIO mode.
319 while (!(readl(i2c->regs + MXS_I2C_CTRL1) &
320 MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)) {
321 if (time_after(jiffies, timeout))
326 writel(MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ,
327 i2c->regs + MXS_I2C_CTRL1_CLR);
330 * When ending a transfer with a stop, we have to wait for the bus to
331 * go idle before we report the transfer as completed. Otherwise the
332 * start of the next transfer may race with the end of the current one.
334 while (last && (readl(i2c->regs + MXS_I2C_STAT) &
335 (MXS_I2C_STAT_BUS_BUSY | MXS_I2C_STAT_CLK_GEN_BUSY))) {
336 if (time_after(jiffies, timeout))
344 static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
348 state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
350 if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
351 i2c->cmd_err = -ENXIO;
352 else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
353 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
354 MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
355 MXS_I2C_CTRL1_SLAVE_IRQ))
361 static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
365 writel(cmd, i2c->regs + MXS_I2C_CTRL0);
367 /* readback makes sure the write is latched into hardware */
368 reg = readl(i2c->regs + MXS_I2C_CTRL0);
369 reg |= MXS_I2C_CTRL0_RUN;
370 writel(reg, i2c->regs + MXS_I2C_CTRL0);
373 static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
374 struct i2c_msg *msg, uint32_t flags)
376 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
377 uint32_t addr_data = msg->addr << 1;
379 int i, shifts_left, ret;
381 /* Mute IRQs coming from this block. */
382 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
384 if (msg->flags & I2C_M_RD) {
385 addr_data |= I2C_SMBUS_READ;
387 /* SELECT command. */
388 mxs_i2c_pio_trigger_cmd(i2c, MXS_CMD_I2C_SELECT);
390 ret = mxs_i2c_pio_wait_dmareq(i2c);
394 writel(addr_data, i2c->regs + MXS_I2C_DATA);
395 writel(MXS_I2C_DEBUG0_DMAREQ, i2c->regs + MXS_I2C_DEBUG0_CLR);
397 ret = mxs_i2c_pio_wait_cplt(i2c, 0);
401 if (mxs_i2c_pio_check_error_state(i2c))
405 mxs_i2c_pio_trigger_cmd(i2c,
406 MXS_CMD_I2C_READ | flags |
407 MXS_I2C_CTRL0_XFER_COUNT(msg->len));
409 for (i = 0; i < msg->len; i++) {
411 ret = mxs_i2c_pio_wait_dmareq(i2c);
414 data = readl(i2c->regs + MXS_I2C_DATA);
415 writel(MXS_I2C_DEBUG0_DMAREQ,
416 i2c->regs + MXS_I2C_DEBUG0_CLR);
418 msg->buf[i] = data & 0xff;
422 addr_data |= I2C_SMBUS_WRITE;
425 mxs_i2c_pio_trigger_cmd(i2c,
426 MXS_CMD_I2C_WRITE | flags |
427 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1));
430 * The LSB of data buffer is the first byte blasted across
431 * the bus. Higher order bytes follow. Thus the following
434 data = addr_data << 24;
435 for (i = 0; i < msg->len; i++) {
437 data |= (msg->buf[i] << 24);
439 ret = mxs_i2c_pio_wait_dmareq(i2c);
442 writel(data, i2c->regs + MXS_I2C_DATA);
443 writel(MXS_I2C_DEBUG0_DMAREQ,
444 i2c->regs + MXS_I2C_DEBUG0_CLR);
448 shifts_left = 24 - (i & 3) * 8;
450 data >>= shifts_left;
451 ret = mxs_i2c_pio_wait_dmareq(i2c);
454 writel(data, i2c->regs + MXS_I2C_DATA);
455 writel(MXS_I2C_DEBUG0_DMAREQ,
456 i2c->regs + MXS_I2C_DEBUG0_CLR);
460 ret = mxs_i2c_pio_wait_cplt(i2c, flags & MXS_I2C_CTRL0_POST_SEND_STOP);
464 /* make sure we capture any occurred error into cmd_err */
465 mxs_i2c_pio_check_error_state(i2c);
468 /* Clear any dangling IRQs and re-enable interrupts. */
469 writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
470 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
476 * Low level master read/write transaction.
478 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
481 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
485 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
487 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
488 msg->addr, msg->len, msg->flags, stop);
494 * The current boundary to select between PIO/DMA transfer method
495 * is set to 8 bytes, transfers shorter than 8 bytes are transfered
496 * using PIO mode while longer transfers use DMA. The 8 byte border is
497 * based on this empirical measurement and a lot of previous frobbing.
500 if (0) { /* disable PIO mode until a proper fix is made */
501 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
503 err = mxs_i2c_reset(i2c);
508 INIT_COMPLETION(i2c->cmd_complete);
509 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
513 ret = wait_for_completion_timeout(&i2c->cmd_complete,
514 msecs_to_jiffies(1000));
519 if (i2c->cmd_err == -ENXIO) {
521 * If the transfer fails with a NAK from the slave the
522 * controller halts until it gets told to return to idle state.
524 writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
525 i2c->regs + MXS_I2C_CTRL1_SET);
530 dev_dbg(i2c->dev, "Done with err=%d\n", ret);
535 dev_dbg(i2c->dev, "Timeout!\n");
536 mxs_i2c_dma_finish(i2c);
537 ret = mxs_i2c_reset(i2c);
544 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
550 for (i = 0; i < num; i++) {
551 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
559 static u32 mxs_i2c_func(struct i2c_adapter *adap)
561 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
564 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
566 struct mxs_i2c_dev *i2c = dev_id;
567 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
572 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
573 i2c->cmd_err = -ENXIO;
574 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
575 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
576 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
577 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
580 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
585 static const struct i2c_algorithm mxs_i2c_algo = {
586 .master_xfer = mxs_i2c_xfer,
587 .functionality = mxs_i2c_func,
590 static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)
592 /* The I2C block clock runs at 24MHz */
593 const uint32_t clk = 24000000;
595 uint16_t high_count, low_count, rcv_count, xmit_count;
596 uint32_t bus_free, leadin;
597 struct device *dev = i2c->dev;
599 divider = DIV_ROUND_UP(clk, speed);
603 * limit the divider, so that min(low_count, high_count)
608 "Speed too high (%u.%03u kHz), using %u.%03u kHz\n",
609 speed / 1000, speed % 1000,
610 clk / divider / 1000, clk / divider % 1000);
611 } else if (divider > 1897) {
613 * limit the divider, so that max(low_count, high_count)
618 "Speed too low (%u.%03u kHz), using %u.%03u kHz\n",
619 speed / 1000, speed % 1000,
620 clk / divider / 1000, clk / divider % 1000);
624 * The I2C spec specifies the following timing data:
625 * standard mode fast mode Bitfield name
626 * tLOW (SCL LOW period) 4700 ns 1300 ns
627 * tHIGH (SCL HIGH period) 4000 ns 600 ns
628 * tSU;DAT (data setup time) 250 ns 100 ns
629 * tHD;STA (START hold time) 4000 ns 600 ns
630 * tBUF (bus free time) 4700 ns 1300 ns
632 * The hardware (of the i.MX28 at least) seems to add 2 additional
633 * clock cycles to the low_count and 7 cycles to the high_count.
634 * This is compensated for by subtracting the respective constants
635 * from the values written to the timing registers.
637 if (speed > 100000) {
639 low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
640 high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
641 leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);
642 bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);
645 low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
646 high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
647 leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
648 bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
650 rcv_count = high_count * 3 / 8;
651 xmit_count = low_count * 3 / 8;
654 "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",
655 speed, clk / divider, divider, low_count, high_count,
656 xmit_count, rcv_count, leadin, bus_free);
660 i2c->timing0 = (high_count << 16) | rcv_count;
661 i2c->timing1 = (low_count << 16) | xmit_count;
662 i2c->timing2 = (bus_free << 16 | leadin);
665 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
668 struct device *dev = i2c->dev;
669 struct device_node *node = dev->of_node;
672 ret = of_property_read_u32(node, "clock-frequency", &speed);
674 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
678 mxs_i2c_derive_timing(i2c, speed);
683 static int mxs_i2c_probe(struct platform_device *pdev)
685 struct device *dev = &pdev->dev;
686 struct mxs_i2c_dev *i2c;
687 struct i2c_adapter *adap;
688 struct resource *res;
689 resource_size_t res_size;
692 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
696 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
697 irq = platform_get_irq(pdev, 0);
702 res_size = resource_size(res);
703 if (!devm_request_mem_region(dev, res->start, res_size, res->name))
706 i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
710 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
716 init_completion(&i2c->cmd_complete);
719 err = mxs_i2c_get_ofdata(i2c);
725 i2c->dmach = dma_request_slave_channel(dev, "rx-tx");
727 dev_err(dev, "Failed to request dma\n");
731 platform_set_drvdata(pdev, i2c);
733 /* Do reset to enforce correct startup after pinmuxing */
734 err = mxs_i2c_reset(i2c);
738 adap = &i2c->adapter;
739 strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
740 adap->owner = THIS_MODULE;
741 adap->algo = &mxs_i2c_algo;
742 adap->dev.parent = dev;
744 adap->dev.of_node = pdev->dev.of_node;
745 i2c_set_adapdata(adap, i2c);
746 err = i2c_add_numbered_adapter(adap);
748 dev_err(dev, "Failed to add adapter (%d)\n", err);
749 writel(MXS_I2C_CTRL0_SFTRST,
750 i2c->regs + MXS_I2C_CTRL0_SET);
757 static int mxs_i2c_remove(struct platform_device *pdev)
759 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
761 i2c_del_adapter(&i2c->adapter);
764 dma_release_channel(i2c->dmach);
766 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
771 static const struct of_device_id mxs_i2c_dt_ids[] = {
772 { .compatible = "fsl,imx28-i2c", },
775 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
777 static struct platform_driver mxs_i2c_driver = {
780 .owner = THIS_MODULE,
781 .of_match_table = mxs_i2c_dt_ids,
783 .remove = mxs_i2c_remove,
786 static int __init mxs_i2c_init(void)
788 return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
790 subsys_initcall(mxs_i2c_init);
792 static void __exit mxs_i2c_exit(void)
794 platform_driver_unregister(&mxs_i2c_driver);
796 module_exit(mxs_i2c_exit);
798 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
799 MODULE_DESCRIPTION("MXS I2C Bus Driver");
800 MODULE_LICENSE("GPL");
801 MODULE_ALIAS("platform:" DRIVER_NAME);