2 * Freescale MXS I2C bus driver
4 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
6 * based on a (non-working) driver which was:
8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
17 #include <linux/slab.h>
18 #include <linux/device.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/completion.h>
24 #include <linux/platform_device.h>
25 #include <linux/jiffies.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/stmp_device.h>
30 #include <linux/of_device.h>
31 #include <linux/of_i2c.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dmaengine.h>
34 #include <linux/fsl/mxs-dma.h>
36 #define DRIVER_NAME "mxs-i2c"
38 #define MXS_I2C_CTRL0 (0x00)
39 #define MXS_I2C_CTRL0_SET (0x04)
41 #define MXS_I2C_CTRL0_SFTRST 0x80000000
42 #define MXS_I2C_CTRL0_RUN 0x20000000
43 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
44 #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
45 #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
46 #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
47 #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
48 #define MXS_I2C_CTRL0_DIRECTION 0x00010000
49 #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
51 #define MXS_I2C_TIMING0 (0x10)
52 #define MXS_I2C_TIMING1 (0x20)
53 #define MXS_I2C_TIMING2 (0x30)
55 #define MXS_I2C_CTRL1 (0x40)
56 #define MXS_I2C_CTRL1_SET (0x44)
57 #define MXS_I2C_CTRL1_CLR (0x48)
59 #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
60 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
61 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
62 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
63 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
64 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
65 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
66 #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
68 #define MXS_I2C_DATA (0xa0)
70 #define MXS_I2C_DEBUG0 (0xb0)
71 #define MXS_I2C_DEBUG0_CLR (0xb8)
73 #define MXS_I2C_DEBUG0_DMAREQ 0x80000000
75 #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
76 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
77 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
78 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
79 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
80 MXS_I2C_CTRL1_SLAVE_IRQ)
83 #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
84 MXS_I2C_CTRL0_PRE_SEND_START | \
85 MXS_I2C_CTRL0_MASTER_MODE | \
86 MXS_I2C_CTRL0_DIRECTION | \
87 MXS_I2C_CTRL0_XFER_COUNT(1))
89 #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
90 MXS_I2C_CTRL0_MASTER_MODE | \
91 MXS_I2C_CTRL0_DIRECTION)
93 #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
94 MXS_I2C_CTRL0_MASTER_MODE)
97 * struct mxs_i2c_dev - per device, private MXS-I2C data
99 * @dev: driver model device node
100 * @regs: IO registers pointer
101 * @cmd_complete: completion object for transaction wait
102 * @cmd_err: error code for last transaction
103 * @adapter: i2c subsystem adapter node
108 struct completion cmd_complete;
110 struct i2c_adapter adapter;
115 /* DMA support components */
117 struct dma_chan *dmach;
118 struct mxs_dma_data dma_data;
119 uint32_t pio_data[2];
121 struct scatterlist sg_io[2];
125 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
127 stmp_reset_block(i2c->regs);
130 * Configure timing for the I2C block. The I2C TIMING2 register has to
131 * be programmed with this particular magic number. The rest is derived
132 * from the XTAL speed and requested I2C speed.
134 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
136 writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
137 writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
138 writel(0x00300030, i2c->regs + MXS_I2C_TIMING2);
140 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
143 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
146 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
147 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
149 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
153 static void mxs_i2c_dma_irq_callback(void *param)
155 struct mxs_i2c_dev *i2c = param;
157 complete(&i2c->cmd_complete);
158 mxs_i2c_dma_finish(i2c);
161 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
162 struct i2c_msg *msg, uint32_t flags)
164 struct dma_async_tx_descriptor *desc;
165 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
167 if (msg->flags & I2C_M_RD) {
169 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
175 /* Queue the PIO register write transfer. */
176 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
177 desc = dmaengine_prep_slave_sg(i2c->dmach,
178 (struct scatterlist *)&i2c->pio_data[0],
179 1, DMA_TRANS_NONE, 0);
182 "Failed to get PIO reg. write descriptor.\n");
183 goto select_init_pio_fail;
186 /* Queue the DMA data transfer. */
187 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
188 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
189 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
191 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
194 "Failed to get DMA data write descriptor.\n");
195 goto select_init_dma_fail;
202 /* Queue the PIO register write transfer. */
203 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
204 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
205 desc = dmaengine_prep_slave_sg(i2c->dmach,
206 (struct scatterlist *)&i2c->pio_data[1],
207 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
210 "Failed to get PIO reg. write descriptor.\n");
211 goto select_init_dma_fail;
214 /* Queue the DMA data transfer. */
215 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
216 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
217 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
219 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
222 "Failed to get DMA data write descriptor.\n");
223 goto read_init_dma_fail;
227 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
233 /* Queue the PIO register write transfer. */
234 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
235 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
236 desc = dmaengine_prep_slave_sg(i2c->dmach,
237 (struct scatterlist *)&i2c->pio_data[0],
238 1, DMA_TRANS_NONE, 0);
241 "Failed to get PIO reg. write descriptor.\n");
242 goto write_init_pio_fail;
245 /* Queue the DMA data transfer. */
246 sg_init_table(i2c->sg_io, 2);
247 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
248 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
249 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
250 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
252 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
255 "Failed to get DMA data write descriptor.\n");
256 goto write_init_dma_fail;
261 * The last descriptor must have this callback,
262 * to finish the DMA transaction.
264 desc->callback = mxs_i2c_dma_irq_callback;
265 desc->callback_param = i2c;
267 /* Start the transfer. */
268 dmaengine_submit(desc);
269 dma_async_issue_pending(i2c->dmach);
274 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
275 select_init_dma_fail:
276 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
277 select_init_pio_fail:
278 dmaengine_terminate_all(i2c->dmach);
281 /* Write failpath. */
283 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
285 dmaengine_terminate_all(i2c->dmach);
289 static int mxs_i2c_pio_wait_dmareq(struct mxs_i2c_dev *i2c)
291 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
293 while (!(readl(i2c->regs + MXS_I2C_DEBUG0) &
294 MXS_I2C_DEBUG0_DMAREQ)) {
295 if (time_after(jiffies, timeout))
300 writel(MXS_I2C_DEBUG0_DMAREQ, i2c->regs + MXS_I2C_DEBUG0_CLR);
305 static int mxs_i2c_pio_wait_cplt(struct mxs_i2c_dev *i2c)
307 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
310 * We do not use interrupts in the PIO mode. Due to the
311 * maximum transfer length being 8 bytes in PIO mode, the
312 * overhead of interrupt would be too large and this would
313 * neglect the gain from using the PIO mode.
316 while (!(readl(i2c->regs + MXS_I2C_CTRL1) &
317 MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)) {
318 if (time_after(jiffies, timeout))
323 writel(MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ,
324 i2c->regs + MXS_I2C_CTRL1_CLR);
329 static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
330 struct i2c_msg *msg, uint32_t flags)
332 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
333 uint32_t addr_data = msg->addr << 1;
335 int i, shifts_left, ret;
337 /* Mute IRQs coming from this block. */
338 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
340 if (msg->flags & I2C_M_RD) {
341 addr_data |= I2C_SMBUS_READ;
343 /* SELECT command. */
344 writel(MXS_I2C_CTRL0_RUN | MXS_CMD_I2C_SELECT,
345 i2c->regs + MXS_I2C_CTRL0);
347 ret = mxs_i2c_pio_wait_dmareq(i2c);
351 writel(addr_data, i2c->regs + MXS_I2C_DATA);
353 ret = mxs_i2c_pio_wait_cplt(i2c);
358 writel(MXS_I2C_CTRL0_RUN | MXS_CMD_I2C_READ | flags |
359 MXS_I2C_CTRL0_XFER_COUNT(msg->len),
360 i2c->regs + MXS_I2C_CTRL0);
362 for (i = 0; i < msg->len; i++) {
364 ret = mxs_i2c_pio_wait_dmareq(i2c);
367 data = readl(i2c->regs + MXS_I2C_DATA);
369 msg->buf[i] = data & 0xff;
373 addr_data |= I2C_SMBUS_WRITE;
376 writel(MXS_I2C_CTRL0_RUN | MXS_CMD_I2C_WRITE | flags |
377 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1),
378 i2c->regs + MXS_I2C_CTRL0);
381 * The LSB of data buffer is the first byte blasted across
382 * the bus. Higher order bytes follow. Thus the following
385 data = addr_data << 24;
386 for (i = 0; i < msg->len; i++) {
388 data |= (msg->buf[i] << 24);
390 ret = mxs_i2c_pio_wait_dmareq(i2c);
393 writel(data, i2c->regs + MXS_I2C_DATA);
397 shifts_left = 24 - (i & 3) * 8;
399 data >>= shifts_left;
400 ret = mxs_i2c_pio_wait_dmareq(i2c);
403 writel(data, i2c->regs + MXS_I2C_DATA);
407 ret = mxs_i2c_pio_wait_cplt(i2c);
411 /* Clear any dangling IRQs and re-enable interrupts. */
412 writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
413 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
419 * Low level master read/write transaction.
421 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
424 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
428 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
430 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
431 msg->addr, msg->len, msg->flags, stop);
437 * The current boundary to select between PIO/DMA transfer method
438 * is set to 8 bytes, transfers shorter than 8 bytes are transfered
439 * using PIO mode while longer transfers use DMA. The 8 byte border is
440 * based on this empirical measurement and a lot of previous frobbing.
443 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
448 INIT_COMPLETION(i2c->cmd_complete);
449 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
453 ret = wait_for_completion_timeout(&i2c->cmd_complete,
454 msecs_to_jiffies(1000));
458 if (i2c->cmd_err == -ENXIO)
464 dev_dbg(i2c->dev, "Done with err=%d\n", ret);
469 dev_dbg(i2c->dev, "Timeout!\n");
470 mxs_i2c_dma_finish(i2c);
475 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
481 for (i = 0; i < num; i++) {
482 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
490 static u32 mxs_i2c_func(struct i2c_adapter *adap)
492 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
495 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
497 struct mxs_i2c_dev *i2c = dev_id;
498 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
503 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
504 i2c->cmd_err = -ENXIO;
505 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
506 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
507 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
508 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
511 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
516 static const struct i2c_algorithm mxs_i2c_algo = {
517 .master_xfer = mxs_i2c_xfer,
518 .functionality = mxs_i2c_func,
521 static bool mxs_i2c_dma_filter(struct dma_chan *chan, void *param)
523 struct mxs_i2c_dev *i2c = param;
525 if (!mxs_dma_is_apbx(chan))
528 if (chan->chan_id != i2c->dma_channel)
531 chan->private = &i2c->dma_data;
536 static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, int speed)
538 /* The I2C block clock run at 24MHz */
539 const uint32_t clk = 24000000;
541 uint16_t high_count, low_count, rcv_count, xmit_count;
542 struct device *dev = i2c->dev;
544 if (speed > 540000) {
545 dev_warn(dev, "Speed too high (%d Hz), using 540 kHz\n", speed);
547 } else if (speed < 12000) {
548 dev_warn(dev, "Speed too low (%d Hz), using 12 kHz\n", speed);
553 * The timing derivation algorithm. There is no documentation for this
554 * algorithm available, it was derived by using the scope and fiddling
555 * with constants until the result observed on the scope was good enough
556 * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
557 * possible to assume the algorithm works for other frequencies as well.
559 * Note it was necessary to cap the frequency on both ends as it's not
560 * possible to configure completely arbitrary frequency for the I2C bus
563 base = ((clk / speed) - 38) / 2;
564 high_count = base + 3;
565 low_count = base - 3;
566 rcv_count = (high_count * 3) / 4;
567 xmit_count = low_count / 4;
569 i2c->timing0 = (high_count << 16) | rcv_count;
570 i2c->timing1 = (low_count << 16) | xmit_count;
573 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
576 struct device *dev = i2c->dev;
577 struct device_node *node = dev->of_node;
581 * TODO: This is a temporary solution and should be changed
582 * to use generic DMA binding later when the helpers get in.
584 ret = of_property_read_u32(node, "fsl,i2c-dma-channel",
587 dev_err(dev, "Failed to get DMA channel!\n");
591 ret = of_property_read_u32(node, "clock-frequency", &speed);
593 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
597 mxs_i2c_derive_timing(i2c, speed);
602 static int mxs_i2c_probe(struct platform_device *pdev)
604 struct device *dev = &pdev->dev;
605 struct mxs_i2c_dev *i2c;
606 struct i2c_adapter *adap;
607 struct pinctrl *pinctrl;
608 struct resource *res;
609 resource_size_t res_size;
610 int err, irq, dmairq;
613 pinctrl = devm_pinctrl_get_select_default(dev);
615 return PTR_ERR(pinctrl);
617 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
622 irq = platform_get_irq(pdev, 0);
623 dmairq = platform_get_irq(pdev, 1);
625 if (!res || irq < 0 || dmairq < 0)
628 res_size = resource_size(res);
629 if (!devm_request_mem_region(dev, res->start, res_size, res->name))
632 i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
636 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
642 init_completion(&i2c->cmd_complete);
645 err = mxs_i2c_get_ofdata(i2c);
652 dma_cap_set(DMA_SLAVE, mask);
653 i2c->dma_data.chan_irq = dmairq;
654 i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c);
656 dev_err(dev, "Failed to request dma\n");
660 platform_set_drvdata(pdev, i2c);
662 /* Do reset to enforce correct startup after pinmuxing */
665 adap = &i2c->adapter;
666 strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
667 adap->owner = THIS_MODULE;
668 adap->algo = &mxs_i2c_algo;
669 adap->dev.parent = dev;
671 adap->dev.of_node = pdev->dev.of_node;
672 i2c_set_adapdata(adap, i2c);
673 err = i2c_add_numbered_adapter(adap);
675 dev_err(dev, "Failed to add adapter (%d)\n", err);
676 writel(MXS_I2C_CTRL0_SFTRST,
677 i2c->regs + MXS_I2C_CTRL0_SET);
681 of_i2c_register_devices(adap);
686 static int mxs_i2c_remove(struct platform_device *pdev)
688 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
691 ret = i2c_del_adapter(&i2c->adapter);
696 dma_release_channel(i2c->dmach);
698 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
703 static const struct of_device_id mxs_i2c_dt_ids[] = {
704 { .compatible = "fsl,imx28-i2c", },
707 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
709 static struct platform_driver mxs_i2c_driver = {
712 .owner = THIS_MODULE,
713 .of_match_table = mxs_i2c_dt_ids,
715 .remove = mxs_i2c_remove,
718 static int __init mxs_i2c_init(void)
720 return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
722 subsys_initcall(mxs_i2c_init);
724 static void __exit mxs_i2c_exit(void)
726 platform_driver_unregister(&mxs_i2c_driver);
728 module_exit(mxs_i2c_exit);
730 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
731 MODULE_DESCRIPTION("MXS I2C Bus Driver");
732 MODULE_LICENSE("GPL");
733 MODULE_ALIAS("platform:" DRIVER_NAME);