2 * Copyright (C) 2009 ST-Ericsson SA
3 * Copyright (C) 2009 STMicroelectronics
5 * I2C master mode controller driver, used in Nomadik 8815
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/amba/bus.h>
18 #include <linux/atomic.h>
19 #include <linux/slab.h>
20 #include <linux/interrupt.h>
21 #include <linux/i2c.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/platform_data/i2c-nomadik.h>
28 #include <linux/of_i2c.h>
29 #include <linux/pinctrl/consumer.h>
31 #define DRIVER_NAME "nmk-i2c"
33 /* I2C Controller register offsets */
34 #define I2C_CR (0x000)
35 #define I2C_SCR (0x004)
36 #define I2C_HSMCR (0x008)
37 #define I2C_MCR (0x00C)
38 #define I2C_TFR (0x010)
39 #define I2C_SR (0x014)
40 #define I2C_RFR (0x018)
41 #define I2C_TFTR (0x01C)
42 #define I2C_RFTR (0x020)
43 #define I2C_DMAR (0x024)
44 #define I2C_BRCR (0x028)
45 #define I2C_IMSCR (0x02C)
46 #define I2C_RISR (0x030)
47 #define I2C_MISR (0x034)
48 #define I2C_ICR (0x038)
50 /* Control registers */
51 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
52 #define I2C_CR_OM (0x3 << 1) /* Operating mode */
53 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
54 #define I2C_CR_SM (0x3 << 4) /* Speed mode */
55 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
56 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
57 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
58 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
59 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
60 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
61 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */
62 #define I2C_CR_FON (0x3 << 13) /* Filtering on */
63 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */
65 /* Master controller (MCR) register */
66 #define I2C_MCR_OP (0x1 << 0) /* Operation */
67 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
68 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
69 #define I2C_MCR_SB (0x1 << 11) /* Extended address */
70 #define I2C_MCR_AM (0x3 << 12) /* Address type */
71 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
72 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
74 /* Status register (SR) */
75 #define I2C_SR_OP (0x3 << 0) /* Operation */
76 #define I2C_SR_STATUS (0x3 << 2) /* controller status */
77 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
78 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */
79 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
81 /* Interrupt mask set/clear (IMSCR) bits */
82 #define I2C_IT_TXFE (0x1 << 0)
83 #define I2C_IT_TXFNE (0x1 << 1)
84 #define I2C_IT_TXFF (0x1 << 2)
85 #define I2C_IT_TXFOVR (0x1 << 3)
86 #define I2C_IT_RXFE (0x1 << 4)
87 #define I2C_IT_RXFNF (0x1 << 5)
88 #define I2C_IT_RXFF (0x1 << 6)
89 #define I2C_IT_RFSR (0x1 << 16)
90 #define I2C_IT_RFSE (0x1 << 17)
91 #define I2C_IT_WTSR (0x1 << 18)
92 #define I2C_IT_MTD (0x1 << 19)
93 #define I2C_IT_STD (0x1 << 20)
94 #define I2C_IT_MAL (0x1 << 24)
95 #define I2C_IT_BERR (0x1 << 25)
96 #define I2C_IT_MTDWS (0x1 << 28)
98 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
100 /* some bits in ICR are reserved */
101 #define I2C_CLEAR_ALL_INTS 0x131f007f
103 /* first three msb bits are reserved */
104 #define IRQ_MASK(mask) (mask & 0x1fffffff)
106 /* maximum threshold value */
107 #define MAX_I2C_FIFO_THRESHOLD 15
118 I2C_NO_OPERATION = 0xff,
124 * struct i2c_nmk_client - client specific data
125 * @slave_adr: 7-bit slave address
126 * @count: no. bytes to be transferred
127 * @buffer: client data buffer
128 * @xfer_bytes: bytes transferred till now
129 * @operation: current I2C operation
131 struct i2c_nmk_client {
132 unsigned short slave_adr;
134 unsigned char *buffer;
135 unsigned long xfer_bytes;
136 enum i2c_operation operation;
140 * struct nmk_i2c_dev - private data structure of the controller.
141 * @adev: parent amba device.
142 * @adap: corresponding I2C adapter.
143 * @irq: interrupt line for the controller.
144 * @virtbase: virtual io memory area.
145 * @clk: hardware i2c block clock.
146 * @cfg: machine provided controller configuration.
147 * @cli: holder of client specific data.
148 * @stop: stop condition.
149 * @xfer_complete: acknowledge completion for a I2C message.
150 * @result: controller propogated result.
151 * @busy: Busy doing transfer.
154 struct amba_device *adev;
155 struct i2c_adapter adap;
157 void __iomem *virtbase;
159 struct nmk_i2c_controller cfg;
160 struct i2c_nmk_client cli;
162 struct completion xfer_complete;
167 /* controller's abort causes */
168 static const char *abort_causes[] = {
169 "no ack received after address transmission",
170 "no ack received during data phase",
171 "ack received after xmission of master code",
172 "master lost arbitration",
175 "overflow, maxsize is 2047 bytes",
178 static inline void i2c_set_bit(void __iomem *reg, u32 mask)
180 writel(readl(reg) | mask, reg);
183 static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
185 writel(readl(reg) & ~mask, reg);
189 * flush_i2c_fifo() - This function flushes the I2C FIFO
190 * @dev: private data of I2C Driver
192 * This function flushes the I2C Tx and Rx FIFOs. It returns
193 * 0 on successful flushing of FIFO
195 static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
197 #define LOOP_ATTEMPTS 10
199 unsigned long timeout;
202 * flush the transmit and receive FIFO. The flushing
203 * operation takes several cycles before to be completed.
204 * On the completion, the I2C internal logic clears these
205 * bits, until then no one must access Tx, Rx FIFO and
206 * should poll on these bits waiting for the completion.
208 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
210 for (i = 0; i < LOOP_ATTEMPTS; i++) {
211 timeout = jiffies + dev->adap.timeout;
213 while (!time_after(jiffies, timeout)) {
214 if ((readl(dev->virtbase + I2C_CR) &
215 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
220 dev_err(&dev->adev->dev,
221 "flushing operation timed out giving up after %d attempts",
228 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
229 * @dev: private data of I2C Driver
231 static void disable_all_interrupts(struct nmk_i2c_dev *dev)
233 u32 mask = IRQ_MASK(0);
234 writel(mask, dev->virtbase + I2C_IMSCR);
238 * clear_all_interrupts() - Clear all interrupts of I2C Controller
239 * @dev: private data of I2C Driver
241 static void clear_all_interrupts(struct nmk_i2c_dev *dev)
244 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
245 writel(mask, dev->virtbase + I2C_ICR);
249 * init_hw() - initialize the I2C hardware
250 * @dev: private data of I2C Driver
252 static int init_hw(struct nmk_i2c_dev *dev)
256 stat = flush_i2c_fifo(dev);
260 /* disable the controller */
261 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
263 disable_all_interrupts(dev);
265 clear_all_interrupts(dev);
267 dev->cli.operation = I2C_NO_OPERATION;
273 /* enable peripheral, master mode operation */
274 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
277 * load_i2c_mcr_reg() - load the MCR register
278 * @dev: private data of controller
279 * @flags: message flags
281 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
284 unsigned short slave_adr_3msb_bits;
286 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
288 if (unlikely(flags & I2C_M_TEN)) {
289 /* 10-bit address transaction */
290 mcr |= GEN_MASK(2, I2C_MCR_AM, 12);
292 * Get the top 3 bits.
293 * EA10 represents extended address in MCR. This includes
294 * the extension (MSB bits) of the 7 bit address loaded
297 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
299 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
301 /* 7-bit address transaction */
302 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
305 /* start byte procedure not applied */
306 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
308 /* check the operation, master read/write? */
309 if (dev->cli.operation == I2C_WRITE)
310 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
312 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
314 /* stop or repeated start? */
316 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
318 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
320 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
326 * setup_i2c_controller() - setup the controller
327 * @dev: private data of controller
329 static void setup_i2c_controller(struct nmk_i2c_dev *dev)
334 writel(0x0, dev->virtbase + I2C_CR);
335 writel(0x0, dev->virtbase + I2C_HSMCR);
336 writel(0x0, dev->virtbase + I2C_TFTR);
337 writel(0x0, dev->virtbase + I2C_RFTR);
338 writel(0x0, dev->virtbase + I2C_DMAR);
343 * slsu defines the data setup time after SCL clock
344 * stretching in terms of i2c clk cycles. The
345 * needed setup time for the three modes are 250ns,
346 * 100ns, 10ns respectively thus leading to the values
347 * of 14, 6, 2 for a 48 MHz i2c clk.
349 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
351 i2c_clk = clk_get_rate(dev->clk);
354 * The spec says, in case of std. mode the divider is
355 * 2 whereas it is 3 for fast and fastplus mode of
356 * operation. TODO - high speed support.
358 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
361 * generate the mask for baud rate counters. The controller
362 * has two baud rate counters. One is used for High speed
363 * operation, and the other is for std, fast mode, fast mode
364 * plus operation. Currently we do not supprt high speed mode
368 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
370 /* set the baud rate counter register */
371 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
374 * set the speed mode. Currently we support
375 * only standard and fast mode of operation
376 * TODO - support for fast mode plus (up to 1Mb/s)
377 * and high speed (up to 3.4 Mb/s)
379 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
380 dev_err(&dev->adev->dev,
381 "do not support this mode defaulting to std. mode\n");
382 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
383 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
384 writel(I2C_FREQ_MODE_STANDARD << 4,
385 dev->virtbase + I2C_CR);
387 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
389 /* set the Tx and Rx FIFO threshold */
390 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
391 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
395 * read_i2c() - Read from I2C client device
396 * @dev: private data of I2C Driver
397 * @flags: message flags
399 * This function reads from i2c client device when controller is in
400 * master mode. There is a completion timeout. If there is no transfer
401 * before timeout error is returned.
403 static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
409 mcr = load_i2c_mcr_reg(dev, flags);
410 writel(mcr, dev->virtbase + I2C_MCR);
412 /* load the current CR value */
413 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
414 dev->virtbase + I2C_CR);
416 /* enable the controller */
417 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
419 init_completion(&dev->xfer_complete);
421 /* enable interrupts by setting the mask */
422 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
423 I2C_IT_MAL | I2C_IT_BERR);
426 irq_mask |= I2C_IT_MTD;
428 irq_mask |= I2C_IT_MTDWS;
430 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
432 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
433 dev->virtbase + I2C_IMSCR);
435 timeout = wait_for_completion_timeout(
436 &dev->xfer_complete, dev->adap.timeout);
439 /* Controller timed out */
440 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
447 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
451 for (count = (no_bytes - 2);
453 (dev->cli.count != 0);
455 /* write to the Tx FIFO */
456 writeb(*dev->cli.buffer,
457 dev->virtbase + I2C_TFR);
460 dev->cli.xfer_bytes++;
466 * write_i2c() - Write data to I2C client.
467 * @dev: private data of I2C Driver
468 * @flags: message flags
470 * This function writes data to I2C client
472 static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
478 mcr = load_i2c_mcr_reg(dev, flags);
480 writel(mcr, dev->virtbase + I2C_MCR);
482 /* load the current CR value */
483 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
484 dev->virtbase + I2C_CR);
486 /* enable the controller */
487 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
489 init_completion(&dev->xfer_complete);
491 /* enable interrupts by settings the masks */
492 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
494 /* Fill the TX FIFO with transmit data */
495 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
497 if (dev->cli.count != 0)
498 irq_mask |= I2C_IT_TXFNE;
501 * check if we want to transfer a single or multiple bytes, if so
502 * set the MTDWS bit (Master Transaction Done Without Stop)
503 * to start repeated start operation
506 irq_mask |= I2C_IT_MTD;
508 irq_mask |= I2C_IT_MTDWS;
510 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
512 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
513 dev->virtbase + I2C_IMSCR);
515 timeout = wait_for_completion_timeout(
516 &dev->xfer_complete, dev->adap.timeout);
519 /* Controller timed out */
520 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
529 * nmk_i2c_xfer_one() - transmit a single I2C message
530 * @dev: device with a message encoded into it
531 * @flags: message flags
533 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
537 if (flags & I2C_M_RD) {
539 dev->cli.operation = I2C_READ;
540 status = read_i2c(dev, flags);
542 /* write operation */
543 dev->cli.operation = I2C_WRITE;
544 status = write_i2c(dev, flags);
547 if (status || (dev->result)) {
551 i2c_sr = readl(dev->virtbase + I2C_SR);
553 * Check if the controller I2C operation status
554 * is set to ABORT(11b).
556 if (((i2c_sr >> 2) & 0x3) == 0x3) {
557 /* get the abort cause */
558 cause = (i2c_sr >> 4) & 0x7;
559 dev_err(&dev->adev->dev, "%s\n",
560 cause >= ARRAY_SIZE(abort_causes) ?
562 abort_causes[cause]);
567 status = status ? status : dev->result;
574 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
575 * @i2c_adap: Adapter pointer to the controller
576 * @msgs: Pointer to data to be written.
577 * @num_msgs: Number of messages to be executed
579 * This is the function called by the generic kernel i2c_transfer()
580 * or i2c_smbus...() API calls. Note that this code is protected by the
581 * semaphore set in the kernel i2c_transfer() function.
584 * READ TRANSFER : We impose a restriction of the first message to be the
585 * index message for any read transaction.
586 * - a no index is coded as '0',
587 * - 2byte big endian index is coded as '3'
588 * !!! msg[0].buf holds the actual index.
589 * This is compatible with generic messages of smbus emulator
590 * that send a one byte index.
591 * eg. a I2C transation to read 2 bytes from index 0
593 * msg[0].addr = client->addr;
594 * msg[0].flags = 0x0;
598 * msg[1].addr = client->addr;
599 * msg[1].flags = I2C_M_RD;
601 * msg[1].buf = rd_buff
602 * i2c_transfer(adap, msg, 2);
604 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
605 * If you want to emulate an SMBUS write transaction put the
606 * index as first byte(or first and second) in the payload.
607 * eg. a I2C transation to write 2 bytes from index 1
611 * msg[0].flags = 0x0;
613 * msg[0].buf = wr_buff;
614 * i2c_transfer(adap, msg, 1);
616 * To read or write a block of data (multiple bytes) using SMBUS emulation
617 * please use the i2c_smbus_read_i2c_block_data()
618 * or i2c_smbus_write_i2c_block_data() API
620 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
621 struct i2c_msg msgs[], int num_msgs)
625 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
630 pm_runtime_get_sync(&dev->adev->dev);
632 status = clk_prepare_enable(dev->clk);
634 dev_err(&dev->adev->dev, "can't prepare_enable clock\n");
638 /* Optionaly enable pins to be muxed in and configured */
639 pinctrl_pm_select_default_state(&dev->adev->dev);
641 status = init_hw(dev);
645 /* Attempt three times to send the message queue */
646 for (j = 0; j < 3; j++) {
647 /* setup the i2c controller */
648 setup_i2c_controller(dev);
650 for (i = 0; i < num_msgs; i++) {
651 dev->cli.slave_adr = msgs[i].addr;
652 dev->cli.buffer = msgs[i].buf;
653 dev->cli.count = msgs[i].len;
654 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
657 status = nmk_i2c_xfer_one(dev, msgs[i].flags);
666 clk_disable_unprepare(dev->clk);
668 /* Optionally let pins go into idle state */
669 pinctrl_pm_select_idle_state(&dev->adev->dev);
671 pm_runtime_put_sync(&dev->adev->dev);
675 /* return the no. messages processed */
683 * disable_interrupts() - disable the interrupts
684 * @dev: private data of controller
685 * @irq: interrupt number
687 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
690 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
691 dev->virtbase + I2C_IMSCR);
696 * i2c_irq_handler() - interrupt routine
697 * @irq: interrupt number
698 * @arg: data passed to the handler
700 * This is the interrupt handler for the i2c driver. Currently
701 * it handles the major interrupts like Rx & Tx FIFO management
702 * interrupts, master transaction interrupts, arbitration and
703 * bus error interrupts. The rest of the interrupts are treated as
706 static irqreturn_t i2c_irq_handler(int irq, void *arg)
708 struct nmk_i2c_dev *dev = arg;
713 /* load Tx FIFO and Rx FIFO threshold values */
714 tft = readl(dev->virtbase + I2C_TFTR);
715 rft = readl(dev->virtbase + I2C_RFTR);
717 /* read interrupt status register */
718 misr = readl(dev->virtbase + I2C_MISR);
721 switch ((1 << src)) {
723 /* Transmit FIFO nearly empty interrupt */
726 if (dev->cli.operation == I2C_READ) {
728 * in read operation why do we care for writing?
729 * so disable the Transmit FIFO interrupt
731 disable_interrupts(dev, I2C_IT_TXFNE);
733 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
735 * if done, close the transfer by disabling the
736 * corresponding TXFNE interrupt
738 if (dev->cli.count == 0)
739 disable_interrupts(dev, I2C_IT_TXFNE);
745 * Rx FIFO nearly full interrupt.
746 * This is set when the numer of entries in Rx FIFO is
747 * greater or equal than the threshold value programmed
751 for (count = rft; count > 0; count--) {
752 /* Read the Rx FIFO */
753 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
756 dev->cli.count -= rft;
757 dev->cli.xfer_bytes += rft;
762 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
763 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
766 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
767 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
770 /* Master Transaction Done with/without stop */
773 if (dev->cli.operation == I2C_READ) {
774 while (!(readl(dev->virtbase + I2C_RISR)
776 if (dev->cli.count == 0)
779 readb(dev->virtbase + I2C_RFR);
782 dev->cli.xfer_bytes++;
786 disable_all_interrupts(dev);
787 clear_all_interrupts(dev);
789 if (dev->cli.count) {
791 dev_err(&dev->adev->dev,
792 "%lu bytes still remain to be xfered\n",
796 complete(&dev->xfer_complete);
800 /* Master Arbitration lost interrupt */
805 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
806 complete(&dev->xfer_complete);
811 * Bus Error interrupt.
812 * This happens when an unexpected start/stop condition occurs
813 * during the transaction.
818 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
821 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
822 complete(&dev->xfer_complete);
827 * Tx FIFO overrun interrupt.
828 * This is set when a write operation in Tx FIFO is performed and
829 * the Tx FIFO is full.
835 dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
836 complete(&dev->xfer_complete);
840 /* unhandled interrupts by this driver - TODO*/
848 dev_err(&dev->adev->dev, "unhandled Interrupt\n");
851 dev_err(&dev->adev->dev, "spurious Interrupt..\n");
860 static int nmk_i2c_suspend(struct device *dev)
862 struct amba_device *adev = to_amba_device(dev);
863 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
868 pinctrl_pm_select_sleep_state(dev);
873 static int nmk_i2c_resume(struct device *dev)
875 /* First go to the default state */
876 pinctrl_pm_select_default_state(dev);
877 /* Then let's idle the pins until the next transfer happens */
878 pinctrl_pm_select_idle_state(dev);
883 #define nmk_i2c_suspend NULL
884 #define nmk_i2c_resume NULL
888 * We use noirq so that we suspend late and resume before the wakeup interrupt
889 * to ensure that we do the !pm_runtime_suspended() check in resume before
890 * there has been a regular pm runtime resume (via pm_runtime_get_sync()).
892 static const struct dev_pm_ops nmk_i2c_pm = {
893 .suspend_noirq = nmk_i2c_suspend,
894 .resume_noirq = nmk_i2c_resume,
897 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
899 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
902 static const struct i2c_algorithm nmk_i2c_algo = {
903 .master_xfer = nmk_i2c_xfer,
904 .functionality = nmk_i2c_functionality
907 static struct nmk_i2c_controller u8500_i2c = {
909 * Slave data setup time; 250ns, 100ns, and 10ns, which
910 * is 14, 6 and 2 respectively for a 48Mhz i2c clock.
913 .tft = 1, /* Tx FIFO threshold */
914 .rft = 8, /* Rx FIFO threshold */
915 .clk_freq = 400000, /* fast mode operation */
916 .timeout = 200, /* Slave response timeout(ms) */
917 .sm = I2C_FREQ_MODE_FAST,
920 static void nmk_i2c_of_probe(struct device_node *np,
921 struct nmk_i2c_controller *pdata)
923 of_property_read_u32(np, "clock-frequency", &pdata->clk_freq);
925 /* This driver only supports 'standard' and 'fast' modes of operation. */
926 if (pdata->clk_freq <= 100000)
927 pdata->sm = I2C_FREQ_MODE_STANDARD;
929 pdata->sm = I2C_FREQ_MODE_FAST;
932 static atomic_t adapter_id = ATOMIC_INIT(0);
934 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
937 struct nmk_i2c_controller *pdata = adev->dev.platform_data;
938 struct device_node *np = adev->dev.of_node;
939 struct nmk_i2c_dev *dev;
940 struct i2c_adapter *adap;
944 pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL);
949 /* Provide the default configuration as a base. */
950 memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller));
951 nmk_i2c_of_probe(np, pdata);
953 /* No i2c configuration found, using the default. */
957 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
959 dev_err(&adev->dev, "cannot allocate memory\n");
965 amba_set_drvdata(adev, dev);
967 /* Select default pin state */
968 pinctrl_pm_select_default_state(&adev->dev);
969 /* If possible, let's go to idle until the first transfer */
970 pinctrl_pm_select_idle_state(&adev->dev);
972 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
973 if (!dev->virtbase) {
978 dev->irq = adev->irq[0];
979 ret = request_irq(dev->irq, i2c_irq_handler, 0,
982 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq);
986 pm_suspend_ignore_children(&adev->dev, true);
988 dev->clk = clk_get(&adev->dev, NULL);
989 if (IS_ERR(dev->clk)) {
990 dev_err(&adev->dev, "could not get i2c clock\n");
991 ret = PTR_ERR(dev->clk);
996 adap->dev.of_node = np;
997 adap->dev.parent = &adev->dev;
998 adap->owner = THIS_MODULE;
999 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1000 adap->algo = &nmk_i2c_algo;
1001 adap->timeout = msecs_to_jiffies(pdata->timeout);
1002 adap->nr = atomic_read(&adapter_id);
1003 snprintf(adap->name, sizeof(adap->name),
1004 "Nomadik I2C%d at %pR", adap->nr, &adev->res);
1005 atomic_inc(&adapter_id);
1007 /* fetch the controller configuration from machine */
1008 dev->cfg.clk_freq = pdata->clk_freq;
1009 dev->cfg.slsu = pdata->slsu;
1010 dev->cfg.tft = pdata->tft;
1011 dev->cfg.rft = pdata->rft;
1012 dev->cfg.sm = pdata->sm;
1014 i2c_set_adapdata(adap, dev);
1016 dev_info(&adev->dev,
1017 "initialize %s on virtual base %p\n",
1018 adap->name, dev->virtbase);
1020 ret = i2c_add_numbered_adapter(adap);
1022 dev_err(&adev->dev, "failed to add adapter\n");
1026 of_i2c_register_devices(adap);
1028 pm_runtime_put(&adev->dev);
1035 free_irq(dev->irq, dev);
1037 iounmap(dev->virtbase);
1045 static int nmk_i2c_remove(struct amba_device *adev)
1047 struct resource *res = &adev->res;
1048 struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
1050 i2c_del_adapter(&dev->adap);
1051 flush_i2c_fifo(dev);
1052 disable_all_interrupts(dev);
1053 clear_all_interrupts(dev);
1054 /* disable the controller */
1055 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
1056 free_irq(dev->irq, dev);
1057 iounmap(dev->virtbase);
1059 release_mem_region(res->start, resource_size(res));
1061 pm_runtime_disable(&adev->dev);
1067 static struct amba_id nmk_i2c_ids[] = {
1079 MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
1081 static struct amba_driver nmk_i2c_driver = {
1083 .owner = THIS_MODULE,
1084 .name = DRIVER_NAME,
1087 .id_table = nmk_i2c_ids,
1088 .probe = nmk_i2c_probe,
1089 .remove = nmk_i2c_remove,
1092 static int __init nmk_i2c_init(void)
1094 return amba_driver_register(&nmk_i2c_driver);
1097 static void __exit nmk_i2c_exit(void)
1099 amba_driver_unregister(&nmk_i2c_driver);
1102 subsys_initcall(nmk_i2c_init);
1103 module_exit(nmk_i2c_exit);
1105 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1106 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1107 MODULE_LICENSE("GPL");