2 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
3 * (http://www.opencores.org/projects.cgi/web/i2c/overview).
5 * Peter Korsgaard <jacmet@sunsite.dk>
7 * Support for the GRLIB port of the controller by
8 * Andreas Larsson <andreas@gaisler.com>
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/platform_device.h>
20 #include <linux/i2c.h>
21 #include <linux/interrupt.h>
22 #include <linux/wait.h>
23 #include <linux/i2c-ocores.h>
24 #include <linux/slab.h>
26 #include <linux/of_i2c.h>
27 #include <linux/log2.h>
33 wait_queue_head_t wait;
34 struct i2c_adapter adap;
38 int state; /* see STATE_ */
40 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
41 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
45 #define OCI2C_PRELOW 0
46 #define OCI2C_PREHIGH 1
47 #define OCI2C_CONTROL 2
49 #define OCI2C_CMD 4 /* write only */
50 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
52 #define OCI2C_CTRL_IEN 0x40
53 #define OCI2C_CTRL_EN 0x80
55 #define OCI2C_CMD_START 0x91
56 #define OCI2C_CMD_STOP 0x41
57 #define OCI2C_CMD_READ 0x21
58 #define OCI2C_CMD_WRITE 0x11
59 #define OCI2C_CMD_READ_ACK 0x21
60 #define OCI2C_CMD_READ_NACK 0x29
61 #define OCI2C_CMD_IACK 0x01
63 #define OCI2C_STAT_IF 0x01
64 #define OCI2C_STAT_TIP 0x02
65 #define OCI2C_STAT_ARBLOST 0x20
66 #define OCI2C_STAT_BUSY 0x40
67 #define OCI2C_STAT_NACK 0x80
78 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
80 iowrite8(value, i2c->base + (reg << i2c->reg_shift));
83 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
85 iowrite16(value, i2c->base + (reg << i2c->reg_shift));
88 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
90 iowrite32(value, i2c->base + (reg << i2c->reg_shift));
93 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
95 return ioread8(i2c->base + (reg << i2c->reg_shift));
98 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
100 return ioread16(i2c->base + (reg << i2c->reg_shift));
103 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
105 return ioread32(i2c->base + (reg << i2c->reg_shift));
108 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
110 i2c->setreg(i2c, reg, value);
113 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
115 return i2c->getreg(i2c, reg);
118 static void ocores_process(struct ocores_i2c *i2c)
120 struct i2c_msg *msg = i2c->msg;
121 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
123 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
124 /* stop has been sent */
125 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
131 if (stat & OCI2C_STAT_ARBLOST) {
132 i2c->state = STATE_ERROR;
133 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
137 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
139 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
141 if (stat & OCI2C_STAT_NACK) {
142 i2c->state = STATE_ERROR;
143 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
147 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
150 if (i2c->pos == msg->len) {
156 if (i2c->nmsgs) { /* end? */
158 if (!(msg->flags & I2C_M_NOSTART)) {
159 u8 addr = (msg->addr << 1);
161 if (msg->flags & I2C_M_RD)
164 i2c->state = STATE_START;
166 oc_setreg(i2c, OCI2C_DATA, addr);
167 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
170 i2c->state = (msg->flags & I2C_M_RD)
171 ? STATE_READ : STATE_WRITE;
173 i2c->state = STATE_DONE;
174 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
179 if (i2c->state == STATE_READ) {
180 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
181 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
183 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
184 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
188 static irqreturn_t ocores_isr(int irq, void *dev_id)
190 struct ocores_i2c *i2c = dev_id;
197 static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
199 struct ocores_i2c *i2c = i2c_get_adapdata(adap);
204 i2c->state = STATE_START;
206 oc_setreg(i2c, OCI2C_DATA,
207 (i2c->msg->addr << 1) |
208 ((i2c->msg->flags & I2C_M_RD) ? 1:0));
210 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
212 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
213 (i2c->state == STATE_DONE), HZ))
214 return (i2c->state == STATE_DONE) ? num : -EIO;
219 static void ocores_init(struct ocores_i2c *i2c)
222 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
224 /* make sure the device is disabled */
225 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
227 prescale = (i2c->clock_khz / (5*100)) - 1;
228 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
229 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
231 /* Init the device */
232 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
233 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
237 static u32 ocores_func(struct i2c_adapter *adap)
239 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
242 static const struct i2c_algorithm ocores_algorithm = {
243 .master_xfer = ocores_xfer,
244 .functionality = ocores_func,
247 static struct i2c_adapter ocores_adapter = {
248 .owner = THIS_MODULE,
249 .name = "i2c-ocores",
250 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
251 .algo = &ocores_algorithm,
254 static struct of_device_id ocores_i2c_match[] = {
256 .compatible = "opencores,i2c-ocores",
257 .data = (void *)TYPE_OCORES,
260 .compatible = "aeroflexgaisler,i2cmst",
261 .data = (void *)TYPE_GRLIB,
265 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
268 /* Read and write functions for the GRLIB port of the controller. Registers are
269 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
270 * register. The subsequent registers has their offset decreased accordingly. */
271 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
275 if (reg != OCI2C_PRELOW)
277 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
278 if (reg == OCI2C_PREHIGH)
279 return (u8)(rd >> 8);
284 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
288 if (reg != OCI2C_PRELOW)
290 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
291 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
292 if (reg == OCI2C_PRELOW)
293 wr = (curr & 0xff00) | value;
295 wr = (((u32)value) << 8) | (curr & 0xff);
299 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
302 static int ocores_i2c_of_probe(struct platform_device *pdev,
303 struct ocores_i2c *i2c)
305 struct device_node *np = pdev->dev.of_node;
306 const struct of_device_id *match;
309 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
310 /* no 'reg-shift', check for deprecated 'regstep' */
311 if (!of_property_read_u32(np, "regstep", &val)) {
312 if (!is_power_of_2(val)) {
313 dev_err(&pdev->dev, "invalid regstep %d\n",
317 i2c->reg_shift = ilog2(val);
319 "regstep property deprecated, use reg-shift\n");
323 if (of_property_read_u32(np, "clock-frequency", &val)) {
325 "Missing required parameter 'clock-frequency'\n");
328 i2c->clock_khz = val / 1000;
330 of_property_read_u32(pdev->dev.of_node, "reg-io-width",
333 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
334 if (match && (int)match->data == TYPE_GRLIB) {
335 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
336 i2c->setreg = oc_setreg_grlib;
337 i2c->getreg = oc_getreg_grlib;
343 #define ocores_i2c_of_probe(pdev,i2c) -ENODEV
346 static int __devinit ocores_i2c_probe(struct platform_device *pdev)
348 struct ocores_i2c *i2c;
349 struct ocores_i2c_platform_data *pdata;
350 struct resource *res;
355 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
359 irq = platform_get_irq(pdev, 0);
363 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
367 i2c->base = devm_request_and_ioremap(&pdev->dev, res);
369 return -EADDRNOTAVAIL;
371 pdata = pdev->dev.platform_data;
373 i2c->reg_shift = pdata->reg_shift;
374 i2c->reg_io_width = pdata->reg_io_width;
375 i2c->clock_khz = pdata->clock_khz;
377 ret = ocores_i2c_of_probe(pdev, i2c);
382 if (i2c->reg_io_width == 0)
383 i2c->reg_io_width = 1; /* Set to default value */
385 if (!i2c->setreg || !i2c->getreg) {
386 switch (i2c->reg_io_width) {
388 i2c->setreg = oc_setreg_8;
389 i2c->getreg = oc_getreg_8;
393 i2c->setreg = oc_setreg_16;
394 i2c->getreg = oc_getreg_16;
398 i2c->setreg = oc_setreg_32;
399 i2c->getreg = oc_getreg_32;
403 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
411 init_waitqueue_head(&i2c->wait);
412 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
415 dev_err(&pdev->dev, "Cannot claim IRQ\n");
419 /* hook up driver to tree */
420 platform_set_drvdata(pdev, i2c);
421 i2c->adap = ocores_adapter;
422 i2c_set_adapdata(&i2c->adap, i2c);
423 i2c->adap.dev.parent = &pdev->dev;
424 i2c->adap.dev.of_node = pdev->dev.of_node;
426 /* add i2c adapter to i2c tree */
427 ret = i2c_add_adapter(&i2c->adap);
429 dev_err(&pdev->dev, "Failed to add adapter\n");
433 /* add in known devices to the bus */
435 for (i = 0; i < pdata->num_devices; i++)
436 i2c_new_device(&i2c->adap, pdata->devices + i);
438 of_i2c_register_devices(&i2c->adap);
444 static int __devexit ocores_i2c_remove(struct platform_device *pdev)
446 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
448 /* disable i2c logic */
449 oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
450 & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
452 /* remove adapter & data */
453 i2c_del_adapter(&i2c->adap);
454 platform_set_drvdata(pdev, NULL);
460 static int ocores_i2c_suspend(struct device *dev)
462 struct ocores_i2c *i2c = dev_get_drvdata(dev);
463 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
465 /* make sure the device is disabled */
466 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
471 static int ocores_i2c_resume(struct device *dev)
473 struct ocores_i2c *i2c = dev_get_drvdata(dev);
480 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
481 #define OCORES_I2C_PM (&ocores_i2c_pm)
483 #define OCORES_I2C_PM NULL
486 static struct platform_driver ocores_i2c_driver = {
487 .probe = ocores_i2c_probe,
488 .remove = __devexit_p(ocores_i2c_remove),
490 .owner = THIS_MODULE,
491 .name = "ocores-i2c",
492 .of_match_table = ocores_i2c_match,
497 module_platform_driver(ocores_i2c_driver);
499 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
500 MODULE_DESCRIPTION("OpenCores I2C bus driver");
501 MODULE_LICENSE("GPL");
502 MODULE_ALIAS("platform:ocores-i2c");