drivers/i2c/busses/i2c-octeon.c

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
   4  *
   5  * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
   6  *
   7  * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/platform_device.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/delay.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/i2c.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24
  25 #include <asm/octeon/octeon.h>
  26
  27 #define DRV_NAME "i2c-octeon"
  28
  29 /* Register offsets */
  30 #define SW_TWSI                 0x00
  31 #define TWSI_INT                0x10
  32 #define SW_TWSI_EXT             0x18
  33
  34 /* Controller command patterns */
  35 #define SW_TWSI_V               BIT_ULL(63)     /* Valid bit */
  36 #define SW_TWSI_EIA             BIT_ULL(61)     /* Extended internal address */
  37 #define SW_TWSI_R               BIT_ULL(56)     /* Result or read bit */
  38 #define SW_TWSI_SOVR            BIT_ULL(55)     /* Size override */
  39 #define SW_TWSI_SIZE_SHIFT      52
  40 #define SW_TWSI_ADDR_SHIFT      40
  41 #define SW_TWSI_IA_SHIFT        32              /* Internal address */
  42
  43 /* Controller opcode word (bits 60:57) */
  44 #define SW_TWSI_OP_SHIFT        57
  45 #define SW_TWSI_OP_7            (0ULL << SW_TWSI_OP_SHIFT)
  46 #define SW_TWSI_OP_7_IA         (1ULL << SW_TWSI_OP_SHIFT)
  47 #define SW_TWSI_OP_10           (2ULL << SW_TWSI_OP_SHIFT)
  48 #define SW_TWSI_OP_10_IA        (3ULL << SW_TWSI_OP_SHIFT)
  49 #define SW_TWSI_OP_TWSI_CLK     (4ULL << SW_TWSI_OP_SHIFT)
  50 #define SW_TWSI_OP_EOP          (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
  51
  52 /* Controller extended opcode word (bits 34:32) */
  53 #define SW_TWSI_EOP_SHIFT       32
  54 #define SW_TWSI_EOP_TWSI_DATA   (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
  55 #define SW_TWSI_EOP_TWSI_CTL    (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
  56 #define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
  57 #define SW_TWSI_EOP_TWSI_STAT   (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
  58 #define SW_TWSI_EOP_TWSI_RST    (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
  59
  60 /* Controller command and status bits */
  61 #define TWSI_CTL_CE             0x80    /* High level controller enable */
  62 #define TWSI_CTL_ENAB           0x40    /* Bus enable */
  63 #define TWSI_CTL_STA            0x20    /* Master-mode start, HW clears when done */
  64 #define TWSI_CTL_STP            0x10    /* Master-mode stop, HW clears when done */
  65 #define TWSI_CTL_IFLG           0x08    /* HW event, SW writes 0 to ACK */
  66 #define TWSI_CTL_AAK            0x04    /* Assert ACK */
  67
  68 /* Status values */
  69 #define STAT_ERROR              0x00
  70 #define STAT_START              0x08
  71 #define STAT_REP_START          0x10
  72 #define STAT_TXADDR_ACK         0x18
  73 #define STAT_TXADDR_NAK         0x20
  74 #define STAT_TXDATA_ACK         0x28
  75 #define STAT_TXDATA_NAK         0x30
  76 #define STAT_LOST_ARB_38        0x38
  77 #define STAT_RXADDR_ACK         0x40
  78 #define STAT_RXADDR_NAK         0x48
  79 #define STAT_RXDATA_ACK         0x50
  80 #define STAT_RXDATA_NAK         0x58
  81 #define STAT_SLAVE_60           0x60
  82 #define STAT_LOST_ARB_68        0x68
  83 #define STAT_SLAVE_70           0x70
  84 #define STAT_LOST_ARB_78        0x78
  85 #define STAT_SLAVE_80           0x80
  86 #define STAT_SLAVE_88           0x88
  87 #define STAT_GENDATA_ACK        0x90
  88 #define STAT_GENDATA_NAK        0x98
  89 #define STAT_SLAVE_A0           0xA0
  90 #define STAT_SLAVE_A8           0xA8
  91 #define STAT_LOST_ARB_B0        0xB0
  92 #define STAT_SLAVE_LOST         0xB8
  93 #define STAT_SLAVE_NAK          0xC0
  94 #define STAT_SLAVE_ACK          0xC8
  95 #define STAT_AD2W_ACK           0xD0
  96 #define STAT_AD2W_NAK           0xD8
  97 #define STAT_IDLE               0xF8
  98
  99 /* TWSI_INT values */
 100 #define TWSI_INT_ST_INT         BIT_ULL(0)
 101 #define TWSI_INT_TS_INT         BIT_ULL(1)
 102 #define TWSI_INT_CORE_INT       BIT_ULL(2)
 103 #define TWSI_INT_ST_EN          BIT_ULL(4)
 104 #define TWSI_INT_TS_EN          BIT_ULL(5)
 105 #define TWSI_INT_CORE_EN        BIT_ULL(6)
 106 #define TWSI_INT_SDA_OVR        BIT_ULL(8)
 107 #define TWSI_INT_SCL_OVR        BIT_ULL(9)
 108 #define TWSI_INT_SDA            BIT_ULL(10)
 109 #define TWSI_INT_SCL            BIT_ULL(11)
 110
 111 struct octeon_i2c {
 112         wait_queue_head_t queue;
 113         struct i2c_adapter adap;
 114         int irq;
 115         u32 twsi_freq;
 116         int sys_freq;
 117         void __iomem *twsi_base;
 118         struct device *dev;
 119         bool hlc_enabled;
 120 };
 121
 122 static void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
 123 {
 124         __raw_writeq(val, addr);
 125         __raw_readq(addr);      /* wait for write to land */
 126 }
 127
 128 /**
 129  * octeon_i2c_reg_write - write an I2C core register
 130  * @i2c: The struct octeon_i2c
 131  * @eop_reg: Register selector
 132  * @data: Value to be written
 133  *
 134  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 135  */
 136 static void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
 137 {
 138         u64 tmp;
 139
 140         __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
 141         do {
 142                 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
 143         } while ((tmp & SW_TWSI_V) != 0);
 144 }
 145
 146 #define octeon_i2c_ctl_write(i2c, val)                                  \
 147         octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
 148 #define octeon_i2c_data_write(i2c, val)                                 \
 149         octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
 150
 151 /**
 152  * octeon_i2c_reg_read - read lower bits of an I2C core register
 153  * @i2c: The struct octeon_i2c
 154  * @eop_reg: Register selector
 155  *
 156  * Returns the data.
 157  *
 158  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 159  */
 160 static u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)
 161 {
 162         u64 tmp;
 163
 164         __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
 165         do {
 166                 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
 167         } while ((tmp & SW_TWSI_V) != 0);
 168
 169         return tmp & 0xFF;
 170 }
 171
 172 #define octeon_i2c_ctl_read(i2c)                                        \
 173         octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL)
 174 #define octeon_i2c_data_read(i2c)                                       \
 175         octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA)
 176 #define octeon_i2c_stat_read(i2c)                                       \
 177         octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT)
 178
 179 /**
 180  * octeon_i2c_read_int - read the TWSI_INT register
 181  * @i2c: The struct octeon_i2c
 182  *
 183  * Returns the value of the register.
 184  */
 185 static u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
 186 {
 187         return __raw_readq(i2c->twsi_base + TWSI_INT);
 188 }
 189
 190 /**
 191  * octeon_i2c_write_int - write the TWSI_INT register
 192  * @i2c: The struct octeon_i2c
 193  * @data: Value to be written
 194  */
 195 static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
 196 {
 197         octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT);
 198 }
 199
 200 /**
 201  * octeon_i2c_int_enable - enable the CORE interrupt
 202  * @i2c: The struct octeon_i2c
 203  *
 204  * The interrupt will be asserted when there is non-STAT_IDLE state in
 205  * the SW_TWSI_EOP_TWSI_STAT register.
 206  */
 207 static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
 208 {
 209         octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
 210 }
 211
 212 /* disable the CORE interrupt */
 213 static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
 214 {
 215         /* clear TS/ST/IFLG events */
 216         octeon_i2c_write_int(i2c, 0);
 217 }
 218
 219 /*
 220  * Cleanup low-level state & enable high-level controller.
 221  */
 222 static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)
 223 {
 224         int try = 0;
 225         u64 val;
 226
 227         if (i2c->hlc_enabled)
 228                 return;
 229         i2c->hlc_enabled = true;
 230
 231         while (1) {
 232                 val = octeon_i2c_ctl_read(i2c);
 233                 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP)))
 234                         break;
 235
 236                 /* clear IFLG event */
 237                 if (val & TWSI_CTL_IFLG)
 238                         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 239
 240                 if (try++ > 100) {
 241                         pr_err("%s: giving up\n", __func__);
 242                         break;
 243                 }
 244
 245                 /* spin until any start/stop has finished */
 246                 udelay(10);
 247         }
 248         octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
 249 }
 250
 251 static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
 252 {
 253         if (!i2c->hlc_enabled)
 254                 return;
 255
 256         i2c->hlc_enabled = false;
 257         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 258 }
 259
 260 /* interrupt service routine */
 261 static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
 262 {
 263         struct octeon_i2c *i2c = dev_id;
 264
 265         octeon_i2c_int_disable(i2c);
 266         wake_up(&i2c->queue);
 267
 268         return IRQ_HANDLED;
 269 }
 270
 271 static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
 272 {
 273         return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);
 274 }
 275
 276 /**
 277  * octeon_i2c_wait - wait for the IFLG to be set
 278  * @i2c: The struct octeon_i2c
 279  *
 280  * Returns 0 on success, otherwise a negative errno.
 281  */
 282 static int octeon_i2c_wait(struct octeon_i2c *i2c)
 283 {
 284         long time_left;
 285
 286         octeon_i2c_int_enable(i2c);
 287         time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
 288                                        i2c->adap.timeout);
 289         octeon_i2c_int_disable(i2c);
 290         if (!time_left) {
 291                 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
 292                 return -ETIMEDOUT;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
 299 {
 300         u8 stat = octeon_i2c_stat_read(i2c);
 301
 302         switch (stat) {
 303         /* Everything is fine */
 304         case STAT_IDLE:
 305         case STAT_AD2W_ACK:
 306         case STAT_RXADDR_ACK:
 307         case STAT_TXADDR_ACK:
 308         case STAT_TXDATA_ACK:
 309                 return 0;
 310
 311         /* ACK allowed on pre-terminal bytes only */
 312         case STAT_RXDATA_ACK:
 313                 if (!final_read)
 314                         return 0;
 315                 return -EIO;
 316
 317         /* NAK allowed on terminal byte only */
 318         case STAT_RXDATA_NAK:
 319                 if (final_read)
 320                         return 0;
 321                 return -EIO;
 322
 323         /* Arbitration lost */
 324         case STAT_LOST_ARB_38:
 325         case STAT_LOST_ARB_68:
 326         case STAT_LOST_ARB_78:
 327         case STAT_LOST_ARB_B0:
 328                 return -EAGAIN;
 329
 330         /* Being addressed as slave, should back off & listen */
 331         case STAT_SLAVE_60:
 332         case STAT_SLAVE_70:
 333         case STAT_GENDATA_ACK:
 334         case STAT_GENDATA_NAK:
 335                 return -EOPNOTSUPP;
 336
 337         /* Core busy as slave */
 338         case STAT_SLAVE_80:
 339         case STAT_SLAVE_88:
 340         case STAT_SLAVE_A0:
 341         case STAT_SLAVE_A8:
 342         case STAT_SLAVE_LOST:
 343         case STAT_SLAVE_NAK:
 344         case STAT_SLAVE_ACK:
 345                 return -EOPNOTSUPP;
 346
 347         case STAT_TXDATA_NAK:
 348                 return -EIO;
 349         case STAT_TXADDR_NAK:
 350         case STAT_RXADDR_NAK:
 351         case STAT_AD2W_NAK:
 352                 return -ENXIO;
 353         default:
 354                 dev_err(i2c->dev, "unhandled state: %d\n", stat);
 355                 return -EIO;
 356         }
 357 }
 358
 359 static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c)
 360 {
 361         u64 val = __raw_readq(i2c->twsi_base + SW_TWSI);
 362
 363         return (val & SW_TWSI_V) == 0;
 364 }
 365
 366 static void octeon_i2c_hlc_int_enable(struct octeon_i2c *i2c)
 367 {
 368         octeon_i2c_write_int(i2c, TWSI_INT_ST_EN);
 369 }
 370
 371 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
 372 {
 373         /* clear ST/TS events, listen for neither */
 374         octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
 375 }
 376
 377 /**
 378  * octeon_i2c_hlc_wait - wait for an HLC operation to complete
 379  * @i2c: The struct octeon_i2c
 380  *
 381  * Returns 0 on success, otherwise -ETIMEDOUT.
 382  */
 383 static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
 384 {
 385         int time_left;
 386
 387         octeon_i2c_hlc_int_enable(i2c);
 388         time_left = wait_event_timeout(i2c->queue,
 389                                        octeon_i2c_hlc_test_ready(i2c),
 390                                        i2c->adap.timeout);
 391         octeon_i2c_int_disable(i2c);
 392         if (!time_left) {
 393                 octeon_i2c_hlc_int_clear(i2c);
 394                 return -ETIMEDOUT;
 395         }
 396         return 0;
 397 }
 398
 399 /* high-level-controller pure read of up to 8 bytes */
 400 static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 401 {
 402         int i, j, ret = 0;
 403         u64 cmd;
 404
 405         octeon_i2c_hlc_enable(i2c);
 406         octeon_i2c_hlc_int_clear(i2c);
 407
 408         cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
 409         /* SIZE */
 410         cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
 411         /* A */
 412         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 413
 414         if (msgs[0].flags & I2C_M_TEN)
 415                 cmd |= SW_TWSI_OP_10;
 416         else
 417                 cmd |= SW_TWSI_OP_7;
 418
 419         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
 420         ret = octeon_i2c_hlc_wait(i2c);
 421         if (ret)
 422                 goto err;
 423
 424         cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
 425         if ((cmd & SW_TWSI_R) == 0)
 426                 return -EAGAIN;
 427
 428         for (i = 0, j = msgs[0].len - 1; i  < msgs[0].len && i < 4; i++, j--)
 429                 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
 430
 431         if (msgs[0].len > 4) {
 432                 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
 433                 for (i = 0; i  < msgs[0].len - 4 && i < 4; i++, j--)
 434                         msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
 435         }
 436
 437 err:
 438         return ret;
 439 }
 440
 441 /* high-level-controller pure write of up to 8 bytes */
 442 static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 443 {
 444         int i, j, ret = 0;
 445         u64 cmd;
 446
 447         octeon_i2c_hlc_enable(i2c);
 448         octeon_i2c_hlc_int_clear(i2c);
 449
 450         cmd = SW_TWSI_V | SW_TWSI_SOVR;
 451         /* SIZE */
 452         cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
 453         /* A */
 454         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 455
 456         if (msgs[0].flags & I2C_M_TEN)
 457                 cmd |= SW_TWSI_OP_10;
 458         else
 459                 cmd |= SW_TWSI_OP_7;
 460
 461         for (i = 0, j = msgs[0].len - 1; i  < msgs[0].len && i < 4; i++, j--)
 462                 cmd |= (u64)msgs[0].buf[j] << (8 * i);
 463
 464         if (msgs[0].len > 4) {
 465                 u64 ext = 0;
 466
 467                 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
 468                         ext |= (u64)msgs[0].buf[j] << (8 * i);
 469                 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT);
 470         }
 471
 472         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
 473         ret = octeon_i2c_hlc_wait(i2c);
 474         if (ret)
 475                 goto err;
 476
 477         cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
 478         if ((cmd & SW_TWSI_R) == 0)
 479                 return -EAGAIN;
 480
 481         ret = octeon_i2c_check_status(i2c, false);
 482
 483 err:
 484         return ret;
 485 }
 486
 487 /* high-level-controller composite write+read, msg0=addr, msg1=data */
 488 static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 489 {
 490         int i, j, ret = 0;
 491         u64 cmd;
 492
 493         octeon_i2c_hlc_enable(i2c);
 494
 495         cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
 496         /* SIZE */
 497         cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
 498         /* A */
 499         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 500
 501         if (msgs[0].flags & I2C_M_TEN)
 502                 cmd |= SW_TWSI_OP_10_IA;
 503         else
 504                 cmd |= SW_TWSI_OP_7_IA;
 505
 506         if (msgs[0].len == 2) {
 507                 u64 ext = 0;
 508
 509                 cmd |= SW_TWSI_EIA;
 510                 ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 511                 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
 512                 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT);
 513         } else {
 514                 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 515         }
 516
 517         octeon_i2c_hlc_int_clear(i2c);
 518         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
 519
 520         ret = octeon_i2c_hlc_wait(i2c);
 521         if (ret)
 522                 goto err;
 523
 524         cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
 525         if ((cmd & SW_TWSI_R) == 0)
 526                 return -EAGAIN;
 527
 528         for (i = 0, j = msgs[1].len - 1; i  < msgs[1].len && i < 4; i++, j--)
 529                 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
 530
 531         if (msgs[1].len > 4) {
 532                 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
 533                 for (i = 0; i  < msgs[1].len - 4 && i < 4; i++, j--)
 534                         msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
 535         }
 536
 537 err:
 538         return ret;
 539 }
 540
 541 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
 542 static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
 543 {
 544         bool set_ext = false;
 545         int i, j, ret = 0;
 546         u64 cmd, ext = 0;
 547
 548         octeon_i2c_hlc_enable(i2c);
 549
 550         cmd = SW_TWSI_V | SW_TWSI_SOVR;
 551         /* SIZE */
 552         cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
 553         /* A */
 554         cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
 555
 556         if (msgs[0].flags & I2C_M_TEN)
 557                 cmd |= SW_TWSI_OP_10_IA;
 558         else
 559                 cmd |= SW_TWSI_OP_7_IA;
 560
 561         if (msgs[0].len == 2) {
 562                 cmd |= SW_TWSI_EIA;
 563                 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 564                 set_ext = true;
 565                 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
 566         } else {
 567                 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
 568         }
 569
 570         for (i = 0, j = msgs[1].len - 1; i  < msgs[1].len && i < 4; i++, j--)
 571                 cmd |= (u64)msgs[1].buf[j] << (8 * i);
 572
 573         if (msgs[1].len > 4) {
 574                 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
 575                         ext |= (u64)msgs[1].buf[j] << (8 * i);
 576                 set_ext = true;
 577         }
 578         if (set_ext)
 579                 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT);
 580
 581         octeon_i2c_hlc_int_clear(i2c);
 582         octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI);
 583
 584         ret = octeon_i2c_hlc_wait(i2c);
 585         if (ret)
 586                 goto err;
 587
 588         cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
 589         if ((cmd & SW_TWSI_R) == 0)
 590                 return -EAGAIN;
 591
 592         ret = octeon_i2c_check_status(i2c, false);
 593
 594 err:
 595         return ret;
 596 }
 597
 598 /* calculate and set clock divisors */
 599 static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
 600 {
 601         int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
 602         int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
 603
 604         for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
 605                 /*
 606                  * An mdiv value of less than 2 seems to not work well
 607                  * with ds1337 RTCs, so we constrain it to larger values.
 608                  */
 609                 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
 610                         /*
 611                          * For given ndiv and mdiv values check the
 612                          * two closest thp values.
 613                          */
 614                         tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
 615                         tclk *= (1 << ndiv_idx);
 616                         thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
 617
 618                         for (inc = 0; inc <= 1; inc++) {
 619                                 thp_idx = thp_base + inc;
 620                                 if (thp_idx < 5 || thp_idx > 0xff)
 621                                         continue;
 622
 623                                 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
 624                                 foscl = foscl / (1 << ndiv_idx);
 625                                 foscl = foscl / (mdiv_idx + 1) / 10;
 626                                 diff = abs(foscl - i2c->twsi_freq);
 627                                 if (diff < delta_hz) {
 628                                         delta_hz = diff;
 629                                         thp = thp_idx;
 630                                         mdiv = mdiv_idx;
 631                                         ndiv = ndiv_idx;
 632                                 }
 633                         }
 634                 }
 635         }
 636         octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
 637         octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
 638 }
 639
 640 static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
 641 {
 642         u8 status = 0;
 643         int tries;
 644
 645         /* reset controller */
 646         octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
 647
 648         for (tries = 10; tries && status != STAT_IDLE; tries--) {
 649                 udelay(1);
 650                 status = octeon_i2c_stat_read(i2c);
 651                 if (status == STAT_IDLE)
 652                         break;
 653         }
 654
 655         if (status != STAT_IDLE) {
 656                 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
 657                         __func__, status);
 658                 return -EIO;
 659         }
 660
 661         /* toggle twice to force both teardowns */
 662         octeon_i2c_hlc_enable(i2c);
 663         octeon_i2c_hlc_disable(i2c);
 664         return 0;
 665 }
 666
 667 static int octeon_i2c_recovery(struct octeon_i2c *i2c)
 668 {
 669         int ret;
 670
 671         ret = i2c_recover_bus(&i2c->adap);
 672         if (ret)
 673                 /* recover failed, try hardware re-init */
 674                 ret = octeon_i2c_init_lowlevel(i2c);
 675         return ret;
 676 }
 677
 678 /**
 679  * octeon_i2c_start - send START to the bus
 680  * @i2c: The struct octeon_i2c
 681  *
 682  * Returns 0 on success, otherwise a negative errno.
 683  */
 684 static int octeon_i2c_start(struct octeon_i2c *i2c)
 685 {
 686         int ret;
 687         u8 stat;
 688
 689         octeon_i2c_hlc_disable(i2c);
 690
 691         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
 692         ret = octeon_i2c_wait(i2c);
 693         if (ret)
 694                 goto error;
 695
 696         stat = octeon_i2c_stat_read(i2c);
 697         if (stat == STAT_START || stat == STAT_REP_START)
 698                 /* START successful, bail out */
 699                 return 0;
 700
 701 error:
 702         /* START failed, try to recover */
 703         ret = octeon_i2c_recovery(i2c);
 704         return (ret) ? ret : -EAGAIN;
 705 }
 706
 707 /* send STOP to the bus */
 708 static void octeon_i2c_stop(struct octeon_i2c *i2c)
 709 {
 710         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);
 711 }
 712
 713 /**
 714  * octeon_i2c_write - send data to the bus via low-level controller
 715  * @i2c: The struct octeon_i2c
 716  * @target: Target address
 717  * @data: Pointer to the data to be sent
 718  * @length: Length of the data
 719  *
 720  * The address is sent over the bus, then the data.
 721  *
 722  * Returns 0 on success, otherwise a negative errno.
 723  */
 724 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
 725                             const u8 *data, int length)
 726 {
 727         int i, result;
 728
 729         octeon_i2c_data_write(i2c, target << 1);
 730         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 731
 732         result = octeon_i2c_wait(i2c);
 733         if (result)
 734                 return result;
 735
 736         for (i = 0; i < length; i++) {
 737                 result = octeon_i2c_check_status(i2c, false);
 738                 if (result)
 739                         return result;
 740
 741                 octeon_i2c_data_write(i2c, data[i]);
 742                 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 743
 744                 result = octeon_i2c_wait(i2c);
 745                 if (result)
 746                         return result;
 747         }
 748
 749         return 0;
 750 }
 751
 752 /**
 753  * octeon_i2c_read - receive data from the bus via low-level controller
 754  * @i2c: The struct octeon_i2c
 755  * @target: Target address
 756  * @data: Pointer to the location to store the data
 757  * @rlength: Length of the data
 758  * @recv_len: flag for length byte
 759  *
 760  * The address is sent over the bus, then the data is read.
 761  *
 762  * Returns 0 on success, otherwise a negative errno.
 763  */
 764 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
 765                            u8 *data, u16 *rlength, bool recv_len)
 766 {
 767         int i, result, length = *rlength;
 768         bool final_read = false;
 769
 770         if (length < 1)
 771                 return -EINVAL;
 772
 773         octeon_i2c_data_write(i2c, (target << 1) | 1);
 774         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 775
 776         result = octeon_i2c_wait(i2c);
 777         if (result)
 778                 return result;
 779
 780         /* address OK ? */
 781         result = octeon_i2c_check_status(i2c, false);
 782         if (result)
 783                 return result;
 784
 785         for (i = 0; i < length; i++) {
 786                 /* for the last byte TWSI_CTL_AAK must not be set */
 787                 if (i + 1 == length)
 788                         final_read = true;
 789
 790                 /* clear iflg to allow next event */
 791                 if (final_read)
 792                         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
 793                 else
 794                         octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);
 795
 796                 result = octeon_i2c_wait(i2c);
 797                 if (result)
 798                         return result;
 799
 800                 data[i] = octeon_i2c_data_read(i2c);
 801                 if (recv_len && i == 0) {
 802                         if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {
 803                                 dev_err(i2c->dev,
 804                                         "%s: read len > I2C_SMBUS_BLOCK_MAX %d\n",
 805                                         __func__, data[i]);
 806                                 return -EPROTO;
 807                         }
 808                         length += data[i];
 809                 }
 810
 811                 result = octeon_i2c_check_status(i2c, final_read);
 812                 if (result)
 813                         return result;
 814         }
 815         *rlength = length;
 816         return 0;
 817 }
 818
 819 /**
 820  * octeon_i2c_xfer - The driver's master_xfer function
 821  * @adap: Pointer to the i2c_adapter structure
 822  * @msgs: Pointer to the messages to be processed
 823  * @num: Length of the MSGS array
 824  *
 825  * Returns the number of messages processed, or a negative errno on failure.
 826  */
 827 static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 828                            int num)
 829 {
 830         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 831         int i, ret = 0;
 832
 833         if (num == 1) {
 834                 if (msgs[0].len > 0 && msgs[0].len <= 8) {
 835                         if (msgs[0].flags & I2C_M_RD)
 836                                 ret = octeon_i2c_hlc_read(i2c, msgs);
 837                         else
 838                                 ret = octeon_i2c_hlc_write(i2c, msgs);
 839                         goto out;
 840                 }
 841         } else if (num == 2) {
 842                 if ((msgs[0].flags & I2C_M_RD) == 0 &&
 843                     (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
 844                     msgs[0].len > 0 && msgs[0].len <= 2 &&
 845                     msgs[1].len > 0 && msgs[1].len <= 8 &&
 846                     msgs[0].addr == msgs[1].addr) {
 847                         if (msgs[1].flags & I2C_M_RD)
 848                                 ret = octeon_i2c_hlc_comp_read(i2c, msgs);
 849                         else
 850                                 ret = octeon_i2c_hlc_comp_write(i2c, msgs);
 851                         goto out;
 852                 }
 853         }
 854
 855         for (i = 0; ret == 0 && i < num; i++) {
 856                 struct i2c_msg *pmsg = &msgs[i];
 857
 858                 ret = octeon_i2c_start(i2c);
 859                 if (ret)
 860                         return ret;
 861
 862                 if (pmsg->flags & I2C_M_RD)
 863                         ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
 864                                               &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
 865                 else
 866                         ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
 867                                                pmsg->len);
 868         }
 869         octeon_i2c_stop(i2c);
 870 out:
 871         return (ret != 0) ? ret : num;
 872 }
 873
 874 static int octeon_i2c_get_scl(struct i2c_adapter *adap)
 875 {
 876         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 877         u64 state;
 878
 879         state = octeon_i2c_read_int(i2c);
 880         return state & TWSI_INT_SCL;
 881 }
 882
 883 static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)
 884 {
 885         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 886
 887         octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
 888 }
 889
 890 static int octeon_i2c_get_sda(struct i2c_adapter *adap)
 891 {
 892         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 893         u64 state;
 894
 895         state = octeon_i2c_read_int(i2c);
 896         return state & TWSI_INT_SDA;
 897 }
 898
 899 static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
 900 {
 901         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 902
 903         /*
 904          * The stop resets the state machine, does not _transmit_ STOP unless
 905          * engine was active.
 906          */
 907         octeon_i2c_stop(i2c);
 908
 909         octeon_i2c_hlc_disable(i2c);
 910         octeon_i2c_write_int(i2c, 0);
 911 }
 912
 913 static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap)
 914 {
 915         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 916
 917         octeon_i2c_write_int(i2c, 0);
 918 }
 919
 920 static struct i2c_bus_recovery_info octeon_i2c_recovery_info = {
 921         .recover_bus = i2c_generic_scl_recovery,
 922         .get_scl = octeon_i2c_get_scl,
 923         .set_scl = octeon_i2c_set_scl,
 924         .get_sda = octeon_i2c_get_sda,
 925         .prepare_recovery = octeon_i2c_prepare_recovery,
 926         .unprepare_recovery = octeon_i2c_unprepare_recovery,
 927 };
 928
 929 static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
 930 {
 931         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 932                I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
 933 }
 934
 935 static const struct i2c_algorithm octeon_i2c_algo = {
 936         .master_xfer = octeon_i2c_xfer,
 937         .functionality = octeon_i2c_functionality,
 938 };
 939
 940 static struct i2c_adapter octeon_i2c_ops = {
 941         .owner = THIS_MODULE,
 942         .name = "OCTEON adapter",
 943         .algo = &octeon_i2c_algo,
 944 };
 945
 946 static int octeon_i2c_probe(struct platform_device *pdev)
 947 {
 948         struct device_node *node = pdev->dev.of_node;
 949         struct resource *res_mem;
 950         struct octeon_i2c *i2c;
 951         int irq, result = 0;
 952
 953         /* All adaptors have an irq.  */
 954         irq = platform_get_irq(pdev, 0);
 955         if (irq < 0)
 956                 return irq;
 957
 958         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 959         if (!i2c) {
 960                 result = -ENOMEM;
 961                 goto out;
 962         }
 963         i2c->dev = &pdev->dev;
 964
 965         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 966         i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem);
 967         if (IS_ERR(i2c->twsi_base)) {
 968                 result = PTR_ERR(i2c->twsi_base);
 969                 goto out;
 970         }
 971
 972         /*
 973          * "clock-rate" is a legacy binding, the official binding is
 974          * "clock-frequency".  Try the official one first and then
 975          * fall back if it doesn't exist.
 976          */
 977         if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
 978             of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
 979                 dev_err(i2c->dev,
 980                         "no I2C 'clock-rate' or 'clock-frequency' property\n");
 981                 result = -ENXIO;
 982                 goto out;
 983         }
 984
 985         i2c->sys_freq = octeon_get_io_clock_rate();
 986
 987         init_waitqueue_head(&i2c->queue);
 988
 989         i2c->irq = irq;
 990
 991         result = devm_request_irq(&pdev->dev, i2c->irq,
 992                                   octeon_i2c_isr, 0, DRV_NAME, i2c);
 993         if (result < 0) {
 994                 dev_err(i2c->dev, "failed to attach interrupt\n");
 995                 goto out;
 996         }
 997
 998         result = octeon_i2c_init_lowlevel(i2c);
 999         if (result) {
1000                 dev_err(i2c->dev, "init low level failed\n");
1001                 goto  out;
1002         }
1003
1004         octeon_i2c_set_clock(i2c);
1005
1006         i2c->adap = octeon_i2c_ops;
1007         i2c->adap.timeout = msecs_to_jiffies(2);
1008         i2c->adap.retries = 5;
1009         i2c->adap.bus_recovery_info = &octeon_i2c_recovery_info;
1010         i2c->adap.dev.parent = &pdev->dev;
1011         i2c->adap.dev.of_node = node;
1012         i2c_set_adapdata(&i2c->adap, i2c);
1013         platform_set_drvdata(pdev, i2c);
1014
1015         result = i2c_add_adapter(&i2c->adap);
1016         if (result < 0) {
1017                 dev_err(i2c->dev, "failed to add adapter\n");
1018                 goto out;
1019         }
1020         dev_info(i2c->dev, "probed\n");
1021         return 0;
1022
1023 out:
1024         return result;
1025 };
1026
1027 static int octeon_i2c_remove(struct platform_device *pdev)
1028 {
1029         struct octeon_i2c *i2c = platform_get_drvdata(pdev);
1030
1031         i2c_del_adapter(&i2c->adap);
1032         return 0;
1033 };
1034
1035 static const struct of_device_id octeon_i2c_match[] = {
1036         { .compatible = "cavium,octeon-3860-twsi", },
1037         {},
1038 };
1039 MODULE_DEVICE_TABLE(of, octeon_i2c_match);
1040
1041 static struct platform_driver octeon_i2c_driver = {
1042         .probe          = octeon_i2c_probe,
1043         .remove         = octeon_i2c_remove,
1044         .driver         = {
1045                 .name   = DRV_NAME,
1046                 .of_match_table = octeon_i2c_match,
1047         },
1048 };
1049
1050 module_platform_driver(octeon_i2c_driver);
1051
1052 MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
1053 MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
1054 MODULE_LICENSE("GPL");