2 * Provides I2C support for Philips PNX010x/PNX4008 boards.
4 * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
5 * Vitaly Wool <vwool@ru.mvista.com>
7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/timer.h>
19 #include <linux/completion.h>
20 #include <linux/platform_device.h>
21 #include <linux/i2c-pnx.h>
23 #include <linux/err.h>
24 #include <linux/clk.h>
25 #include <linux/slab.h>
27 #include <mach/hardware.h>
30 #define I2C_PNX_TIMEOUT 10 /* msec */
31 #define I2C_PNX_SPEED_KHZ 100
32 #define I2C_PNX_REGION_SIZE 0x100
34 static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data)
37 (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
41 return (timeout <= 0);
44 static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data)
47 (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
51 return (timeout <= 0);
54 static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
56 struct timer_list *timer = &alg_data->mif.timer;
57 unsigned long expires = msecs_to_jiffies(I2C_PNX_TIMEOUT);
62 del_timer_sync(timer);
64 dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n",
67 timer->expires = jiffies + expires;
68 timer->data = (unsigned long)&alg_data;
74 * i2c_pnx_start - start a device
75 * @slave_addr: slave address
76 * @adap: pointer to adapter structure
78 * Generate a START signal in the desired mode.
80 static int i2c_pnx_start(unsigned char slave_addr,
81 struct i2c_pnx_algo_data *alg_data)
83 dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
84 slave_addr, alg_data->mif.mode);
86 /* Check for 7 bit slave addresses only */
87 if (slave_addr & ~0x7f) {
88 dev_err(&alg_data->adapter.dev,
89 "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
90 alg_data->adapter.name, slave_addr);
94 /* First, make sure bus is idle */
95 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) {
96 /* Somebody else is monopolizing the bus */
97 dev_err(&alg_data->adapter.dev,
98 "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
99 alg_data->adapter.name, slave_addr,
100 ioread32(I2C_REG_CTL(alg_data)),
101 ioread32(I2C_REG_STS(alg_data)));
103 } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
104 /* Sorry, we lost the bus */
105 dev_err(&alg_data->adapter.dev,
106 "%s: Arbitration failure. Slave addr = %02x\n",
107 alg_data->adapter.name, slave_addr);
112 * OK, I2C is enabled and we have the bus.
113 * Clear the current TDI and AFI status flags.
115 iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
116 I2C_REG_STS(alg_data));
118 dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
119 (slave_addr << 1) | start_bit | alg_data->mif.mode);
121 /* Write the slave address, START bit and R/W bit */
122 iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
123 I2C_REG_TX(alg_data));
125 dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
131 * i2c_pnx_stop - stop a device
132 * @adap: pointer to I2C adapter structure
134 * Generate a STOP signal to terminate the master transaction.
136 static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
138 /* Only 1 msec max timeout due to interrupt context */
141 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
142 __func__, ioread32(I2C_REG_STS(alg_data)));
144 /* Write a STOP bit to TX FIFO */
145 iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
147 /* Wait until the STOP is seen. */
148 while (timeout > 0 &&
149 (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
150 /* may be called from interrupt context */
155 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
156 __func__, ioread32(I2C_REG_STS(alg_data)));
160 * i2c_pnx_master_xmit - transmit data to slave
161 * @adap: pointer to I2C adapter structure
163 * Sends one byte of data to the slave
165 static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
169 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
170 __func__, ioread32(I2C_REG_STS(alg_data)));
172 if (alg_data->mif.len > 0) {
173 /* We still have something to talk about... */
174 val = *alg_data->mif.buf++;
177 iowrite32(val, I2C_REG_TX(alg_data));
179 dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
180 __func__, val, alg_data->mif.len + 1);
182 if (alg_data->mif.len == 0) {
183 if (alg_data->last) {
184 /* Wait until the STOP is seen. */
185 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
186 dev_err(&alg_data->adapter.dev,
187 "The bus is still active after timeout\n");
189 /* Disable master interrupts */
190 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
191 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
192 I2C_REG_CTL(alg_data));
194 del_timer_sync(&alg_data->mif.timer);
196 dev_dbg(&alg_data->adapter.dev,
197 "%s(): Waking up xfer routine.\n",
200 complete(&alg_data->mif.complete);
202 } else if (alg_data->mif.len == 0) {
203 /* zero-sized transfer */
204 i2c_pnx_stop(alg_data);
206 /* Disable master interrupts. */
207 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
208 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
209 I2C_REG_CTL(alg_data));
212 del_timer_sync(&alg_data->mif.timer);
213 dev_dbg(&alg_data->adapter.dev,
214 "%s(): Waking up xfer routine after zero-xfer.\n",
217 complete(&alg_data->mif.complete);
220 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
221 __func__, ioread32(I2C_REG_STS(alg_data)));
227 * i2c_pnx_master_rcv - receive data from slave
228 * @adap: pointer to I2C adapter structure
230 * Reads one byte data from the slave
232 static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
234 unsigned int val = 0;
237 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
238 __func__, ioread32(I2C_REG_STS(alg_data)));
240 /* Check, whether there is already data,
241 * or we didn't 'ask' for it yet.
243 if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
244 dev_dbg(&alg_data->adapter.dev,
245 "%s(): Write dummy data to fill Rx-fifo...\n",
248 if (alg_data->mif.len == 1) {
250 * Enable interrupt RFDAIE (data in Rx fifo),
251 * and disable DRMIE (need data for Tx)
253 ctl = ioread32(I2C_REG_CTL(alg_data));
254 ctl |= mcntrl_rffie | mcntrl_daie;
255 ctl &= ~mcntrl_drmie;
256 iowrite32(ctl, I2C_REG_CTL(alg_data));
260 * Now we'll 'ask' for data:
261 * For each byte we want to receive, we must
262 * write a (dummy) byte to the Tx-FIFO.
264 iowrite32(val, I2C_REG_TX(alg_data));
270 if (alg_data->mif.len > 0) {
271 val = ioread32(I2C_REG_RX(alg_data));
272 *alg_data->mif.buf++ = (u8) (val & 0xff);
273 dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
274 __func__, val, alg_data->mif.len);
277 if (alg_data->mif.len == 0) {
279 /* Wait until the STOP is seen. */
280 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
281 dev_err(&alg_data->adapter.dev,
282 "The bus is still active after timeout\n");
284 /* Disable master interrupts */
285 ctl = ioread32(I2C_REG_CTL(alg_data));
286 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
287 mcntrl_drmie | mcntrl_daie);
288 iowrite32(ctl, I2C_REG_CTL(alg_data));
291 del_timer_sync(&alg_data->mif.timer);
292 complete(&alg_data->mif.complete);
296 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
297 __func__, ioread32(I2C_REG_STS(alg_data)));
302 static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
304 struct i2c_pnx_algo_data *alg_data = dev_id;
307 dev_dbg(&alg_data->adapter.dev,
308 "%s(): mstat = %x mctrl = %x, mode = %d\n",
310 ioread32(I2C_REG_STS(alg_data)),
311 ioread32(I2C_REG_CTL(alg_data)),
313 stat = ioread32(I2C_REG_STS(alg_data));
315 /* let's see what kind of event this is */
316 if (stat & mstatus_afi) {
317 /* We lost arbitration in the midst of a transfer */
318 alg_data->mif.ret = -EIO;
320 /* Disable master interrupts. */
321 ctl = ioread32(I2C_REG_CTL(alg_data));
322 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
324 iowrite32(ctl, I2C_REG_CTL(alg_data));
326 /* Stop timer, to prevent timeout. */
327 del_timer_sync(&alg_data->mif.timer);
328 complete(&alg_data->mif.complete);
329 } else if (stat & mstatus_nai) {
330 /* Slave did not acknowledge, generate a STOP */
331 dev_dbg(&alg_data->adapter.dev,
332 "%s(): Slave did not acknowledge, generating a STOP.\n",
334 i2c_pnx_stop(alg_data);
336 /* Disable master interrupts. */
337 ctl = ioread32(I2C_REG_CTL(alg_data));
338 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
340 iowrite32(ctl, I2C_REG_CTL(alg_data));
342 /* Our return value. */
343 alg_data->mif.ret = -EIO;
345 /* Stop timer, to prevent timeout. */
346 del_timer_sync(&alg_data->mif.timer);
347 complete(&alg_data->mif.complete);
351 * - Master Tx needs data.
352 * - There is data in the Rx-fifo
353 * The latter is only the case if we have requested for data,
354 * via a dummy write. (See 'i2c_pnx_master_rcv'.)
355 * We therefore check, as a sanity check, whether that interrupt
358 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
359 if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
360 i2c_pnx_master_xmit(alg_data);
361 } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
362 i2c_pnx_master_rcv(alg_data);
367 /* Clear TDI and AFI bits */
368 stat = ioread32(I2C_REG_STS(alg_data));
369 iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
371 dev_dbg(&alg_data->adapter.dev,
372 "%s(): exiting, stat = %x ctrl = %x.\n",
373 __func__, ioread32(I2C_REG_STS(alg_data)),
374 ioread32(I2C_REG_CTL(alg_data)));
379 static void i2c_pnx_timeout(unsigned long data)
381 struct i2c_pnx_algo_data *alg_data = (struct i2c_pnx_algo_data *)data;
384 dev_err(&alg_data->adapter.dev,
385 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
386 ioread32(I2C_REG_STS(alg_data)),
387 ioread32(I2C_REG_CTL(alg_data)));
389 /* Reset master and disable interrupts */
390 ctl = ioread32(I2C_REG_CTL(alg_data));
391 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
392 iowrite32(ctl, I2C_REG_CTL(alg_data));
395 iowrite32(ctl, I2C_REG_CTL(alg_data));
396 wait_reset(I2C_PNX_TIMEOUT, alg_data);
397 alg_data->mif.ret = -EIO;
398 complete(&alg_data->mif.complete);
401 static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
405 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
406 dev_err(&alg_data->adapter.dev,
407 "%s: Bus is still active after xfer. Reset it...\n",
408 alg_data->adapter.name);
409 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
410 I2C_REG_CTL(alg_data));
411 wait_reset(I2C_PNX_TIMEOUT, alg_data);
412 } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
413 /* If there is data in the fifo's after transfer,
414 * flush fifo's by reset.
416 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
417 I2C_REG_CTL(alg_data));
418 wait_reset(I2C_PNX_TIMEOUT, alg_data);
419 } else if (stat & mstatus_nai) {
420 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
421 I2C_REG_CTL(alg_data));
422 wait_reset(I2C_PNX_TIMEOUT, alg_data);
427 * i2c_pnx_xfer - generic transfer entry point
428 * @adap: pointer to I2C adapter structure
429 * @msgs: array of messages
430 * @num: number of messages
432 * Initiates the transfer
435 i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
437 struct i2c_msg *pmsg;
438 int rc = 0, completed = 0, i;
439 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
440 u32 stat = ioread32(I2C_REG_STS(alg_data));
442 dev_dbg(&alg_data->adapter.dev,
443 "%s(): entering: %d messages, stat = %04x.\n",
444 __func__, num, ioread32(I2C_REG_STS(alg_data)));
446 bus_reset_if_active(alg_data);
448 /* Process transactions in a loop. */
449 for (i = 0; rc >= 0 && i < num; i++) {
455 if (pmsg->flags & I2C_M_TEN) {
456 dev_err(&alg_data->adapter.dev,
457 "%s: 10 bits addr not supported!\n",
458 alg_data->adapter.name);
463 alg_data->mif.buf = pmsg->buf;
464 alg_data->mif.len = pmsg->len;
465 alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
466 I2C_SMBUS_READ : I2C_SMBUS_WRITE;
467 alg_data->mif.ret = 0;
468 alg_data->last = (i == num - 1);
470 dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
471 __func__, alg_data->mif.mode, alg_data->mif.len);
473 i2c_pnx_arm_timer(alg_data);
475 /* initialize the completion var */
476 init_completion(&alg_data->mif.complete);
478 /* Enable master interrupt */
479 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
480 mcntrl_naie | mcntrl_drmie,
481 I2C_REG_CTL(alg_data));
483 /* Put start-code and slave-address on the bus. */
484 rc = i2c_pnx_start(addr, alg_data);
488 /* Wait for completion */
489 wait_for_completion(&alg_data->mif.complete);
491 if (!(rc = alg_data->mif.ret))
493 dev_dbg(&alg_data->adapter.dev,
494 "%s(): Complete, return code = %d.\n",
497 /* Clear TDI and AFI bits in case they are set. */
498 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
499 dev_dbg(&alg_data->adapter.dev,
500 "%s: TDI still set... clearing now.\n",
501 alg_data->adapter.name);
502 iowrite32(stat, I2C_REG_STS(alg_data));
504 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
505 dev_dbg(&alg_data->adapter.dev,
506 "%s: AFI still set... clearing now.\n",
507 alg_data->adapter.name);
508 iowrite32(stat, I2C_REG_STS(alg_data));
512 bus_reset_if_active(alg_data);
514 /* Cleanup to be sure... */
515 alg_data->mif.buf = NULL;
516 alg_data->mif.len = 0;
518 dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
519 __func__, ioread32(I2C_REG_STS(alg_data)));
521 if (completed != num)
522 return ((rc < 0) ? rc : -EREMOTEIO);
527 static u32 i2c_pnx_func(struct i2c_adapter *adapter)
529 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
532 static struct i2c_algorithm pnx_algorithm = {
533 .master_xfer = i2c_pnx_xfer,
534 .functionality = i2c_pnx_func,
538 static int i2c_pnx_controller_suspend(struct platform_device *pdev,
541 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
543 /* FIXME: shouldn't this be clk_disable? */
544 clk_enable(alg_data->clk);
549 static int i2c_pnx_controller_resume(struct platform_device *pdev)
551 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
553 return clk_enable(alg_data->clk);
556 #define i2c_pnx_controller_suspend NULL
557 #define i2c_pnx_controller_resume NULL
560 static int __devinit i2c_pnx_probe(struct platform_device *pdev)
564 struct i2c_pnx_algo_data *alg_data;
566 struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data;
568 if (!i2c_pnx || !i2c_pnx->name) {
569 dev_err(&pdev->dev, "%s: no platform data supplied\n",
575 alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL);
581 platform_set_drvdata(pdev, alg_data);
583 strlcpy(alg_data->adapter.name, i2c_pnx->name,
584 sizeof(alg_data->adapter.name));
585 alg_data->adapter.dev.parent = &pdev->dev;
586 alg_data->adapter.algo = &pnx_algorithm;
587 alg_data->adapter.algo_data = alg_data;
588 alg_data->adapter.nr = pdev->id;
589 alg_data->i2c_pnx = i2c_pnx;
591 alg_data->clk = clk_get(&pdev->dev, NULL);
592 if (IS_ERR(alg_data->clk)) {
593 ret = PTR_ERR(alg_data->clk);
597 init_timer(&alg_data->mif.timer);
598 alg_data->mif.timer.function = i2c_pnx_timeout;
599 alg_data->mif.timer.data = (unsigned long)alg_data;
601 /* Register I/O resource */
602 if (!request_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE,
605 "I/O region 0x%08x for I2C already in use.\n",
611 alg_data->ioaddr = ioremap(i2c_pnx->base, I2C_PNX_REGION_SIZE);
612 if (!alg_data->ioaddr) {
613 dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n");
618 ret = clk_enable(alg_data->clk);
622 freq = clk_get_rate(alg_data->clk);
625 * Clock Divisor High This value is the number of system clocks
626 * the serial clock (SCL) will be high.
627 * For example, if the system clock period is 50 ns and the maximum
628 * desired serial period is 10000 ns (100 kHz), then CLKHI would be
629 * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
630 * programmed into CLKHI will vary from this slightly due to
631 * variations in the output pad's rise and fall times as well as
632 * the deglitching filter length.
635 tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2;
636 iowrite32(tmp, I2C_REG_CKH(alg_data));
637 iowrite32(tmp, I2C_REG_CKL(alg_data));
639 iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
640 if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) {
644 init_completion(&alg_data->mif.complete);
646 ret = request_irq(i2c_pnx->irq, i2c_pnx_interrupt,
647 0, pdev->name, alg_data);
651 /* Register this adapter with the I2C subsystem */
652 ret = i2c_add_numbered_adapter(&alg_data->adapter);
654 dev_err(&pdev->dev, "I2C: Failed to add bus\n");
658 dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
659 alg_data->adapter.name, i2c_pnx->base, i2c_pnx->irq);
664 free_irq(i2c_pnx->irq, alg_data);
666 clk_disable(alg_data->clk);
668 iounmap(alg_data->ioaddr);
670 release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
672 clk_put(alg_data->clk);
676 platform_set_drvdata(pdev, NULL);
681 static int __devexit i2c_pnx_remove(struct platform_device *pdev)
683 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
684 struct i2c_pnx_data *i2c_pnx = alg_data->i2c_pnx;
686 free_irq(i2c_pnx->irq, alg_data);
687 i2c_del_adapter(&alg_data->adapter);
688 clk_disable(alg_data->clk);
689 iounmap(alg_data->ioaddr);
690 release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
691 clk_put(alg_data->clk);
693 platform_set_drvdata(pdev, NULL);
698 static struct platform_driver i2c_pnx_driver = {
701 .owner = THIS_MODULE,
703 .probe = i2c_pnx_probe,
704 .remove = __devexit_p(i2c_pnx_remove),
705 .suspend = i2c_pnx_controller_suspend,
706 .resume = i2c_pnx_controller_resume,
709 static int __init i2c_adap_pnx_init(void)
711 return platform_driver_register(&i2c_pnx_driver);
714 static void __exit i2c_adap_pnx_exit(void)
716 platform_driver_unregister(&i2c_pnx_driver);
719 MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
720 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
721 MODULE_LICENSE("GPL");
722 MODULE_ALIAS("platform:pnx-i2c");
724 /* We need to make sure I2C is initialized before USB */
725 subsys_initcall(i2c_adap_pnx_init);
726 module_exit(i2c_adap_pnx_exit);