2 * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2014, Sony Mobile Communications AB.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/atomic.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dmapool.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/err.h>
24 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
27 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/scatterlist.h>
34 #define QUP_CONFIG 0x000
35 #define QUP_STATE 0x004
36 #define QUP_IO_MODE 0x008
37 #define QUP_SW_RESET 0x00c
38 #define QUP_OPERATIONAL 0x018
39 #define QUP_ERROR_FLAGS 0x01c
40 #define QUP_ERROR_FLAGS_EN 0x020
41 #define QUP_OPERATIONAL_MASK 0x028
42 #define QUP_HW_VERSION 0x030
43 #define QUP_MX_OUTPUT_CNT 0x100
44 #define QUP_OUT_FIFO_BASE 0x110
45 #define QUP_MX_WRITE_CNT 0x150
46 #define QUP_MX_INPUT_CNT 0x200
47 #define QUP_MX_READ_CNT 0x208
48 #define QUP_IN_FIFO_BASE 0x218
49 #define QUP_I2C_CLK_CTL 0x400
50 #define QUP_I2C_STATUS 0x404
51 #define QUP_I2C_MASTER_GEN 0x408
53 /* QUP States and reset values */
54 #define QUP_RESET_STATE 0
55 #define QUP_RUN_STATE 1
56 #define QUP_PAUSE_STATE 3
57 #define QUP_STATE_MASK 3
59 #define QUP_STATE_VALID BIT(2)
60 #define QUP_I2C_MAST_GEN BIT(4)
61 #define QUP_I2C_FLUSH BIT(6)
63 #define QUP_OPERATIONAL_RESET 0x000ff0
64 #define QUP_I2C_STATUS_RESET 0xfffffc
66 /* QUP OPERATIONAL FLAGS */
67 #define QUP_I2C_NACK_FLAG BIT(3)
68 #define QUP_OUT_NOT_EMPTY BIT(4)
69 #define QUP_IN_NOT_EMPTY BIT(5)
70 #define QUP_OUT_FULL BIT(6)
71 #define QUP_OUT_SVC_FLAG BIT(8)
72 #define QUP_IN_SVC_FLAG BIT(9)
73 #define QUP_MX_OUTPUT_DONE BIT(10)
74 #define QUP_MX_INPUT_DONE BIT(11)
76 /* I2C mini core related values */
77 #define QUP_CLOCK_AUTO_GATE BIT(13)
78 #define I2C_MINI_CORE (2 << 8)
80 #define I2C_N_VAL_V2 7
82 /* Most significant word offset in FIFO port */
83 #define QUP_MSW_SHIFT (I2C_N_VAL + 1)
85 /* Packing/Unpacking words in FIFOs, and IO modes */
86 #define QUP_OUTPUT_BLK_MODE (1 << 10)
87 #define QUP_OUTPUT_BAM_MODE (3 << 10)
88 #define QUP_INPUT_BLK_MODE (1 << 12)
89 #define QUP_INPUT_BAM_MODE (3 << 12)
90 #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
91 #define QUP_UNPACK_EN BIT(14)
92 #define QUP_PACK_EN BIT(15)
94 #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
95 #define QUP_V2_TAGS_EN 1
97 #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
98 #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
99 #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
100 #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
103 #define QUP_TAG_START (1 << 8)
104 #define QUP_TAG_DATA (2 << 8)
105 #define QUP_TAG_STOP (3 << 8)
106 #define QUP_TAG_REC (4 << 8)
107 #define QUP_BAM_INPUT_EOT 0x93
108 #define QUP_BAM_FLUSH_STOP 0x96
111 #define QUP_TAG_V2_START 0x81
112 #define QUP_TAG_V2_DATAWR 0x82
113 #define QUP_TAG_V2_DATAWR_STOP 0x83
114 #define QUP_TAG_V2_DATARD 0x85
115 #define QUP_TAG_V2_DATARD_STOP 0x87
117 /* Status, Error flags */
118 #define I2C_STATUS_WR_BUFFER_FULL BIT(0)
119 #define I2C_STATUS_BUS_ACTIVE BIT(8)
120 #define I2C_STATUS_ERROR_MASK 0x38000fc
121 #define QUP_STATUS_ERROR_FLAGS 0x7c
123 #define QUP_READ_LIMIT 256
125 #define RESET_BIT 0x0
127 #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
129 #define MX_TX_RX_LEN SZ_64K
130 #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
132 /* Max timeout in ms for 32k bytes */
135 struct qup_i2c_block {
150 struct qup_i2c_tag tag;
151 struct dma_chan *dma;
152 struct scatterlist *sg;
161 struct i2c_adapter adap;
169 unsigned long one_byte_t;
170 struct qup_i2c_block blk;
173 /* Current posion in user message buffer */
175 /* I2C protocol errors */
177 /* QUP core errors */
180 /* To check if this is the last msg */
183 /* To configure when bus is in run state */
188 struct dma_pool *dpool;
189 struct qup_i2c_tag start_tag;
190 struct qup_i2c_bam brx;
191 struct qup_i2c_bam btx;
193 struct completion xfer;
196 static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
198 struct qup_i2c_dev *qup = dev;
203 bus_err = readl(qup->base + QUP_I2C_STATUS);
204 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
205 opflags = readl(qup->base + QUP_OPERATIONAL);
208 /* Clear Error interrupt */
209 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
213 bus_err &= I2C_STATUS_ERROR_MASK;
214 qup_err &= QUP_STATUS_ERROR_FLAGS;
217 /* Clear Error interrupt */
218 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
223 /* Clear Error interrupt */
224 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
228 if (opflags & QUP_IN_SVC_FLAG)
229 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
231 if (opflags & QUP_OUT_SVC_FLAG)
232 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
235 qup->qup_err = qup_err;
236 qup->bus_err = bus_err;
237 complete(&qup->xfer);
241 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
242 u32 req_state, u32 req_mask)
248 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
249 * cycles. So retry once after a 1uS delay.
252 state = readl(qup->base + QUP_STATE);
254 if (state & QUP_STATE_VALID &&
255 (state & req_mask) == req_state)
264 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
266 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
269 static void qup_i2c_flush(struct qup_i2c_dev *qup)
271 u32 val = readl(qup->base + QUP_STATE);
273 val |= QUP_I2C_FLUSH;
274 writel(val, qup->base + QUP_STATE);
277 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
279 return qup_i2c_poll_state_mask(qup, 0, 0);
282 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
284 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
287 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
289 if (qup_i2c_poll_state_valid(qup) != 0)
292 writel(state, qup->base + QUP_STATE);
294 if (qup_i2c_poll_state(qup, state) != 0)
300 * qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
301 * @qup: The qup_i2c_dev device
302 * @op: The bit/event to wait on
303 * @val: value of the bit to wait on, 0 or 1
304 * @len: The length the bytes to be transferred
306 static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val,
309 unsigned long timeout;
312 u32 shift = __ffs(op);
314 len *= qup->one_byte_t;
315 /* timeout after a wait of twice the max time */
316 timeout = jiffies + len * 4;
319 opflags = readl(qup->base + QUP_OPERATIONAL);
320 status = readl(qup->base + QUP_I2C_STATUS);
322 if (((opflags & op) >> shift) == val) {
323 if ((op == QUP_OUT_NOT_EMPTY) && qup->is_last) {
324 if (!(status & I2C_STATUS_BUS_ACTIVE))
331 if (time_after(jiffies, timeout))
334 usleep_range(len, len * 2);
338 static void qup_i2c_set_write_mode_v2(struct qup_i2c_dev *qup,
341 /* Number of entries to shift out, including the tags */
342 int total = msg->len + qup->blk.tx_tag_len;
344 total |= qup->config_run;
346 if (total < qup->out_fifo_sz) {
348 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
349 writel(total, qup->base + QUP_MX_WRITE_CNT);
351 /* BLOCK mode (transfer data on chunks) */
352 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
353 qup->base + QUP_IO_MODE);
354 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
358 static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
360 /* Number of entries to shift out, including the start */
361 int total = msg->len + 1;
363 if (total < qup->out_fifo_sz) {
365 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
366 writel(total, qup->base + QUP_MX_WRITE_CNT);
368 /* BLOCK mode (transfer data on chunks) */
369 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
370 qup->base + QUP_IO_MODE);
371 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
375 static int check_for_fifo_space(struct qup_i2c_dev *qup)
379 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
383 ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL,
384 RESET_BIT, 4 * ONE_BYTE);
386 /* Fifo is full. Drain out the fifo */
387 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
391 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY,
392 RESET_BIT, 256 * ONE_BYTE);
394 dev_err(qup->dev, "timeout for fifo out full");
398 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
407 static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
409 u32 addr = msg->addr << 1;
416 val = QUP_TAG_START | addr;
423 while (qup->pos < msg->len) {
424 /* Check that there's space in the FIFO for our pair */
425 ret = check_for_fifo_space(qup);
429 if (qup->pos == msg->len - 1)
430 qup_tag = QUP_TAG_STOP;
432 qup_tag = QUP_TAG_DATA;
435 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
437 val = qup_tag | msg->buf[qup->pos];
439 /* Write out the pair and the last odd value */
440 if (idx & 1 || qup->pos == msg->len - 1)
441 writel(val, qup->base + QUP_OUT_FIFO_BASE);
447 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
452 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
455 memset(&qup->blk, 0, sizeof(qup->blk));
457 qup->blk.data_len = msg->len;
458 qup->blk.count = (msg->len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT;
460 /* 4 bytes for first block and 2 writes for rest */
461 qup->blk.tx_tag_len = 4 + (qup->blk.count - 1) * 2;
463 /* There are 2 tag bytes that are read in to fifo for every block */
464 if (msg->flags & I2C_M_RD)
465 qup->blk.rx_tag_len = qup->blk.count * 2;
468 static int qup_i2c_send_data(struct qup_i2c_dev *qup, int tlen, u8 *tbuf,
471 u32 val = 0, idx = 0, pos = 0, i = 0, t;
472 int len = tlen + dlen;
477 ret = check_for_fifo_space(qup);
481 t = (len >= 4) ? 4 : len;
484 if (!i && (pos >= tlen)) {
489 val |= buf[pos++] << (idx++ * 8);
492 writel(val, qup->base + QUP_OUT_FIFO_BASE);
498 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
503 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
507 if (qup->blk.data_len > QUP_READ_LIMIT)
508 data_len = QUP_READ_LIMIT;
510 data_len = qup->blk.data_len;
515 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
516 struct i2c_msg *msg, int is_dma)
518 u16 addr = i2c_8bit_addr_from_msg(msg);
522 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
524 if (qup->blk.pos == 0) {
525 tags[len++] = QUP_TAG_V2_START;
526 tags[len++] = addr & 0xff;
528 if (msg->flags & I2C_M_TEN)
529 tags[len++] = addr >> 8;
532 /* Send _STOP commands for the last block */
534 if (msg->flags & I2C_M_RD)
535 tags[len++] = QUP_TAG_V2_DATARD_STOP;
537 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
539 if (msg->flags & I2C_M_RD)
540 tags[len++] = QUP_TAG_V2_DATARD;
542 tags[len++] = QUP_TAG_V2_DATAWR;
545 data_len = qup_i2c_get_data_len(qup);
547 /* 0 implies 256 bytes */
548 if (data_len == QUP_READ_LIMIT)
551 tags[len++] = data_len;
553 if ((msg->flags & I2C_M_RD) && last && is_dma) {
554 tags[len++] = QUP_BAM_INPUT_EOT;
555 tags[len++] = QUP_BAM_FLUSH_STOP;
561 static int qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
563 int data_len = 0, tag_len, index;
566 tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg, 0);
567 index = msg->len - qup->blk.data_len;
569 /* only tags are written for read */
570 if (!(msg->flags & I2C_M_RD))
571 data_len = qup_i2c_get_data_len(qup);
573 ret = qup_i2c_send_data(qup, tag_len, qup->blk.tags,
574 data_len, &msg->buf[index]);
575 qup->blk.data_len -= data_len;
580 static void qup_i2c_bam_cb(void *data)
582 struct qup_i2c_dev *qup = data;
584 complete(&qup->xfer);
587 static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
588 struct qup_i2c_tag *tg, unsigned int buflen,
589 struct qup_i2c_dev *qup, int map, int dir)
593 sg_set_buf(sg, buf, buflen);
594 ret = dma_map_sg(qup->dev, sg, 1, dir);
599 sg_dma_address(sg) = tg->addr + ((u8 *)buf - tg->start);
604 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
607 dma_release_channel(qup->btx.dma);
609 dma_release_channel(qup->brx.dma);
614 static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
619 qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx");
620 if (IS_ERR(qup->btx.dma)) {
621 err = PTR_ERR(qup->btx.dma);
623 dev_err(qup->dev, "\n tx channel not available");
629 qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx");
630 if (IS_ERR(qup->brx.dma)) {
631 dev_err(qup->dev, "\n rx channel not available");
632 err = PTR_ERR(qup->brx.dma);
634 qup_i2c_rel_dma(qup);
641 static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, struct i2c_msg *msg,
644 struct dma_async_tx_descriptor *txd, *rxd = NULL;
645 int ret = 0, idx = 0, limit = QUP_READ_LIMIT;
646 dma_cookie_t cookie_rx, cookie_tx;
647 u32 rx_nents = 0, tx_nents = 0, len, blocks, rem;
648 u32 i, tlen, tx_len, tx_buf = 0, rx_buf = 0, off = 0;
652 blocks = (msg->len + limit) / limit;
653 rem = msg->len % limit;
654 tx_len = 0, len = 0, i = 0;
656 qup->is_last = (idx == (num - 1));
658 qup_i2c_set_blk_data(qup, msg);
660 if (msg->flags & I2C_M_RD) {
661 rx_nents += (blocks * 2) + 1;
664 while (qup->blk.pos < blocks) {
665 /* length set to '0' implies 256 bytes */
666 tlen = (i == (blocks - 1)) ? rem : 0;
667 tags = &qup->start_tag.start[off + len];
668 len += qup_i2c_set_tags(tags, qup, msg, 1);
670 /* scratch buf to read the start and len tags */
671 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
672 &qup->brx.tag.start[0],
679 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
680 &msg->buf[limit * i],
689 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
690 &qup->start_tag.start[off],
691 &qup->start_tag, len, qup, 0, 0);
696 /* scratch buf to read the BAM EOT and FLUSH tags */
697 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
698 &qup->brx.tag.start[0],
704 tx_nents += (blocks * 2);
706 while (qup->blk.pos < blocks) {
707 tlen = (i == (blocks - 1)) ? rem : 0;
708 tags = &qup->start_tag.start[off + tx_len];
709 len = qup_i2c_set_tags(tags, qup, msg, 1);
711 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
713 &qup->start_tag, len,
719 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
720 &msg->buf[limit * i],
730 if (idx == (num - 1)) {
733 qup->btx.tag.start[0] =
737 qup->btx.tag.start[len - 1] =
739 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
740 &qup->btx.tag.start[0],
752 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_nents,
754 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
756 dev_err(qup->dev, "failed to get tx desc\n");
762 txd->callback = qup_i2c_bam_cb;
763 txd->callback_param = qup;
766 cookie_tx = dmaengine_submit(txd);
767 if (dma_submit_error(cookie_tx)) {
772 dma_async_issue_pending(qup->btx.dma);
775 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
776 rx_nents, DMA_DEV_TO_MEM,
779 dev_err(qup->dev, "failed to get rx desc\n");
782 /* abort TX descriptors */
783 dmaengine_terminate_all(qup->btx.dma);
787 rxd->callback = qup_i2c_bam_cb;
788 rxd->callback_param = qup;
789 cookie_rx = dmaengine_submit(rxd);
790 if (dma_submit_error(cookie_rx)) {
795 dma_async_issue_pending(qup->brx.dma);
798 if (!wait_for_completion_timeout(&qup->xfer, TOUT_MAX * HZ)) {
799 dev_err(qup->dev, "normal trans timed out\n");
803 if (ret || qup->bus_err || qup->qup_err) {
804 if (qup->bus_err & QUP_I2C_NACK_FLAG) {
806 dev_err(qup->dev, "NACK from %x\n", msg->addr);
809 if (qup_i2c_change_state(qup, QUP_RUN_STATE)) {
810 dev_err(qup->dev, "change to run state timed out");
815 writel(QUP_BAM_INPUT_EOT,
816 qup->base + QUP_OUT_FIFO_BASE);
818 writel(QUP_BAM_FLUSH_STOP,
819 qup->base + QUP_OUT_FIFO_BASE);
823 /* wait for remaining interrupts to occur */
824 if (!wait_for_completion_timeout(&qup->xfer, HZ))
825 dev_err(qup->dev, "flush timed out\n");
827 qup_i2c_rel_dma(qup);
831 dma_unmap_sg(qup->dev, qup->btx.sg, tx_nents, DMA_TO_DEVICE);
834 dma_unmap_sg(qup->dev, qup->brx.sg, rx_nents,
840 static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
843 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
846 enable_irq(qup->irq);
847 ret = qup_i2c_req_dma(qup);
855 writel(0, qup->base + QUP_MX_INPUT_CNT);
856 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
859 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
862 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
865 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
869 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
872 ret = qup_i2c_bam_do_xfer(qup, qup->msg, num);
874 disable_irq(qup->irq);
880 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
886 left = wait_for_completion_timeout(&qup->xfer, HZ);
888 writel(1, qup->base + QUP_SW_RESET);
892 if (qup->bus_err || qup->qup_err) {
893 if (qup->bus_err & QUP_I2C_NACK_FLAG) {
894 dev_err(qup->dev, "NACK from %x\n", msg->addr);
902 static int qup_i2c_write_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
908 enable_irq(qup->irq);
909 qup_i2c_set_blk_data(qup, msg);
910 qup_i2c_set_write_mode_v2(qup, msg);
912 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
916 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
919 ret = qup_i2c_issue_xfer_v2(qup, msg);
923 ret = qup_i2c_wait_for_complete(qup, msg);
928 } while (qup->blk.pos < qup->blk.count);
930 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
933 disable_irq(qup->irq);
939 static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
946 enable_irq(qup->irq);
948 qup_i2c_set_write_mode(qup, msg);
950 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
954 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
957 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
961 ret = qup_i2c_issue_write(qup, msg);
965 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
969 ret = qup_i2c_wait_for_complete(qup, msg);
972 } while (qup->pos < msg->len);
974 /* Wait for the outstanding data in the fifo to drain */
975 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
977 disable_irq(qup->irq);
983 static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
985 if (len < qup->in_fifo_sz) {
987 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
988 writel(len, qup->base + QUP_MX_READ_CNT);
990 /* BLOCK mode (transfer data on chunks) */
991 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
992 qup->base + QUP_IO_MODE);
993 writel(len, qup->base + QUP_MX_INPUT_CNT);
997 static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev *qup, int len)
999 int tx_len = qup->blk.tx_tag_len;
1001 len += qup->blk.rx_tag_len;
1002 len |= qup->config_run;
1003 tx_len |= qup->config_run;
1005 if (len < qup->in_fifo_sz) {
1007 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
1008 writel(tx_len, qup->base + QUP_MX_WRITE_CNT);
1009 writel(len, qup->base + QUP_MX_READ_CNT);
1011 /* BLOCK mode (transfer data on chunks) */
1012 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
1013 qup->base + QUP_IO_MODE);
1014 writel(tx_len, qup->base + QUP_MX_OUTPUT_CNT);
1015 writel(len, qup->base + QUP_MX_INPUT_CNT);
1019 static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1023 addr = (msg->addr << 1) | 1;
1025 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
1026 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
1028 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
1029 writel(val, qup->base + QUP_OUT_FIFO_BASE);
1033 static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1039 for (idx = 0; qup->pos < msg->len; idx++) {
1040 if ((idx & 1) == 0) {
1041 /* Check that FIFO have data */
1042 ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
1043 SET_BIT, 4 * ONE_BYTE);
1047 /* Reading 2 words at time */
1048 val = readl(qup->base + QUP_IN_FIFO_BASE);
1050 msg->buf[qup->pos++] = val & 0xFF;
1052 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
1059 static int qup_i2c_read_fifo_v2(struct qup_i2c_dev *qup,
1060 struct i2c_msg *msg)
1063 int idx, pos = 0, ret = 0, total;
1065 total = qup_i2c_get_data_len(qup);
1067 /* 2 extra bytes for read tags */
1068 while (pos < (total + 2)) {
1069 /* Check that FIFO have data */
1070 ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
1071 SET_BIT, 4 * ONE_BYTE);
1073 dev_err(qup->dev, "timeout for fifo not empty");
1076 val = readl(qup->base + QUP_IN_FIFO_BASE);
1078 for (idx = 0; idx < 4; idx++, val >>= 8, pos++) {
1079 /* first 2 bytes are tag bytes */
1083 if (pos >= (total + 2))
1086 msg->buf[qup->pos++] = val & 0xff;
1091 qup->blk.data_len -= total;
1096 static int qup_i2c_read_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1102 enable_irq(qup->irq);
1103 qup_i2c_set_blk_data(qup, msg);
1104 qup_i2c_set_read_mode_v2(qup, msg->len);
1106 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1110 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1113 ret = qup_i2c_issue_xfer_v2(qup, msg);
1117 ret = qup_i2c_wait_for_complete(qup, msg);
1121 ret = qup_i2c_read_fifo_v2(qup, msg);
1126 } while (qup->blk.pos < qup->blk.count);
1129 disable_irq(qup->irq);
1135 static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1142 enable_irq(qup->irq);
1143 qup_i2c_set_read_mode(qup, msg->len);
1145 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1149 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1151 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1155 qup_i2c_issue_read(qup, msg);
1157 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1162 ret = qup_i2c_wait_for_complete(qup, msg);
1166 ret = qup_i2c_read_fifo(qup, msg);
1169 } while (qup->pos < msg->len);
1172 disable_irq(qup->irq);
1178 static int qup_i2c_xfer(struct i2c_adapter *adap,
1179 struct i2c_msg msgs[],
1182 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1185 ret = pm_runtime_get_sync(qup->dev);
1189 writel(1, qup->base + QUP_SW_RESET);
1190 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1194 /* Configure QUP as I2C mini core */
1195 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1197 for (idx = 0; idx < num; idx++) {
1198 if (msgs[idx].len == 0) {
1203 if (qup_i2c_poll_state_i2c_master(qup)) {
1208 if (msgs[idx].flags & I2C_M_RD)
1209 ret = qup_i2c_read_one(qup, &msgs[idx]);
1211 ret = qup_i2c_write_one(qup, &msgs[idx]);
1216 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1225 pm_runtime_mark_last_busy(qup->dev);
1226 pm_runtime_put_autosuspend(qup->dev);
1231 static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1232 struct i2c_msg msgs[],
1235 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1236 int ret, len, idx = 0, use_dma = 0;
1238 ret = pm_runtime_get_sync(qup->dev);
1242 writel(1, qup->base + QUP_SW_RESET);
1243 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1247 /* Configure QUP as I2C mini core */
1248 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1249 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1251 if ((qup->is_dma)) {
1252 /* All i2c_msgs should be transferred using either dma or cpu */
1253 for (idx = 0; idx < num; idx++) {
1254 if (msgs[idx].len == 0) {
1259 len = (msgs[idx].len > qup->out_fifo_sz) ||
1260 (msgs[idx].len > qup->in_fifo_sz);
1262 if ((!is_vmalloc_addr(msgs[idx].buf)) && len) {
1274 if (msgs[idx].len == 0) {
1279 if (qup_i2c_poll_state_i2c_master(qup)) {
1284 qup->is_last = (idx == (num - 1));
1286 qup->config_run = QUP_I2C_MX_CONFIG_DURING_RUN;
1288 qup->config_run = 0;
1290 reinit_completion(&qup->xfer);
1293 ret = qup_i2c_bam_xfer(adap, &msgs[idx], num);
1295 if (msgs[idx].flags & I2C_M_RD)
1296 ret = qup_i2c_read_one_v2(qup, &msgs[idx]);
1298 ret = qup_i2c_write_one_v2(qup, &msgs[idx]);
1300 } while ((idx++ < (num - 1)) && !use_dma && !ret);
1303 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1308 pm_runtime_mark_last_busy(qup->dev);
1309 pm_runtime_put_autosuspend(qup->dev);
1314 static u32 qup_i2c_func(struct i2c_adapter *adap)
1316 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1319 static const struct i2c_algorithm qup_i2c_algo = {
1320 .master_xfer = qup_i2c_xfer,
1321 .functionality = qup_i2c_func,
1324 static const struct i2c_algorithm qup_i2c_algo_v2 = {
1325 .master_xfer = qup_i2c_xfer_v2,
1326 .functionality = qup_i2c_func,
1330 * The QUP block will issue a NACK and STOP on the bus when reaching
1331 * the end of the read, the length of the read is specified as one byte
1332 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1334 static struct i2c_adapter_quirks qup_i2c_quirks = {
1335 .max_read_len = QUP_READ_LIMIT,
1338 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1340 clk_prepare_enable(qup->clk);
1341 clk_prepare_enable(qup->pclk);
1344 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1348 qup_i2c_change_state(qup, QUP_RESET_STATE);
1349 clk_disable_unprepare(qup->clk);
1350 config = readl(qup->base + QUP_CONFIG);
1351 config |= QUP_CLOCK_AUTO_GATE;
1352 writel(config, qup->base + QUP_CONFIG);
1353 clk_disable_unprepare(qup->pclk);
1356 static int qup_i2c_probe(struct platform_device *pdev)
1358 static const int blk_sizes[] = {4, 16, 32};
1359 struct device_node *node = pdev->dev.of_node;
1360 struct qup_i2c_dev *qup;
1361 unsigned long one_bit_t;
1362 struct resource *res;
1363 u32 io_mode, hw_ver, size;
1364 int ret, fs_div, hs_div;
1366 u32 clk_freq = 100000;
1369 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1373 qup->dev = &pdev->dev;
1374 init_completion(&qup->xfer);
1375 platform_set_drvdata(pdev, qup);
1377 of_property_read_u32(node, "clock-frequency", &clk_freq);
1379 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
1380 qup->adap.algo = &qup_i2c_algo;
1381 qup->adap.quirks = &qup_i2c_quirks;
1383 qup->adap.algo = &qup_i2c_algo_v2;
1384 ret = qup_i2c_req_dma(qup);
1386 if (ret == -EPROBE_DEFER)
1391 blocks = (MX_BLOCKS << 1) + 1;
1392 qup->btx.sg = devm_kzalloc(&pdev->dev,
1393 sizeof(*qup->btx.sg) * blocks,
1399 sg_init_table(qup->btx.sg, blocks);
1401 qup->brx.sg = devm_kzalloc(&pdev->dev,
1402 sizeof(*qup->brx.sg) * blocks,
1408 sg_init_table(qup->brx.sg, blocks);
1410 /* 2 tag bytes for each block + 5 for start, stop tags */
1411 size = blocks * 2 + 5;
1412 qup->dpool = dma_pool_create("qup_i2c-dma-pool", &pdev->dev,
1415 qup->start_tag.start = dma_pool_alloc(qup->dpool, GFP_KERNEL,
1416 &qup->start_tag.addr);
1417 if (!qup->start_tag.start) {
1422 qup->brx.tag.start = dma_pool_alloc(qup->dpool,
1424 &qup->brx.tag.addr);
1425 if (!qup->brx.tag.start) {
1430 qup->btx.tag.start = dma_pool_alloc(qup->dpool,
1432 &qup->btx.tag.addr);
1433 if (!qup->btx.tag.start) {
1441 /* We support frequencies up to FAST Mode (400KHz) */
1442 if (!clk_freq || clk_freq > 400000) {
1443 dev_err(qup->dev, "clock frequency not supported %d\n",
1448 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1449 qup->base = devm_ioremap_resource(qup->dev, res);
1450 if (IS_ERR(qup->base))
1451 return PTR_ERR(qup->base);
1453 qup->irq = platform_get_irq(pdev, 0);
1455 dev_err(qup->dev, "No IRQ defined\n");
1459 qup->clk = devm_clk_get(qup->dev, "core");
1460 if (IS_ERR(qup->clk)) {
1461 dev_err(qup->dev, "Could not get core clock\n");
1462 return PTR_ERR(qup->clk);
1465 qup->pclk = devm_clk_get(qup->dev, "iface");
1466 if (IS_ERR(qup->pclk)) {
1467 dev_err(qup->dev, "Could not get iface clock\n");
1468 return PTR_ERR(qup->pclk);
1471 qup_i2c_enable_clocks(qup);
1474 * Bootloaders might leave a pending interrupt on certain QUP's,
1475 * so we reset the core before registering for interrupts.
1477 writel(1, qup->base + QUP_SW_RESET);
1478 ret = qup_i2c_poll_state_valid(qup);
1482 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1483 IRQF_TRIGGER_HIGH, "i2c_qup", qup);
1485 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1488 disable_irq(qup->irq);
1490 hw_ver = readl(qup->base + QUP_HW_VERSION);
1491 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1493 io_mode = readl(qup->base + QUP_IO_MODE);
1496 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1497 * associated with each byte written/received
1499 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1500 if (size >= ARRAY_SIZE(blk_sizes)) {
1504 qup->out_blk_sz = blk_sizes[size] / 2;
1506 size = QUP_INPUT_BLOCK_SIZE(io_mode);
1507 if (size >= ARRAY_SIZE(blk_sizes)) {
1511 qup->in_blk_sz = blk_sizes[size] / 2;
1513 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1514 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1516 size = QUP_INPUT_FIFO_SIZE(io_mode);
1517 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1519 src_clk_freq = clk_get_rate(qup->clk);
1520 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1522 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1525 * Time it takes for a byte to be clocked out on the bus.
1526 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1528 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1529 qup->one_byte_t = one_bit_t * 9;
1531 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1532 qup->in_blk_sz, qup->in_fifo_sz,
1533 qup->out_blk_sz, qup->out_fifo_sz);
1535 i2c_set_adapdata(&qup->adap, qup);
1536 qup->adap.dev.parent = qup->dev;
1537 qup->adap.dev.of_node = pdev->dev.of_node;
1538 qup->is_last = true;
1540 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1542 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1543 pm_runtime_use_autosuspend(qup->dev);
1544 pm_runtime_set_active(qup->dev);
1545 pm_runtime_enable(qup->dev);
1547 ret = i2c_add_adapter(&qup->adap);
1554 pm_runtime_disable(qup->dev);
1555 pm_runtime_set_suspended(qup->dev);
1557 qup_i2c_disable_clocks(qup);
1560 dma_release_channel(qup->btx.dma);
1562 dma_release_channel(qup->brx.dma);
1566 static int qup_i2c_remove(struct platform_device *pdev)
1568 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1571 dma_pool_free(qup->dpool, qup->start_tag.start,
1572 qup->start_tag.addr);
1573 dma_pool_free(qup->dpool, qup->brx.tag.start,
1575 dma_pool_free(qup->dpool, qup->btx.tag.start,
1577 dma_pool_destroy(qup->dpool);
1578 dma_release_channel(qup->btx.dma);
1579 dma_release_channel(qup->brx.dma);
1582 disable_irq(qup->irq);
1583 qup_i2c_disable_clocks(qup);
1584 i2c_del_adapter(&qup->adap);
1585 pm_runtime_disable(qup->dev);
1586 pm_runtime_set_suspended(qup->dev);
1591 static int qup_i2c_pm_suspend_runtime(struct device *device)
1593 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1595 dev_dbg(device, "pm_runtime: suspending...\n");
1596 qup_i2c_disable_clocks(qup);
1600 static int qup_i2c_pm_resume_runtime(struct device *device)
1602 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1604 dev_dbg(device, "pm_runtime: resuming...\n");
1605 qup_i2c_enable_clocks(qup);
1610 #ifdef CONFIG_PM_SLEEP
1611 static int qup_i2c_suspend(struct device *device)
1613 qup_i2c_pm_suspend_runtime(device);
1617 static int qup_i2c_resume(struct device *device)
1619 qup_i2c_pm_resume_runtime(device);
1620 pm_runtime_mark_last_busy(device);
1621 pm_request_autosuspend(device);
1626 static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1627 SET_SYSTEM_SLEEP_PM_OPS(
1631 qup_i2c_pm_suspend_runtime,
1632 qup_i2c_pm_resume_runtime,
1636 static const struct of_device_id qup_i2c_dt_match[] = {
1637 { .compatible = "qcom,i2c-qup-v1.1.1" },
1638 { .compatible = "qcom,i2c-qup-v2.1.1" },
1639 { .compatible = "qcom,i2c-qup-v2.2.1" },
1642 MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
1644 static struct platform_driver qup_i2c_driver = {
1645 .probe = qup_i2c_probe,
1646 .remove = qup_i2c_remove,
1649 .pm = &qup_i2c_qup_pm_ops,
1650 .of_match_table = qup_i2c_dt_match,
1654 module_platform_driver(qup_i2c_driver);
1656 MODULE_LICENSE("GPL v2");
1657 MODULE_ALIAS("platform:i2c_qup");