2 * Driver for the Renesas RCar I2C unit
4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2012-14 Renesas Solutions Corp.
7 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
9 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
10 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
12 * This file used out-of-tree driver i2c-rcar.c
13 * Copyright (C) 2011-2012 Renesas Electronics Corporation
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; version 2 of the License.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/i2c/i2c-rcar.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/of_device.h>
34 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/slab.h>
37 #include <linux/spinlock.h>
39 /* register offsets */
40 #define ICSCR 0x00 /* slave ctrl */
41 #define ICMCR 0x04 /* master ctrl */
42 #define ICSSR 0x08 /* slave status */
43 #define ICMSR 0x0C /* master status */
44 #define ICSIER 0x10 /* slave irq enable */
45 #define ICMIER 0x14 /* master irq enable */
46 #define ICCCR 0x18 /* clock dividers */
47 #define ICSAR 0x1C /* slave address */
48 #define ICMAR 0x20 /* master address */
49 #define ICRXTX 0x24 /* data port */
52 #define MDBS (1 << 7) /* non-fifo mode switch */
53 #define FSCL (1 << 6) /* override SCL pin */
54 #define FSDA (1 << 5) /* override SDA pin */
55 #define OBPC (1 << 4) /* override pins */
56 #define MIE (1 << 3) /* master if enable */
58 #define FSB (1 << 1) /* force stop bit */
59 #define ESG (1 << 0) /* en startbit gen */
61 /* ICMSR (also for ICMIE) */
62 #define MNR (1 << 6) /* nack received */
63 #define MAL (1 << 5) /* arbitration lost */
64 #define MST (1 << 4) /* sent a stop */
68 #define MAT (1 << 0) /* slave addr xfer done */
71 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
72 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
73 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
75 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
76 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
77 #define RCAR_IRQ_STOP (MST)
79 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF)
80 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF)
82 #define ID_LAST_MSG (1 << 0)
83 #define ID_IOERROR (1 << 1)
84 #define ID_DONE (1 << 2)
85 #define ID_ARBLOST (1 << 3)
86 #define ID_NACK (1 << 4)
93 struct rcar_i2c_priv {
95 struct i2c_adapter adap;
100 wait_queue_head_t wait;
105 enum rcar_i2c_type devtype;
108 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
109 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
111 #define rcar_i2c_flags_set(p, f) ((p)->flags |= (f))
112 #define rcar_i2c_flags_has(p, f) ((p)->flags & (f))
114 #define LOOP_TIMEOUT 1024
117 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
119 writel(val, priv->io + reg);
122 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
124 return readl(priv->io + reg);
127 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
131 * slave mode is not used on this driver
133 rcar_i2c_write(priv, ICSIER, 0);
134 rcar_i2c_write(priv, ICSAR, 0);
135 rcar_i2c_write(priv, ICSCR, 0);
136 rcar_i2c_write(priv, ICSSR, 0);
138 /* reset master mode */
139 rcar_i2c_write(priv, ICMIER, 0);
140 rcar_i2c_write(priv, ICMCR, 0);
141 rcar_i2c_write(priv, ICMSR, 0);
142 rcar_i2c_write(priv, ICMAR, 0);
145 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
149 for (i = 0; i < LOOP_TIMEOUT; i++) {
150 /* make sure that bus is not busy */
151 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
159 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
169 switch (priv->devtype) {
177 dev_err(dev, "device type error\n");
182 * calculate SCL clock
186 * ick = clkp / (1 + CDF)
187 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
189 * ick : I2C internal clock < 20 MHz
190 * ticf : I2C SCL falling time = 35 ns here
191 * tr : I2C SCL rising time = 200 ns here
192 * intd : LSI internal delay = 50 ns here
193 * clkp : peripheral_clk
194 * F[] : integer up-valuation
196 rate = clk_get_rate(priv->clk);
197 cdf = rate / 20000000;
198 if (cdf >= 1 << cdf_width) {
199 dev_err(dev, "Input clock %lu too high\n", rate);
202 ick = rate / (cdf + 1);
205 * it is impossible to calculate large scale
206 * number on u32. separate it
208 * F[(ticf + tr + intd) * ick]
209 * = F[(35 + 200 + 50)ns * ick]
210 * = F[285 * ick / 1000000000]
211 * = F[(ick / 1000000) * 285 / 1000]
213 round = (ick + 500000) / 1000000 * 285;
214 round = (round + 500) / 1000;
217 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
219 * Calculation result (= SCL) should be less than
220 * bus_speed for hardware safety
222 * We could use something along the lines of
223 * div = ick / (bus_speed + 1) + 1;
224 * scgd = (div - 20 - round + 7) / 8;
225 * scl = ick / (20 + (scgd * 8) + round);
226 * (not fully verified) but that would get pretty involved
228 for (scgd = 0; scgd < 0x40; scgd++) {
229 scl = ick / (20 + (scgd * 8) + round);
230 if (scl <= bus_speed)
233 dev_err(dev, "it is impossible to calculate best SCL\n");
237 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
238 scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
243 priv->icccr = scgd << cdf_width | cdf;
248 static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
250 int read = !!rcar_i2c_is_recv(priv);
252 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
253 rcar_i2c_write(priv, ICMSR, 0);
254 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
255 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
261 * interrupt functions
263 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
265 struct i2c_msg *msg = priv->msg;
269 * sometimes, unknown interrupt happened.
276 * If address transfer phase finished,
280 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
282 if (priv->pos < msg->len) {
284 * Prepare next data to ICRXTX register.
285 * This data will go to _SHIFT_ register.
288 * [ICRXTX] -> [SHIFT] -> [I2C bus]
290 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
295 * The last data was pushed to ICRXTX on _PREV_ empty irq.
296 * It is on _SHIFT_ register, and will sent to I2C bus.
299 * [ICRXTX] -> [SHIFT] -> [I2C bus]
302 if (priv->flags & ID_LAST_MSG)
304 * If current msg is the _LAST_ msg,
305 * prepare stop condition here.
306 * ID_DONE will be set on STOP irq.
308 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
311 * If current msg is _NOT_ last msg,
312 * it doesn't call stop phase.
313 * thus, there is no STOP irq.
314 * return ID_DONE here.
319 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
324 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
326 struct i2c_msg *msg = priv->msg;
330 * sometimes, unknown interrupt happened.
338 * Address transfer phase finished,
339 * but, there is no data at this point.
342 } else if (priv->pos < msg->len) {
346 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
351 * If next received data is the _LAST_,
353 * otherwise, go to DATA phase.
355 if (priv->pos + 1 >= msg->len)
356 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
358 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
360 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
365 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
367 struct rcar_i2c_priv *priv = ptr;
370 /*-------------- spin lock -----------------*/
371 spin_lock(&priv->lock);
373 msr = rcar_i2c_read(priv, ICMSR);
375 /* Only handle interrupts that are currently enabled */
376 msr &= rcar_i2c_read(priv, ICMIER);
378 /* Arbitration lost */
380 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
386 /* go to stop phase */
387 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
388 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
389 rcar_i2c_flags_set(priv, ID_NACK);
395 rcar_i2c_flags_set(priv, ID_DONE);
399 if (rcar_i2c_is_recv(priv))
400 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
402 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
405 if (rcar_i2c_flags_has(priv, ID_DONE)) {
406 rcar_i2c_write(priv, ICMIER, 0);
407 rcar_i2c_write(priv, ICMSR, 0);
408 wake_up(&priv->wait);
411 spin_unlock(&priv->lock);
412 /*-------------- spin unlock -----------------*/
417 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
418 struct i2c_msg *msgs,
421 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
422 struct device *dev = rcar_i2c_priv_to_dev(priv);
426 pm_runtime_get_sync(dev);
428 /*-------------- spin lock -----------------*/
429 spin_lock_irqsave(&priv->lock, flags);
433 rcar_i2c_write(priv, ICCCR, priv->icccr);
435 spin_unlock_irqrestore(&priv->lock, flags);
436 /*-------------- spin unlock -----------------*/
438 ret = rcar_i2c_bus_barrier(priv);
442 for (i = 0; i < num; i++) {
443 /* This HW can't send STOP after address phase */
444 if (msgs[i].len == 0) {
449 /*-------------- spin lock -----------------*/
450 spin_lock_irqsave(&priv->lock, flags);
453 priv->msg = &msgs[i];
456 if (priv->msg == &msgs[num - 1])
457 rcar_i2c_flags_set(priv, ID_LAST_MSG);
459 ret = rcar_i2c_prepare_msg(priv);
461 spin_unlock_irqrestore(&priv->lock, flags);
462 /*-------------- spin unlock -----------------*/
467 timeout = wait_event_timeout(priv->wait,
468 rcar_i2c_flags_has(priv, ID_DONE),
475 if (rcar_i2c_flags_has(priv, ID_NACK)) {
480 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
485 if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
490 ret = i + 1; /* The number of transfer */
495 if (ret < 0 && ret != -ENXIO)
496 dev_err(dev, "error %d : %x\n", ret, priv->flags);
501 static u32 rcar_i2c_func(struct i2c_adapter *adap)
503 /* This HW can't do SMBUS_QUICK and NOSTART */
504 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
507 static const struct i2c_algorithm rcar_i2c_algo = {
508 .master_xfer = rcar_i2c_master_xfer,
509 .functionality = rcar_i2c_func,
512 static const struct of_device_id rcar_i2c_dt_ids[] = {
513 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
514 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
515 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
516 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
517 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
518 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
519 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
520 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
523 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
525 static int rcar_i2c_probe(struct platform_device *pdev)
527 struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
528 struct rcar_i2c_priv *priv;
529 struct i2c_adapter *adap;
530 struct resource *res;
531 struct device *dev = &pdev->dev;
535 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
539 priv->clk = devm_clk_get(dev, NULL);
540 if (IS_ERR(priv->clk)) {
541 dev_err(dev, "cannot get clock\n");
542 return PTR_ERR(priv->clk);
545 bus_speed = 100000; /* default 100 kHz */
546 ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
547 if (ret < 0 && pdata && pdata->bus_speed)
548 bus_speed = pdata->bus_speed;
550 if (pdev->dev.of_node)
551 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
554 priv->devtype = platform_get_device_id(pdev)->driver_data;
556 ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
560 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
561 priv->io = devm_ioremap_resource(dev, res);
562 if (IS_ERR(priv->io))
563 return PTR_ERR(priv->io);
565 irq = platform_get_irq(pdev, 0);
566 init_waitqueue_head(&priv->wait);
567 spin_lock_init(&priv->lock);
571 adap->algo = &rcar_i2c_algo;
572 adap->class = I2C_CLASS_DEPRECATED;
574 adap->dev.parent = dev;
575 adap->dev.of_node = dev->of_node;
576 i2c_set_adapdata(adap, priv);
577 strlcpy(adap->name, pdev->name, sizeof(adap->name));
579 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
580 dev_name(dev), priv);
582 dev_err(dev, "cannot get irq %d\n", irq);
586 ret = i2c_add_numbered_adapter(adap);
588 dev_err(dev, "reg adap failed: %d\n", ret);
592 pm_runtime_enable(dev);
593 platform_set_drvdata(pdev, priv);
595 dev_info(dev, "probed\n");
600 static int rcar_i2c_remove(struct platform_device *pdev)
602 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
603 struct device *dev = &pdev->dev;
605 i2c_del_adapter(&priv->adap);
606 pm_runtime_disable(dev);
611 static struct platform_device_id rcar_i2c_id_table[] = {
612 { "i2c-rcar", I2C_RCAR_GEN1 },
613 { "i2c-rcar_gen1", I2C_RCAR_GEN1 },
614 { "i2c-rcar_gen2", I2C_RCAR_GEN2 },
617 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
619 static struct platform_driver rcar_i2c_driver = {
622 .owner = THIS_MODULE,
623 .of_match_table = rcar_i2c_dt_ids,
625 .probe = rcar_i2c_probe,
626 .remove = rcar_i2c_remove,
627 .id_table = rcar_i2c_id_table,
630 module_platform_driver(rcar_i2c_driver);
632 MODULE_LICENSE("GPL v2");
633 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
634 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");