1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3 * Copyright (C) 2004,2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 I2C Controller
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/i2c.h>
27 #include <linux/i2c-id.h>
28 #include <linux/init.h>
29 #include <linux/time.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/errno.h>
33 #include <linux/err.h>
34 #include <linux/platform_device.h>
35 #include <linux/clk.h>
36 #include <linux/cpufreq.h>
41 #include <asm/plat-s3c/regs-iic.h>
42 #include <asm/plat-s3c/iic.h>
44 /* i2c controller state */
46 enum s3c24xx_i2c_state {
56 wait_queue_head_t wait;
63 unsigned int tx_setup;
66 enum s3c24xx_i2c_state state;
67 unsigned long clkrate;
72 struct resource *ioarea;
73 struct i2c_adapter adap;
75 #ifdef CONFIG_CPU_FREQ
76 struct notifier_block freq_transition;
80 /* default platform data removed, dev should always carry data. */
82 /* s3c24xx_i2c_is2440()
84 * return true is this is an s3c2440
87 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
89 struct platform_device *pdev = to_platform_device(i2c->dev);
91 return !strcmp(pdev->name, "s3c2440-i2c");
94 /* s3c24xx_i2c_master_complete
96 * complete the message and wake up the caller, using the given return code,
100 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
102 dev_dbg(i2c->dev, "master_complete %d\n", ret);
114 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
118 tmp = readl(i2c->regs + S3C2410_IICCON);
119 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
122 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
126 tmp = readl(i2c->regs + S3C2410_IICCON);
127 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
130 /* irq enable/disable functions */
132 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
136 tmp = readl(i2c->regs + S3C2410_IICCON);
137 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
140 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
144 tmp = readl(i2c->regs + S3C2410_IICCON);
145 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
149 /* s3c24xx_i2c_message_start
151 * put the start of a message onto the bus
154 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
157 unsigned int addr = (msg->addr & 0x7f) << 1;
159 unsigned long iiccon;
162 stat |= S3C2410_IICSTAT_TXRXEN;
164 if (msg->flags & I2C_M_RD) {
165 stat |= S3C2410_IICSTAT_MASTER_RX;
168 stat |= S3C2410_IICSTAT_MASTER_TX;
170 if (msg->flags & I2C_M_REV_DIR_ADDR)
173 /* todo - check for wether ack wanted or not */
174 s3c24xx_i2c_enable_ack(i2c);
176 iiccon = readl(i2c->regs + S3C2410_IICCON);
177 writel(stat, i2c->regs + S3C2410_IICSTAT);
179 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
180 writeb(addr, i2c->regs + S3C2410_IICDS);
182 /* delay here to ensure the data byte has gotten onto the bus
183 * before the transaction is started */
185 ndelay(i2c->tx_setup);
187 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
188 writel(iiccon, i2c->regs + S3C2410_IICCON);
190 stat |= S3C2410_IICSTAT_START;
191 writel(stat, i2c->regs + S3C2410_IICSTAT);
194 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
196 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
198 dev_dbg(i2c->dev, "STOP\n");
200 /* stop the transfer */
201 iicstat &= ~S3C2410_IICSTAT_START;
202 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
204 i2c->state = STATE_STOP;
206 s3c24xx_i2c_master_complete(i2c, ret);
207 s3c24xx_i2c_disable_irq(i2c);
210 /* helper functions to determine the current state in the set of
211 * messages we are sending */
215 * returns TRUE if the current message is the last in the set
218 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
220 return i2c->msg_idx >= (i2c->msg_num - 1);
225 * returns TRUE if we this is the last byte in the current message
228 static inline int is_msglast(struct s3c24xx_i2c *i2c)
230 return i2c->msg_ptr == i2c->msg->len-1;
235 * returns TRUE if we reached the end of the current message
238 static inline int is_msgend(struct s3c24xx_i2c *i2c)
240 return i2c->msg_ptr >= i2c->msg->len;
243 /* i2s_s3c_irq_nextbyte
245 * process an interrupt and work out what to do
248 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
254 switch (i2c->state) {
257 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
262 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
263 s3c24xx_i2c_disable_irq(i2c);
267 /* last thing we did was send a start condition on the
268 * bus, or started a new i2c message
271 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
272 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
273 /* ack was not received... */
275 dev_dbg(i2c->dev, "ack was not received\n");
276 s3c24xx_i2c_stop(i2c, -ENXIO);
280 if (i2c->msg->flags & I2C_M_RD)
281 i2c->state = STATE_READ;
283 i2c->state = STATE_WRITE;
285 /* terminate the transfer if there is nothing to do
286 * as this is used by the i2c probe to find devices. */
288 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
289 s3c24xx_i2c_stop(i2c, 0);
293 if (i2c->state == STATE_READ)
296 /* fall through to the write state, as we will need to
297 * send a byte as well */
300 /* we are writing data to the device... check for the
301 * end of the message, and if so, work out what to do
304 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
305 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
306 dev_dbg(i2c->dev, "WRITE: No Ack\n");
308 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
315 if (!is_msgend(i2c)) {
316 byte = i2c->msg->buf[i2c->msg_ptr++];
317 writeb(byte, i2c->regs + S3C2410_IICDS);
319 /* delay after writing the byte to allow the
320 * data setup time on the bus, as writing the
321 * data to the register causes the first bit
322 * to appear on SDA, and SCL will change as
323 * soon as the interrupt is acknowledged */
325 ndelay(i2c->tx_setup);
327 } else if (!is_lastmsg(i2c)) {
328 /* we need to go to the next i2c message */
330 dev_dbg(i2c->dev, "WRITE: Next Message\n");
336 /* check to see if we need to do another message */
337 if (i2c->msg->flags & I2C_M_NOSTART) {
339 if (i2c->msg->flags & I2C_M_RD) {
340 /* cannot do this, the controller
341 * forces us to send a new START
342 * when we change direction */
344 s3c24xx_i2c_stop(i2c, -EINVAL);
349 /* send the new start */
350 s3c24xx_i2c_message_start(i2c, i2c->msg);
351 i2c->state = STATE_START;
357 s3c24xx_i2c_stop(i2c, 0);
362 /* we have a byte of data in the data register, do
363 * something with it, and then work out wether we are
364 * going to do any more read/write
367 byte = readb(i2c->regs + S3C2410_IICDS);
368 i2c->msg->buf[i2c->msg_ptr++] = byte;
371 if (is_msglast(i2c)) {
372 /* last byte of buffer */
375 s3c24xx_i2c_disable_ack(i2c);
377 } else if (is_msgend(i2c)) {
378 /* ok, we've read the entire buffer, see if there
379 * is anything else we need to do */
381 if (is_lastmsg(i2c)) {
382 /* last message, send stop and complete */
383 dev_dbg(i2c->dev, "READ: Send Stop\n");
385 s3c24xx_i2c_stop(i2c, 0);
387 /* go to the next transfer */
388 dev_dbg(i2c->dev, "READ: Next Transfer\n");
399 /* acknowlegde the IRQ and get back on with the work */
402 tmp = readl(i2c->regs + S3C2410_IICCON);
403 tmp &= ~S3C2410_IICCON_IRQPEND;
404 writel(tmp, i2c->regs + S3C2410_IICCON);
411 * top level IRQ servicing routine
414 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
416 struct s3c24xx_i2c *i2c = dev_id;
417 unsigned long status;
420 status = readl(i2c->regs + S3C2410_IICSTAT);
422 if (status & S3C2410_IICSTAT_ARBITR) {
423 /* deal with arbitration loss */
424 dev_err(i2c->dev, "deal with arbitration loss\n");
427 if (i2c->state == STATE_IDLE) {
428 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
430 tmp = readl(i2c->regs + S3C2410_IICCON);
431 tmp &= ~S3C2410_IICCON_IRQPEND;
432 writel(tmp, i2c->regs + S3C2410_IICCON);
436 /* pretty much this leaves us with the fact that we've
437 * transmitted or received whatever byte we last sent */
439 i2s_s3c_irq_nextbyte(i2c, status);
446 /* s3c24xx_i2c_set_master
448 * get the i2c bus for a master transaction
451 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
453 unsigned long iicstat;
456 while (timeout-- > 0) {
457 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
459 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
468 /* s3c24xx_i2c_doxfer
470 * this starts an i2c transfer
473 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
474 struct i2c_msg *msgs, int num)
476 unsigned long timeout;
479 if (!(readl(i2c->regs + S3C2410_IICCON) & S3C2410_IICCON_IRQEN))
482 ret = s3c24xx_i2c_set_master(i2c);
484 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
489 spin_lock_irq(&i2c->lock);
495 i2c->state = STATE_START;
497 s3c24xx_i2c_enable_irq(i2c);
498 s3c24xx_i2c_message_start(i2c, msgs);
499 spin_unlock_irq(&i2c->lock);
501 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
505 /* having these next two as dev_err() makes life very
506 * noisy when doing an i2cdetect */
509 dev_dbg(i2c->dev, "timeout\n");
511 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
513 /* ensure the stop has been through the bus */
523 * first port of call from the i2c bus code when an message needs
524 * transferring across the i2c bus.
527 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
528 struct i2c_msg *msgs, int num)
530 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
534 for (retry = 0; retry < adap->retries; retry++) {
536 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
541 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
549 /* declare our i2c functionality */
550 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
552 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
555 /* i2c bus registration info */
557 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
558 .master_xfer = s3c24xx_i2c_xfer,
559 .functionality = s3c24xx_i2c_func,
562 /* s3c24xx_i2c_calcdivisor
564 * return the divisor settings for a given frequency
567 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
568 unsigned int *div1, unsigned int *divs)
570 unsigned int calc_divs = clkin / wanted;
571 unsigned int calc_div1;
573 if (calc_divs > (16*16))
578 calc_divs += calc_div1-1;
579 calc_divs /= calc_div1;
589 return clkin / (calc_divs * calc_div1);
594 * test wether a frequency is within the acceptable range of error
597 static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
599 int diff = freq - wanted;
601 return diff >= -2 && diff <= 2;
604 /* s3c24xx_i2c_clockrate
606 * work out a divisor for the user requested frequency setting,
607 * either by the requested frequency, or scanning the acceptable
608 * range of frequencies until something is found
611 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
613 struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
614 unsigned long clkin = clk_get_rate(i2c->clk);
615 unsigned int divs, div1;
620 i2c->clkrate = clkin;
621 clkin /= 1000; /* clkin now in KHz */
623 dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
624 pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
626 if (pdata->bus_freq != 0) {
627 freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
629 if (freq_acceptable(freq, pdata->bus_freq/1000))
633 /* ok, we may have to search for something suitable... */
635 start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
636 end = pdata->min_freq;
643 for (; start > end; start--) {
644 freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
645 if (freq_acceptable(freq, start))
649 /* cannot find frequency spec */
656 iiccon = readl(i2c->regs + S3C2410_IICCON);
657 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
661 iiccon |= S3C2410_IICCON_TXDIV_512;
663 writel(iiccon, i2c->regs + S3C2410_IICCON);
668 #ifdef CONFIG_CPU_FREQ
670 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
672 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
673 unsigned long val, void *data)
675 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
681 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
683 /* if we're post-change and the input clock has slowed down
684 * or at pre-change and the clock is about to speed up, then
685 * adjust our clock rate. <0 is slow, >0 speedup.
688 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
689 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
690 spin_lock_irqsave(&i2c->lock, flags);
691 ret = s3c24xx_i2c_clockrate(i2c, &got);
692 spin_unlock_irqrestore(&i2c->lock, flags);
695 dev_err(i2c->dev, "cannot find frequency\n");
697 dev_info(i2c->dev, "setting freq %d\n", got);
703 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
705 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
707 return cpufreq_register_notifier(&i2c->freq_transition,
708 CPUFREQ_TRANSITION_NOTIFIER);
711 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
713 cpufreq_unregister_notifier(&i2c->freq_transition,
714 CPUFREQ_TRANSITION_NOTIFIER);
718 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
723 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
730 * initialise the controller, set the IO lines and frequency
733 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
735 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
736 struct s3c2410_platform_i2c *pdata;
739 /* get the plafrom data */
741 pdata = i2c->dev->platform_data;
743 /* inititalise the gpio */
746 pdata->cfg_gpio(to_platform_device(i2c->dev));
748 /* write slave address */
750 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
752 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
754 writel(iicon, i2c->regs + S3C2410_IICCON);
756 /* we need to work out the divisors for the clock... */
758 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
759 writel(0, i2c->regs + S3C2410_IICCON);
760 dev_err(i2c->dev, "cannot meet bus frequency required\n");
764 /* todo - check that the i2c lines aren't being dragged anywhere */
766 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
767 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
769 /* check for s3c2440 i2c controller */
771 if (s3c24xx_i2c_is2440(i2c)) {
772 dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
774 writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
782 * called by the bus driver when a suitable device is found
785 static int s3c24xx_i2c_probe(struct platform_device *pdev)
787 struct s3c24xx_i2c *i2c;
788 struct s3c2410_platform_i2c *pdata;
789 struct resource *res;
792 pdata = pdev->dev.platform_data;
794 dev_err(&pdev->dev, "no platform data\n");
798 i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
800 dev_err(&pdev->dev, "no memory for state\n");
804 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
805 i2c->adap.owner = THIS_MODULE;
806 i2c->adap.algo = &s3c24xx_i2c_algorithm;
807 i2c->adap.retries = 2;
808 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
811 spin_lock_init(&i2c->lock);
812 init_waitqueue_head(&i2c->wait);
814 /* find the clock and enable it */
816 i2c->dev = &pdev->dev;
817 i2c->clk = clk_get(&pdev->dev, "i2c");
818 if (IS_ERR(i2c->clk)) {
819 dev_err(&pdev->dev, "cannot get clock\n");
824 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
826 clk_enable(i2c->clk);
828 /* map the registers */
830 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
832 dev_err(&pdev->dev, "cannot find IO resource\n");
837 i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
840 if (i2c->ioarea == NULL) {
841 dev_err(&pdev->dev, "cannot request IO\n");
846 i2c->regs = ioremap(res->start, (res->end-res->start)+1);
848 if (i2c->regs == NULL) {
849 dev_err(&pdev->dev, "cannot map IO\n");
854 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
855 i2c->regs, i2c->ioarea, res);
857 /* setup info block for the i2c core */
859 i2c->adap.algo_data = i2c;
860 i2c->adap.dev.parent = &pdev->dev;
862 /* initialise the i2c controller */
864 ret = s3c24xx_i2c_init(i2c);
868 /* find the IRQ for this unit (note, this relies on the init call to
869 * ensure no current IRQs pending
872 i2c->irq = ret = platform_get_irq(pdev, 0);
874 dev_err(&pdev->dev, "cannot find IRQ\n");
878 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
879 dev_name(&pdev->dev), i2c);
882 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
886 ret = s3c24xx_i2c_register_cpufreq(i2c);
888 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
892 /* Note, previous versions of the driver used i2c_add_adapter()
893 * to add the bus at any number. We now pass the bus number via
894 * the platform data, so if unset it will now default to always
898 i2c->adap.nr = pdata->bus_num;
900 ret = i2c_add_numbered_adapter(&i2c->adap);
902 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
906 platform_set_drvdata(pdev, i2c);
908 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
912 s3c24xx_i2c_deregister_cpufreq(i2c);
915 free_irq(i2c->irq, i2c);
921 release_resource(i2c->ioarea);
925 clk_disable(i2c->clk);
933 /* s3c24xx_i2c_remove
935 * called when device is removed from the bus
938 static int s3c24xx_i2c_remove(struct platform_device *pdev)
940 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
942 s3c24xx_i2c_deregister_cpufreq(i2c);
944 i2c_del_adapter(&i2c->adap);
945 free_irq(i2c->irq, i2c);
947 clk_disable(i2c->clk);
952 release_resource(i2c->ioarea);
960 static int s3c24xx_i2c_resume(struct platform_device *dev)
962 struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
965 s3c24xx_i2c_init(i2c);
971 #define s3c24xx_i2c_resume NULL
974 /* device driver for platform bus bits */
976 static struct platform_driver s3c2410_i2c_driver = {
977 .probe = s3c24xx_i2c_probe,
978 .remove = s3c24xx_i2c_remove,
979 .resume = s3c24xx_i2c_resume,
981 .owner = THIS_MODULE,
982 .name = "s3c2410-i2c",
986 static struct platform_driver s3c2440_i2c_driver = {
987 .probe = s3c24xx_i2c_probe,
988 .remove = s3c24xx_i2c_remove,
989 .resume = s3c24xx_i2c_resume,
991 .owner = THIS_MODULE,
992 .name = "s3c2440-i2c",
996 static int __init i2c_adap_s3c_init(void)
1000 ret = platform_driver_register(&s3c2410_i2c_driver);
1002 ret = platform_driver_register(&s3c2440_i2c_driver);
1004 platform_driver_unregister(&s3c2410_i2c_driver);
1010 static void __exit i2c_adap_s3c_exit(void)
1012 platform_driver_unregister(&s3c2410_i2c_driver);
1013 platform_driver_unregister(&s3c2440_i2c_driver);
1016 module_init(i2c_adap_s3c_init);
1017 module_exit(i2c_adap_s3c_exit);
1019 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1020 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1021 MODULE_LICENSE("GPL");
1022 MODULE_ALIAS("platform:s3c2410-i2c");
1023 MODULE_ALIAS("platform:s3c2440-i2c");