1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3 * Copyright (C) 2004,2005,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 I2C Controller
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/i2c.h>
27 #include <linux/init.h>
28 #include <linux/time.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/errno.h>
32 #include <linux/err.h>
33 #include <linux/platform_device.h>
34 #include <linux/clk.h>
35 #include <linux/cpufreq.h>
36 #include <linux/slab.h>
41 #include <plat/regs-iic.h>
44 /* i2c controller state */
46 enum s3c24xx_i2c_state {
54 enum s3c24xx_i2c_type {
61 wait_queue_head_t wait;
62 unsigned int suspended:1;
69 unsigned int tx_setup;
72 enum s3c24xx_i2c_state state;
73 unsigned long clkrate;
78 struct resource *ioarea;
79 struct i2c_adapter adap;
81 #ifdef CONFIG_CPU_FREQ
82 struct notifier_block freq_transition;
86 /* default platform data removed, dev should always carry data. */
88 /* s3c24xx_i2c_is2440()
90 * return true is this is an s3c2440
93 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
95 struct platform_device *pdev = to_platform_device(i2c->dev);
96 enum s3c24xx_i2c_type type;
98 type = platform_get_device_id(pdev)->driver_data;
99 return type == TYPE_S3C2440;
102 /* s3c24xx_i2c_master_complete
104 * complete the message and wake up the caller, using the given return code,
105 * or zero to mean ok.
108 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
110 dev_dbg(i2c->dev, "master_complete %d\n", ret);
122 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
126 tmp = readl(i2c->regs + S3C2410_IICCON);
127 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
130 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
134 tmp = readl(i2c->regs + S3C2410_IICCON);
135 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
138 /* irq enable/disable functions */
140 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
144 tmp = readl(i2c->regs + S3C2410_IICCON);
145 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
148 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
152 tmp = readl(i2c->regs + S3C2410_IICCON);
153 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
157 /* s3c24xx_i2c_message_start
159 * put the start of a message onto the bus
162 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
165 unsigned int addr = (msg->addr & 0x7f) << 1;
167 unsigned long iiccon;
170 stat |= S3C2410_IICSTAT_TXRXEN;
172 if (msg->flags & I2C_M_RD) {
173 stat |= S3C2410_IICSTAT_MASTER_RX;
176 stat |= S3C2410_IICSTAT_MASTER_TX;
178 if (msg->flags & I2C_M_REV_DIR_ADDR)
181 /* todo - check for wether ack wanted or not */
182 s3c24xx_i2c_enable_ack(i2c);
184 iiccon = readl(i2c->regs + S3C2410_IICCON);
185 writel(stat, i2c->regs + S3C2410_IICSTAT);
187 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
188 writeb(addr, i2c->regs + S3C2410_IICDS);
190 /* delay here to ensure the data byte has gotten onto the bus
191 * before the transaction is started */
193 ndelay(i2c->tx_setup);
195 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
196 writel(iiccon, i2c->regs + S3C2410_IICCON);
198 stat |= S3C2410_IICSTAT_START;
199 writel(stat, i2c->regs + S3C2410_IICSTAT);
202 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
204 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
206 dev_dbg(i2c->dev, "STOP\n");
208 /* stop the transfer */
209 iicstat &= ~S3C2410_IICSTAT_START;
210 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
212 i2c->state = STATE_STOP;
214 s3c24xx_i2c_master_complete(i2c, ret);
215 s3c24xx_i2c_disable_irq(i2c);
218 /* helper functions to determine the current state in the set of
219 * messages we are sending */
223 * returns TRUE if the current message is the last in the set
226 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
228 return i2c->msg_idx >= (i2c->msg_num - 1);
233 * returns TRUE if we this is the last byte in the current message
236 static inline int is_msglast(struct s3c24xx_i2c *i2c)
238 return i2c->msg_ptr == i2c->msg->len-1;
243 * returns TRUE if we reached the end of the current message
246 static inline int is_msgend(struct s3c24xx_i2c *i2c)
248 return i2c->msg_ptr >= i2c->msg->len;
251 /* i2s_s3c_irq_nextbyte
253 * process an interrupt and work out what to do
256 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
262 switch (i2c->state) {
265 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
270 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
271 s3c24xx_i2c_disable_irq(i2c);
275 /* last thing we did was send a start condition on the
276 * bus, or started a new i2c message
279 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
280 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
281 /* ack was not received... */
283 dev_dbg(i2c->dev, "ack was not received\n");
284 s3c24xx_i2c_stop(i2c, -ENXIO);
288 if (i2c->msg->flags & I2C_M_RD)
289 i2c->state = STATE_READ;
291 i2c->state = STATE_WRITE;
293 /* terminate the transfer if there is nothing to do
294 * as this is used by the i2c probe to find devices. */
296 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
297 s3c24xx_i2c_stop(i2c, 0);
301 if (i2c->state == STATE_READ)
304 /* fall through to the write state, as we will need to
305 * send a byte as well */
308 /* we are writing data to the device... check for the
309 * end of the message, and if so, work out what to do
312 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
313 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
314 dev_dbg(i2c->dev, "WRITE: No Ack\n");
316 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
323 if (!is_msgend(i2c)) {
324 byte = i2c->msg->buf[i2c->msg_ptr++];
325 writeb(byte, i2c->regs + S3C2410_IICDS);
327 /* delay after writing the byte to allow the
328 * data setup time on the bus, as writing the
329 * data to the register causes the first bit
330 * to appear on SDA, and SCL will change as
331 * soon as the interrupt is acknowledged */
333 ndelay(i2c->tx_setup);
335 } else if (!is_lastmsg(i2c)) {
336 /* we need to go to the next i2c message */
338 dev_dbg(i2c->dev, "WRITE: Next Message\n");
344 /* check to see if we need to do another message */
345 if (i2c->msg->flags & I2C_M_NOSTART) {
347 if (i2c->msg->flags & I2C_M_RD) {
348 /* cannot do this, the controller
349 * forces us to send a new START
350 * when we change direction */
352 s3c24xx_i2c_stop(i2c, -EINVAL);
357 /* send the new start */
358 s3c24xx_i2c_message_start(i2c, i2c->msg);
359 i2c->state = STATE_START;
365 s3c24xx_i2c_stop(i2c, 0);
370 /* we have a byte of data in the data register, do
371 * something with it, and then work out wether we are
372 * going to do any more read/write
375 byte = readb(i2c->regs + S3C2410_IICDS);
376 i2c->msg->buf[i2c->msg_ptr++] = byte;
379 if (is_msglast(i2c)) {
380 /* last byte of buffer */
383 s3c24xx_i2c_disable_ack(i2c);
385 } else if (is_msgend(i2c)) {
386 /* ok, we've read the entire buffer, see if there
387 * is anything else we need to do */
389 if (is_lastmsg(i2c)) {
390 /* last message, send stop and complete */
391 dev_dbg(i2c->dev, "READ: Send Stop\n");
393 s3c24xx_i2c_stop(i2c, 0);
395 /* go to the next transfer */
396 dev_dbg(i2c->dev, "READ: Next Transfer\n");
407 /* acknowlegde the IRQ and get back on with the work */
410 tmp = readl(i2c->regs + S3C2410_IICCON);
411 tmp &= ~S3C2410_IICCON_IRQPEND;
412 writel(tmp, i2c->regs + S3C2410_IICCON);
419 * top level IRQ servicing routine
422 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
424 struct s3c24xx_i2c *i2c = dev_id;
425 unsigned long status;
428 status = readl(i2c->regs + S3C2410_IICSTAT);
430 if (status & S3C2410_IICSTAT_ARBITR) {
431 /* deal with arbitration loss */
432 dev_err(i2c->dev, "deal with arbitration loss\n");
435 if (i2c->state == STATE_IDLE) {
436 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
438 tmp = readl(i2c->regs + S3C2410_IICCON);
439 tmp &= ~S3C2410_IICCON_IRQPEND;
440 writel(tmp, i2c->regs + S3C2410_IICCON);
444 /* pretty much this leaves us with the fact that we've
445 * transmitted or received whatever byte we last sent */
447 i2s_s3c_irq_nextbyte(i2c, status);
454 /* s3c24xx_i2c_set_master
456 * get the i2c bus for a master transaction
459 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
461 unsigned long iicstat;
464 while (timeout-- > 0) {
465 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
467 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
476 /* s3c24xx_i2c_doxfer
478 * this starts an i2c transfer
481 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
482 struct i2c_msg *msgs, int num)
484 unsigned long iicstat, timeout;
491 ret = s3c24xx_i2c_set_master(i2c);
493 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
498 spin_lock_irq(&i2c->lock);
504 i2c->state = STATE_START;
506 s3c24xx_i2c_enable_irq(i2c);
507 s3c24xx_i2c_message_start(i2c, msgs);
508 spin_unlock_irq(&i2c->lock);
510 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
514 /* having these next two as dev_err() makes life very
515 * noisy when doing an i2cdetect */
518 dev_dbg(i2c->dev, "timeout\n");
520 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
522 /* ensure the stop has been through the bus */
524 dev_dbg(i2c->dev, "waiting for bus idle\n");
526 /* first, try busy waiting briefly */
528 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
529 } while ((iicstat & S3C2410_IICSTAT_START) && --spins);
531 /* if that timed out sleep */
534 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
537 if (iicstat & S3C2410_IICSTAT_START)
538 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
546 * first port of call from the i2c bus code when an message needs
547 * transferring across the i2c bus.
550 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
551 struct i2c_msg *msgs, int num)
553 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
557 for (retry = 0; retry < adap->retries; retry++) {
559 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
564 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
572 /* declare our i2c functionality */
573 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
575 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
578 /* i2c bus registration info */
580 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
581 .master_xfer = s3c24xx_i2c_xfer,
582 .functionality = s3c24xx_i2c_func,
585 /* s3c24xx_i2c_calcdivisor
587 * return the divisor settings for a given frequency
590 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
591 unsigned int *div1, unsigned int *divs)
593 unsigned int calc_divs = clkin / wanted;
594 unsigned int calc_div1;
596 if (calc_divs > (16*16))
601 calc_divs += calc_div1-1;
602 calc_divs /= calc_div1;
612 return clkin / (calc_divs * calc_div1);
615 /* s3c24xx_i2c_clockrate
617 * work out a divisor for the user requested frequency setting,
618 * either by the requested frequency, or scanning the acceptable
619 * range of frequencies until something is found
622 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
624 struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
625 unsigned long clkin = clk_get_rate(i2c->clk);
626 unsigned int divs, div1;
627 unsigned long target_frequency;
631 i2c->clkrate = clkin;
632 clkin /= 1000; /* clkin now in KHz */
634 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
636 target_frequency = pdata->frequency ? pdata->frequency : 100000;
638 target_frequency /= 1000; /* Target frequency now in KHz */
640 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
642 if (freq > target_frequency) {
644 "Unable to achieve desired frequency %luKHz." \
645 " Lowest achievable %dKHz\n", target_frequency, freq);
651 iiccon = readl(i2c->regs + S3C2410_IICCON);
652 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
656 iiccon |= S3C2410_IICCON_TXDIV_512;
658 writel(iiccon, i2c->regs + S3C2410_IICCON);
660 if (s3c24xx_i2c_is2440(i2c)) {
661 unsigned long sda_delay;
663 if (pdata->sda_delay) {
664 sda_delay = clkin * pdata->sda_delay;
665 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
666 sda_delay = DIV_ROUND_UP(sda_delay, 5);
669 sda_delay |= S3C2410_IICLC_FILTER_ON;
673 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
674 writel(sda_delay, i2c->regs + S3C2440_IICLC);
680 #ifdef CONFIG_CPU_FREQ
682 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
684 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
685 unsigned long val, void *data)
687 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
693 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
695 /* if we're post-change and the input clock has slowed down
696 * or at pre-change and the clock is about to speed up, then
697 * adjust our clock rate. <0 is slow, >0 speedup.
700 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
701 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
702 spin_lock_irqsave(&i2c->lock, flags);
703 ret = s3c24xx_i2c_clockrate(i2c, &got);
704 spin_unlock_irqrestore(&i2c->lock, flags);
707 dev_err(i2c->dev, "cannot find frequency\n");
709 dev_info(i2c->dev, "setting freq %d\n", got);
715 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
717 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
719 return cpufreq_register_notifier(&i2c->freq_transition,
720 CPUFREQ_TRANSITION_NOTIFIER);
723 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
725 cpufreq_unregister_notifier(&i2c->freq_transition,
726 CPUFREQ_TRANSITION_NOTIFIER);
730 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
735 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
742 * initialise the controller, set the IO lines and frequency
745 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
747 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
748 struct s3c2410_platform_i2c *pdata;
751 /* get the plafrom data */
753 pdata = i2c->dev->platform_data;
755 /* inititalise the gpio */
758 pdata->cfg_gpio(to_platform_device(i2c->dev));
760 /* write slave address */
762 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
764 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
766 writel(iicon, i2c->regs + S3C2410_IICCON);
768 /* we need to work out the divisors for the clock... */
770 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
771 writel(0, i2c->regs + S3C2410_IICCON);
772 dev_err(i2c->dev, "cannot meet bus frequency required\n");
776 /* todo - check that the i2c lines aren't being dragged anywhere */
778 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
779 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
786 * called by the bus driver when a suitable device is found
789 static int s3c24xx_i2c_probe(struct platform_device *pdev)
791 struct s3c24xx_i2c *i2c;
792 struct s3c2410_platform_i2c *pdata;
793 struct resource *res;
796 pdata = pdev->dev.platform_data;
798 dev_err(&pdev->dev, "no platform data\n");
802 i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
804 dev_err(&pdev->dev, "no memory for state\n");
808 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
809 i2c->adap.owner = THIS_MODULE;
810 i2c->adap.algo = &s3c24xx_i2c_algorithm;
811 i2c->adap.retries = 2;
812 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
815 spin_lock_init(&i2c->lock);
816 init_waitqueue_head(&i2c->wait);
818 /* find the clock and enable it */
820 i2c->dev = &pdev->dev;
821 i2c->clk = clk_get(&pdev->dev, "i2c");
822 if (IS_ERR(i2c->clk)) {
823 dev_err(&pdev->dev, "cannot get clock\n");
828 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
830 clk_enable(i2c->clk);
832 /* map the registers */
834 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
836 dev_err(&pdev->dev, "cannot find IO resource\n");
841 i2c->ioarea = request_mem_region(res->start, resource_size(res),
844 if (i2c->ioarea == NULL) {
845 dev_err(&pdev->dev, "cannot request IO\n");
850 i2c->regs = ioremap(res->start, resource_size(res));
852 if (i2c->regs == NULL) {
853 dev_err(&pdev->dev, "cannot map IO\n");
858 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
859 i2c->regs, i2c->ioarea, res);
861 /* setup info block for the i2c core */
863 i2c->adap.algo_data = i2c;
864 i2c->adap.dev.parent = &pdev->dev;
866 /* initialise the i2c controller */
868 ret = s3c24xx_i2c_init(i2c);
872 /* find the IRQ for this unit (note, this relies on the init call to
873 * ensure no current IRQs pending
876 i2c->irq = ret = platform_get_irq(pdev, 0);
878 dev_err(&pdev->dev, "cannot find IRQ\n");
882 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
883 dev_name(&pdev->dev), i2c);
886 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
890 ret = s3c24xx_i2c_register_cpufreq(i2c);
892 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
896 /* Note, previous versions of the driver used i2c_add_adapter()
897 * to add the bus at any number. We now pass the bus number via
898 * the platform data, so if unset it will now default to always
902 i2c->adap.nr = pdata->bus_num;
904 ret = i2c_add_numbered_adapter(&i2c->adap);
906 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
910 platform_set_drvdata(pdev, i2c);
912 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
916 s3c24xx_i2c_deregister_cpufreq(i2c);
919 free_irq(i2c->irq, i2c);
925 release_resource(i2c->ioarea);
929 clk_disable(i2c->clk);
937 /* s3c24xx_i2c_remove
939 * called when device is removed from the bus
942 static int s3c24xx_i2c_remove(struct platform_device *pdev)
944 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
946 s3c24xx_i2c_deregister_cpufreq(i2c);
948 i2c_del_adapter(&i2c->adap);
949 free_irq(i2c->irq, i2c);
951 clk_disable(i2c->clk);
956 release_resource(i2c->ioarea);
964 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
966 struct platform_device *pdev = to_platform_device(dev);
967 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
974 static int s3c24xx_i2c_resume(struct device *dev)
976 struct platform_device *pdev = to_platform_device(dev);
977 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
980 s3c24xx_i2c_init(i2c);
985 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
986 .suspend_noirq = s3c24xx_i2c_suspend_noirq,
987 .resume = s3c24xx_i2c_resume,
990 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
992 #define S3C24XX_DEV_PM_OPS NULL
995 /* device driver for platform bus bits */
997 static struct platform_device_id s3c24xx_driver_ids[] = {
999 .name = "s3c2410-i2c",
1000 .driver_data = TYPE_S3C2410,
1002 .name = "s3c2440-i2c",
1003 .driver_data = TYPE_S3C2440,
1006 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1008 static struct platform_driver s3c24xx_i2c_driver = {
1009 .probe = s3c24xx_i2c_probe,
1010 .remove = s3c24xx_i2c_remove,
1011 .id_table = s3c24xx_driver_ids,
1013 .owner = THIS_MODULE,
1015 .pm = S3C24XX_DEV_PM_OPS,
1019 static int __init i2c_adap_s3c_init(void)
1021 return platform_driver_register(&s3c24xx_i2c_driver);
1023 subsys_initcall(i2c_adap_s3c_init);
1025 static void __exit i2c_adap_s3c_exit(void)
1027 platform_driver_unregister(&s3c24xx_i2c_driver);
1029 module_exit(i2c_adap_s3c_exit);
1031 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1032 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1033 MODULE_LICENSE("GPL");