2 * SuperH Mobile I2C Controller
4 * Copyright (C) 2008 Magnus Damm
6 * Portions of the code based on out-of-tree driver i2c-sh7343.c
7 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/err.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/clk.h>
34 #include <linux/slab.h>
36 /* Transmit operation: */
46 /* BUS: S A8 ACK D8(1) ACK P */
47 /* IRQ: DTE WAIT WAIT */
53 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P */
54 /* IRQ: DTE WAIT WAIT WAIT */
57 /* ICDR: A8 D8(1) D8(2) */
59 /* 3 bytes or more, +---------+ gets repeated */
62 /* Receive operation: */
64 /* 0 byte receive - not supported since slave may hold SDA low */
66 /* 1 byte receive [TX] | [RX] */
67 /* BUS: S A8 ACK | D8(1) ACK P */
68 /* IRQ: DTE WAIT | WAIT DTE */
69 /* ICIC: -DTE | +DTE */
70 /* ICCR: 0x94 0x81 | 0xc0 */
71 /* ICDR: A8 | D8(1) */
73 /* 2 byte receive [TX]| [RX] */
74 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P */
75 /* IRQ: DTE WAIT | WAIT WAIT DTE */
76 /* ICIC: -DTE | +DTE */
77 /* ICCR: 0x94 0x81 | 0xc0 */
78 /* ICDR: A8 | D8(1) D8(2) */
80 /* 3 byte receive [TX] | [RX] */
81 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
82 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
83 /* ICIC: -DTE | +DTE */
84 /* ICCR: 0x94 0x81 | 0xc0 */
85 /* ICDR: A8 | D8(1) D8(2) D8(3) */
87 /* 4 bytes or more, this part is repeated +---------+ */
90 /* Interrupt order and BUSY flag */
92 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
93 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
95 /* S D7 D6 D5 D4 D3 D2 D1 D0 P */
97 /* WAIT IRQ ________________________________/ \___________ */
98 /* TACK IRQ ____________________________________/ \_______ */
99 /* DTE IRQ __________________________________________/ \_ */
100 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
101 /* _______________________________________________ */
105 enum sh_mobile_i2c_op {
116 struct sh_mobile_i2c_data {
119 struct i2c_adapter adap;
126 wait_queue_head_t wait;
132 #define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */
134 /* Register offsets */
135 #define ICDR(pd) (pd->reg + 0x00)
136 #define ICCR(pd) (pd->reg + 0x04)
137 #define ICSR(pd) (pd->reg + 0x08)
138 #define ICIC(pd) (pd->reg + 0x0c)
139 #define ICCL(pd) (pd->reg + 0x10)
140 #define ICCH(pd) (pd->reg + 0x14)
143 #define ICCR_ICE 0x80
144 #define ICCR_RACK 0x40
145 #define ICCR_TRS 0x10
146 #define ICCR_BBSY 0x04
147 #define ICCR_SCP 0x01
149 #define ICSR_SCLM 0x80
150 #define ICSR_SDAM 0x40
152 #define ICSR_BUSY 0x10
154 #define ICSR_TACK 0x04
155 #define ICSR_WAIT 0x02
156 #define ICSR_DTE 0x01
158 #define ICIC_ALE 0x08
159 #define ICIC_TACKE 0x04
160 #define ICIC_WAITE 0x02
161 #define ICIC_DTEE 0x01
163 static void activate_ch(struct sh_mobile_i2c_data *pd)
165 unsigned long i2c_clk;
170 /* Wake up device and enable clock */
171 pm_runtime_get_sync(pd->dev);
174 /* Get clock rate after clock is enabled */
175 i2c_clk = clk_get_rate(pd->clk);
177 /* Calculate the value for iccl. From the data sheet:
178 * iccl = (p clock / transfer rate) * (L / (L + H))
179 * where L and H are the SCL low/high ratio (5/4 in this case).
180 * We also round off the result.
183 denom = NORMAL_SPEED * 9;
184 tmp = num * 10 / denom;
186 pd->iccl = (u_int8_t)((num/denom) + 1);
188 pd->iccl = (u_int8_t)(num/denom);
190 /* Calculate the value for icch. From the data sheet:
191 icch = (p clock / transfer rate) * (H / (L + H)) */
193 tmp = num * 10 / denom;
195 pd->icch = (u_int8_t)((num/denom) + 1);
197 pd->icch = (u_int8_t)(num/denom);
199 /* Enable channel and configure rx ack */
200 iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
202 /* Mask all interrupts */
203 iowrite8(0, ICIC(pd));
206 iowrite8(pd->iccl, ICCL(pd));
207 iowrite8(pd->icch, ICCH(pd));
210 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
212 /* Clear/disable interrupts */
213 iowrite8(0, ICSR(pd));
214 iowrite8(0, ICIC(pd));
216 /* Disable channel */
217 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
219 /* Disable clock and mark device as idle */
220 clk_disable(pd->clk);
221 pm_runtime_put_sync(pd->dev);
224 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
225 enum sh_mobile_i2c_op op, unsigned char data)
227 unsigned char ret = 0;
230 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
232 spin_lock_irqsave(&pd->lock, flags);
235 case OP_START: /* issue start and trigger DTE interrupt */
236 iowrite8(0x94, ICCR(pd));
238 case OP_TX_FIRST: /* disable DTE interrupt and write data */
239 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd));
240 iowrite8(data, ICDR(pd));
242 case OP_TX: /* write data */
243 iowrite8(data, ICDR(pd));
245 case OP_TX_STOP: /* write data and issue a stop afterwards */
246 iowrite8(data, ICDR(pd));
247 iowrite8(0x90, ICCR(pd));
249 case OP_TX_TO_RX: /* select read mode */
250 iowrite8(0x81, ICCR(pd));
252 case OP_RX: /* just read data */
253 ret = ioread8(ICDR(pd));
255 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
256 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
258 iowrite8(0xc0, ICCR(pd));
260 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
261 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
263 ret = ioread8(ICDR(pd));
264 iowrite8(0xc0, ICCR(pd));
268 spin_unlock_irqrestore(&pd->lock, flags);
270 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
274 static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
282 static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
284 if (pd->pos == (pd->msg->len - 1))
290 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
295 *buf = (pd->msg->addr & 0x7f) << 1;
296 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
299 *buf = pd->msg->buf[pd->pos];
303 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
307 if (pd->pos == pd->msg->len)
310 sh_mobile_i2c_get_data(pd, &data);
312 if (sh_mobile_i2c_is_last_byte(pd))
313 i2c_op(pd, OP_TX_STOP, data);
314 else if (sh_mobile_i2c_is_first_byte(pd))
315 i2c_op(pd, OP_TX_FIRST, data);
317 i2c_op(pd, OP_TX, data);
323 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
330 sh_mobile_i2c_get_data(pd, &data);
332 if (sh_mobile_i2c_is_first_byte(pd))
333 i2c_op(pd, OP_TX_FIRST, data);
335 i2c_op(pd, OP_TX, data);
340 i2c_op(pd, OP_TX_TO_RX, 0);
344 real_pos = pd->pos - 2;
346 if (pd->pos == pd->msg->len) {
348 i2c_op(pd, OP_RX_STOP, 0);
351 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
353 data = i2c_op(pd, OP_RX, 0);
356 pd->msg->buf[real_pos] = data;
360 return pd->pos == (pd->msg->len + 2);
363 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
365 struct platform_device *dev = dev_id;
366 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
370 sr = ioread8(ICSR(pd));
371 pd->sr |= sr; /* remember state */
373 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
374 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
375 pd->pos, pd->msg->len);
377 if (sr & (ICSR_AL | ICSR_TACK)) {
378 /* don't interrupt transaction - continue to issue stop */
379 iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd));
381 } else if (pd->msg->flags & I2C_M_RD)
382 wakeup = sh_mobile_i2c_isr_rx(pd);
384 wakeup = sh_mobile_i2c_isr_tx(pd);
386 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
387 iowrite8(sr & ~ICSR_WAIT, ICSR(pd));
397 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
399 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
400 dev_err(pd->dev, "Unsupported zero length i2c read\n");
404 /* Initialize channel registers */
405 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
407 /* Enable channel and configure rx ack */
408 iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
411 iowrite8(pd->iccl, ICCL(pd));
412 iowrite8(pd->icch, ICCH(pd));
418 /* Enable all interrupts to begin with */
419 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd));
423 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
424 struct i2c_msg *msgs,
427 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
431 int i, k, retry_count;
435 /* Process all messages */
436 for (i = 0; i < num; i++) {
439 err = start_ch(pd, msg);
443 i2c_op(pd, OP_START, 0);
445 /* The interrupt handler takes care of the rest... */
446 k = wait_event_timeout(pd->wait,
447 pd->sr & (ICSR_TACK | SW_DONE),
450 dev_err(pd->dev, "Transfer request timed out\n");
454 val = ioread8(ICSR(pd));
456 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
458 /* the interrupt handler may wake us up before the
459 * transfer is finished, so poll the hardware
462 if (val & ICSR_BUSY) {
468 dev_err(pd->dev, "Polling timed out\n");
472 /* handle missing acknowledge and arbitration lost */
473 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
486 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
488 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
491 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
492 .functionality = sh_mobile_i2c_func,
493 .master_xfer = sh_mobile_i2c_xfer,
496 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
498 struct resource *res;
504 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
505 for (n = res->start; hook && n <= res->end; n++) {
506 if (request_irq(n, sh_mobile_i2c_isr, IRQF_DISABLED,
507 dev_name(&dev->dev), dev))
514 return k > 0 ? 0 : -ENOENT;
520 for (q = k; k >= 0; k--) {
521 for (m = n; m >= res->start; m--)
524 res = platform_get_resource(dev, IORESOURCE_IRQ, k - 1);
531 static int sh_mobile_i2c_probe(struct platform_device *dev)
533 struct sh_mobile_i2c_data *pd;
534 struct i2c_adapter *adap;
535 struct resource *res;
540 pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
542 dev_err(&dev->dev, "cannot allocate private data\n");
546 snprintf(clk_name, sizeof(clk_name), "i2c%d", dev->id);
547 pd->clk = clk_get(&dev->dev, clk_name);
548 if (IS_ERR(pd->clk)) {
549 dev_err(&dev->dev, "cannot get clock \"%s\"\n", clk_name);
550 ret = PTR_ERR(pd->clk);
554 ret = sh_mobile_i2c_hook_irqs(dev, 1);
556 dev_err(&dev->dev, "cannot request IRQ\n");
561 platform_set_drvdata(dev, pd);
563 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
565 dev_err(&dev->dev, "cannot find IO resource\n");
570 size = resource_size(res);
572 pd->reg = ioremap(res->start, size);
573 if (pd->reg == NULL) {
574 dev_err(&dev->dev, "cannot map IO\n");
579 /* Enable Runtime PM for this device.
581 * Also tell the Runtime PM core to ignore children
582 * for this device since it is valid for us to suspend
583 * this I2C master driver even though the slave devices
584 * on the I2C bus may not be suspended.
586 * The state of the I2C hardware bus is unaffected by
587 * the Runtime PM state.
589 pm_suspend_ignore_children(&dev->dev, true);
590 pm_runtime_enable(&dev->dev);
592 /* setup the private data */
594 i2c_set_adapdata(adap, pd);
596 adap->owner = THIS_MODULE;
597 adap->algo = &sh_mobile_i2c_algorithm;
598 adap->dev.parent = &dev->dev;
602 strlcpy(adap->name, dev->name, sizeof(adap->name));
604 spin_lock_init(&pd->lock);
605 init_waitqueue_head(&pd->wait);
607 ret = i2c_add_numbered_adapter(adap);
609 dev_err(&dev->dev, "cannot add numbered adapter\n");
618 sh_mobile_i2c_hook_irqs(dev, 0);
626 static int sh_mobile_i2c_remove(struct platform_device *dev)
628 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
630 i2c_del_adapter(&pd->adap);
632 sh_mobile_i2c_hook_irqs(dev, 0);
634 pm_runtime_disable(&dev->dev);
639 static int sh_mobile_i2c_runtime_nop(struct device *dev)
641 /* Runtime PM callback shared between ->runtime_suspend()
642 * and ->runtime_resume(). Simply returns success.
644 * This driver re-initializes all registers after
645 * pm_runtime_get_sync() anyway so there is no need
646 * to save and restore registers here.
651 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
652 .runtime_suspend = sh_mobile_i2c_runtime_nop,
653 .runtime_resume = sh_mobile_i2c_runtime_nop,
656 static struct platform_driver sh_mobile_i2c_driver = {
658 .name = "i2c-sh_mobile",
659 .owner = THIS_MODULE,
660 .pm = &sh_mobile_i2c_dev_pm_ops,
662 .probe = sh_mobile_i2c_probe,
663 .remove = sh_mobile_i2c_remove,
666 static int __init sh_mobile_i2c_adap_init(void)
668 return platform_driver_register(&sh_mobile_i2c_driver);
671 static void __exit sh_mobile_i2c_adap_exit(void)
673 platform_driver_unregister(&sh_mobile_i2c_driver);
676 subsys_initcall(sh_mobile_i2c_adap_init);
677 module_exit(sh_mobile_i2c_adap_exit);
679 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
680 MODULE_AUTHOR("Magnus Damm");
681 MODULE_LICENSE("GPL v2");