2 Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
4 National Semiconductor SCx200 ACCESS.bus support
5 Also supports the AMD CS5535 and AMD CS5536
7 Based on i2c-keywest.c which is:
8 Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
9 Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
11 This program is free software; you can redistribute it and/or
12 modify it under the terms of the GNU General Public License as
13 published by the Free Software Foundation; either version 2 of the
14 License, or (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/i2c.h>
31 #include <linux/smp_lock.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
37 #include <linux/scx200.h>
39 #define NAME "scx200_acb"
41 MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
42 MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver");
43 MODULE_LICENSE("GPL");
46 static int base[MAX_DEVICES] = { 0x820, 0x840 };
47 module_param_array(base, int, NULL, 0);
48 MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
50 #define POLL_TIMEOUT (HZ/5)
52 enum scx200_acb_state {
62 static const char *scx200_acb_state_name[] = {
72 /* Physical interface */
73 struct scx200_acb_iface {
74 struct scx200_acb_iface *next;
75 struct i2c_adapter adapter;
79 /* State machine data */
80 enum scx200_acb_state state;
89 /* Register Definitions */
90 #define ACBSDA (iface->base + 0)
91 #define ACBST (iface->base + 1)
92 #define ACBST_SDAST 0x40 /* SDA Status */
93 #define ACBST_BER 0x20
94 #define ACBST_NEGACK 0x10 /* Negative Acknowledge */
95 #define ACBST_STASTR 0x08 /* Stall After Start */
96 #define ACBST_MASTER 0x02
97 #define ACBCST (iface->base + 2)
98 #define ACBCST_BB 0x02
99 #define ACBCTL1 (iface->base + 3)
100 #define ACBCTL1_STASTRE 0x80
101 #define ACBCTL1_NMINTE 0x40
102 #define ACBCTL1_ACK 0x10
103 #define ACBCTL1_STOP 0x02
104 #define ACBCTL1_START 0x01
105 #define ACBADDR (iface->base + 4)
106 #define ACBCTL2 (iface->base + 5)
107 #define ACBCTL2_ENABLE 0x01
109 /************************************************************************/
111 static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status)
115 dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n",
116 scx200_acb_state_name[iface->state], status);
118 if (status & ACBST_BER) {
119 errmsg = "bus error";
122 if (!(status & ACBST_MASTER)) {
123 errmsg = "not master";
126 if (status & ACBST_NEGACK) {
127 dev_dbg(&iface->adapter.dev, "negative ack in state %s\n",
128 scx200_acb_state_name[iface->state]);
130 iface->state = state_idle;
131 iface->result = -ENXIO;
133 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
134 outb(ACBST_STASTR | ACBST_NEGACK, ACBST);
138 switch (iface->state) {
140 dev_warn(&iface->adapter.dev, "interrupt in idle state\n");
144 /* Do a pointer write first */
145 outb(iface->address_byte & ~1, ACBSDA);
147 iface->state = state_command;
151 outb(iface->command, ACBSDA);
153 if (iface->address_byte & 1)
154 iface->state = state_repeat_start;
156 iface->state = state_write;
159 case state_repeat_start:
160 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
164 if (iface->address_byte & 1) {
166 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
168 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
169 outb(iface->address_byte, ACBSDA);
171 iface->state = state_read;
173 outb(iface->address_byte, ACBSDA);
175 iface->state = state_write;
180 /* Set ACK if receiving the last byte */
182 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
184 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
186 *iface->ptr++ = inb(ACBSDA);
189 if (iface->len == 0) {
191 iface->state = state_idle;
192 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
198 if (iface->len == 0) {
200 iface->state = state_idle;
201 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
205 outb(*iface->ptr++, ACBSDA);
214 dev_err(&iface->adapter.dev, "%s in state %s\n", errmsg,
215 scx200_acb_state_name[iface->state]);
217 iface->state = state_idle;
218 iface->result = -EIO;
219 iface->needs_reset = 1;
222 static void scx200_acb_poll(struct scx200_acb_iface *iface)
225 unsigned long timeout;
227 timeout = jiffies + POLL_TIMEOUT;
228 while (time_before(jiffies, timeout)) {
230 if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) {
231 scx200_acb_machine(iface, status);
237 dev_err(&iface->adapter.dev, "timeout in state %s\n",
238 scx200_acb_state_name[iface->state]);
240 iface->state = state_idle;
241 iface->result = -EIO;
242 iface->needs_reset = 1;
245 static void scx200_acb_reset(struct scx200_acb_iface *iface)
247 /* Disable the ACCESS.bus device and Configure the SCL
248 frequency: 16 clock cycles */
252 /* Disable slave address */
254 /* Enable the ACCESS.bus device */
255 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
256 /* Free STALL after START */
257 outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1);
259 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
260 /* Clear BER, NEGACK and STASTR bits */
261 outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST);
263 outb(inb(ACBCST) | ACBCST_BB, ACBCST);
266 static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
267 u16 address, unsigned short flags,
268 char rw, u8 command, int size,
269 union i2c_smbus_data *data)
271 struct scx200_acb_iface *iface = i2c_get_adapdata(adapter);
278 case I2C_SMBUS_QUICK:
285 buffer = rw ? &data->byte : &command;
288 case I2C_SMBUS_BYTE_DATA:
290 buffer = &data->byte;
293 case I2C_SMBUS_WORD_DATA:
295 cur_word = cpu_to_le16(data->word);
296 buffer = (u8 *)&cur_word;
299 case I2C_SMBUS_BLOCK_DATA:
300 len = data->block[0];
301 buffer = &data->block[1];
308 dev_dbg(&adapter->dev,
309 "size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n",
310 size, address, command, len, rw);
312 if (!len && rw == I2C_SMBUS_READ) {
313 dev_dbg(&adapter->dev, "zero length read\n");
319 iface->address_byte = (address << 1) | rw;
320 iface->command = command;
323 iface->result = -EINVAL;
324 iface->needs_reset = 0;
326 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
328 if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE)
329 iface->state = state_quick;
331 iface->state = state_address;
333 while (iface->state != state_idle)
334 scx200_acb_poll(iface);
336 if (iface->needs_reset)
337 scx200_acb_reset(iface);
343 if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ)
344 data->word = le16_to_cpu(cur_word);
347 dev_dbg(&adapter->dev, "transfer done, result: %d", rc);
351 for (i = 0; i < len; ++i)
352 printk(" %02x", buffer[i]);
360 static u32 scx200_acb_func(struct i2c_adapter *adapter)
362 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
363 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
364 I2C_FUNC_SMBUS_BLOCK_DATA;
367 /* For now, we only handle combined mode (smbus) */
368 static struct i2c_algorithm scx200_acb_algorithm = {
369 .smbus_xfer = scx200_acb_smbus_xfer,
370 .functionality = scx200_acb_func,
373 static struct scx200_acb_iface *scx200_acb_list;
374 static DECLARE_MUTEX(scx200_acb_list_mutex);
376 static int scx200_acb_probe(struct scx200_acb_iface *iface)
380 /* Disable the ACCESS.bus device and Configure the SCL
381 frequency: 16 clock cycles */
384 if (inb(ACBCTL2) != 0x70) {
385 pr_debug(NAME ": ACBCTL2 readback failed\n");
389 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
393 pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n",
398 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
400 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
403 if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) {
404 pr_debug(NAME ": enabled, but NMINTE won't be set, "
405 "ACBCTL1=0x%02x\n", val);
412 static int __init scx200_acb_create(const char *text, int base, int index)
414 struct scx200_acb_iface *iface;
415 struct i2c_adapter *adapter;
417 char description[64];
419 iface = kzalloc(sizeof(*iface), GFP_KERNEL);
421 printk(KERN_ERR NAME ": can't allocate memory\n");
426 adapter = &iface->adapter;
427 i2c_set_adapdata(adapter, iface);
428 snprintf(adapter->name, I2C_NAME_SIZE, "%s ACB%d", text, index);
429 adapter->owner = THIS_MODULE;
430 adapter->id = I2C_HW_SMBUS_SCX200;
431 adapter->algo = &scx200_acb_algorithm;
432 adapter->class = I2C_CLASS_HWMON;
434 init_MUTEX(&iface->sem);
436 snprintf(description, sizeof(description), "%s ACCESS.bus [%s]",
437 text, adapter->name);
439 if (request_region(base, 8, description) == 0) {
440 printk(KERN_ERR NAME ": can't allocate io 0x%x-0x%x\n",
447 rc = scx200_acb_probe(iface);
449 printk(KERN_WARNING NAME ": probe failed\n");
453 scx200_acb_reset(iface);
455 if (i2c_add_adapter(adapter) < 0) {
456 printk(KERN_ERR NAME ": failed to register\n");
461 down(&scx200_acb_list_mutex);
462 iface->next = scx200_acb_list;
463 scx200_acb_list = iface;
464 up(&scx200_acb_list_mutex);
469 release_region(iface->base, 8);
476 static struct pci_device_id scx200[] = {
477 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE) },
478 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE) },
482 static struct pci_device_id divil_pci[] = {
483 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
484 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
488 #define MSR_LBAR_SMB 0x5140000B
490 static int scx200_add_cs553x(void)
495 /* Grab & reserve the SMB I/O range */
496 rdmsr(MSR_LBAR_SMB, low, hi);
498 /* Check the IO mask and whether SMB is enabled */
499 if (hi != 0x0000F001) {
500 printk(KERN_WARNING NAME ": SMBus not enabled\n");
504 /* SMBus IO size is 8 bytes */
505 smb_base = low & 0x0000FFF8;
507 return scx200_acb_create("CS5535", smb_base, 0);
510 static int __init scx200_acb_init(void)
515 pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n");
517 /* Verify that this really is a SCx200 processor */
518 if (pci_dev_present(scx200)) {
519 for (i = 0; i < MAX_DEVICES; ++i) {
521 rc = scx200_acb_create("SCx200", base[i], i);
523 } else if (pci_dev_present(divil_pci))
524 rc = scx200_add_cs553x();
529 static void __exit scx200_acb_cleanup(void)
531 struct scx200_acb_iface *iface;
533 down(&scx200_acb_list_mutex);
534 while ((iface = scx200_acb_list) != NULL) {
535 scx200_acb_list = iface->next;
536 up(&scx200_acb_list_mutex);
538 i2c_del_adapter(&iface->adapter);
539 release_region(iface->base, 8);
541 down(&scx200_acb_list_mutex);
543 up(&scx200_acb_list_mutex);
546 module_init(scx200_acb_init);
547 module_exit(scx200_acb_cleanup);