drivers/i2c/mxs_i2c.c

   1 /*
   2  * Freescale i.MX28 I2C Driver
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * Partly based on Linux kernel i2c-mxs.c driver:
   8  * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
   9  *
  10  * Which was based on a (non-working) driver which was:
  11  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <malloc.h>
  18 #include <i2c.h>
  19 #include <asm/errno.h>
  20 #include <asm/io.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include <asm/arch/sys_proto.h>
  24
  25 #define MXS_I2C_MAX_TIMEOUT     1000000
  26
  27 static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap)
  28 {
  29         return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
  30 }
  31
  32 static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap)
  33 {
  34         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
  35         uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
  36         uint32_t timing0;
  37
  38         timing0 = readl(&i2c_regs->hw_i2c_timing0);
  39         /*
  40          * This is a reverse version of the algorithm presented in
  41          * i2c_set_bus_speed(). Please refer there for details.
  42          */
  43         return clk / ((((timing0 >> 16) - 3) * 2) + 38);
  44 }
  45
  46 static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  47 {
  48         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
  49         /*
  50          * The timing derivation algorithm. There is no documentation for this
  51          * algorithm available, it was derived by using the scope and fiddling
  52          * with constants until the result observed on the scope was good enough
  53          * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
  54          * possible to assume the algorithm works for other frequencies as well.
  55          *
  56          * Note it was necessary to cap the frequency on both ends as it's not
  57          * possible to configure completely arbitrary frequency for the I2C bus
  58          * clock.
  59          */
  60         uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
  61         uint32_t base = ((clk / speed) - 38) / 2;
  62         uint16_t high_count = base + 3;
  63         uint16_t low_count = base - 3;
  64         uint16_t rcv_count = (high_count * 3) / 4;
  65         uint16_t xmit_count = low_count / 4;
  66
  67         if (speed > 540000) {
  68                 printf("MXS I2C: Speed too high (%d Hz)\n", speed);
  69                 return -EINVAL;
  70         }
  71
  72         if (speed < 12000) {
  73                 printf("MXS I2C: Speed too low (%d Hz)\n", speed);
  74                 return -EINVAL;
  75         }
  76
  77         writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
  78         writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
  79
  80         writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
  81                 (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
  82                 &i2c_regs->hw_i2c_timing2);
  83
  84         return 0;
  85 }
  86
  87 static void mxs_i2c_reset(struct i2c_adapter *adap)
  88 {
  89         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
  90         int ret;
  91         int speed = mxs_i2c_get_bus_speed(adap);
  92
  93         ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
  94         if (ret) {
  95                 debug("MXS I2C: Block reset timeout\n");
  96                 return;
  97         }
  98
  99         writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
 100                 I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
 101                 I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
 102                 &i2c_regs->hw_i2c_ctrl1_clr);
 103
 104         writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
 105
 106         mxs_i2c_set_bus_speed(adap, speed);
 107 }
 108
 109 static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len)
 110 {
 111         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 112
 113         writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
 114                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
 115                 (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
 116                 &i2c_regs->hw_i2c_queuecmd);
 117
 118         writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
 119
 120         writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
 121                 (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
 122                 I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
 123
 124         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 125 }
 126
 127 static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 128                          int alen, uchar *buf, int blen, int stop)
 129 {
 130         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 131         uint32_t data, tmp;
 132         int i, remain, off;
 133         int timeout = MXS_I2C_MAX_TIMEOUT;
 134
 135         if ((alen > 4) || (alen == 0)) {
 136                 debug("MXS I2C: Invalid address length\n");
 137                 return -EINVAL;
 138         }
 139
 140         if (stop)
 141                 stop = I2C_QUEUECMD_POST_SEND_STOP;
 142
 143         writel(I2C_QUEUECMD_PRE_SEND_START |
 144                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
 145                 ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
 146                 &i2c_regs->hw_i2c_queuecmd);
 147
 148         data = (chip << 1) << 24;
 149
 150         for (i = 0; i < alen; i++) {
 151                 data >>= 8;
 152                 data |= ((char *)&addr)[alen - i - 1] << 24;
 153                 if ((i & 3) == 2)
 154                         writel(data, &i2c_regs->hw_i2c_data);
 155         }
 156
 157         off = i;
 158         for (; i < off + blen; i++) {
 159                 data >>= 8;
 160                 data |= buf[i - off] << 24;
 161                 if ((i & 3) == 2)
 162                         writel(data, &i2c_regs->hw_i2c_data);
 163         }
 164
 165         remain = 24 - ((i & 3) * 8);
 166         if (remain)
 167                 writel(data >> remain, &i2c_regs->hw_i2c_data);
 168
 169         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 170
 171         while (--timeout) {
 172                 tmp = readl(&i2c_regs->hw_i2c_queuestat);
 173                 if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
 174                         break;
 175         }
 176
 177         if (!timeout) {
 178                 debug("MXS I2C: Failed transmitting data!\n");
 179                 return -EINVAL;
 180         }
 181
 182         return 0;
 183 }
 184
 185 static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap)
 186 {
 187         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 188         uint32_t tmp;
 189         int timeout = MXS_I2C_MAX_TIMEOUT;
 190
 191         for (;;) {
 192                 tmp = readl(&i2c_regs->hw_i2c_ctrl1);
 193                 if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
 194                         debug("MXS I2C: No slave ACK\n");
 195                         goto err;
 196                 }
 197
 198                 if (tmp & (
 199                         I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
 200                         I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
 201                         debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
 202                         goto err;
 203                 }
 204
 205                 if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
 206                         break;
 207
 208                 if (!timeout--) {
 209                         debug("MXS I2C: Operation timed out\n");
 210                         goto err;
 211                 }
 212
 213                 udelay(1);
 214         }
 215
 216         return 0;
 217
 218 err:
 219         mxs_i2c_reset(adap);
 220         return 1;
 221 }
 222
 223 static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
 224                            uint addr, int alen, uint8_t *buffer,
 225                            int len)
 226 {
 227         struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
 228         uint32_t tmp = 0;
 229         int timeout = MXS_I2C_MAX_TIMEOUT;
 230         int ret;
 231         int i;
 232
 233         ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0);
 234         if (ret) {
 235                 debug("MXS I2C: Failed writing address\n");
 236                 return ret;
 237         }
 238
 239         ret = mxs_i2c_wait_for_ack(adap);
 240         if (ret) {
 241                 debug("MXS I2C: Failed writing address\n");
 242                 return ret;
 243         }
 244
 245         mxs_i2c_setup_read(adap, chip, len);
 246         ret = mxs_i2c_wait_for_ack(adap);
 247         if (ret) {
 248                 debug("MXS I2C: Failed reading address\n");
 249                 return ret;
 250         }
 251
 252         for (i = 0; i < len; i++) {
 253                 if (!(i & 3)) {
 254                         while (--timeout) {
 255                                 tmp = readl(&i2c_regs->hw_i2c_queuestat);
 256                                 if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
 257                                         break;
 258                         }
 259
 260                         if (!timeout) {
 261                                 debug("MXS I2C: Failed receiving data!\n");
 262                                 return -ETIMEDOUT;
 263                         }
 264
 265                         tmp = readl(&i2c_regs->hw_i2c_queuedata);
 266                 }
 267                 buffer[i] = tmp & 0xff;
 268                 tmp >>= 8;
 269         }
 270
 271         return 0;
 272 }
 273
 274 static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
 275                             uint addr, int alen, uint8_t *buffer,
 276                             int len)
 277 {
 278         int ret;
 279         ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1);
 280         if (ret) {
 281                 debug("MXS I2C: Failed writing address\n");
 282                 return ret;
 283         }
 284
 285         ret = mxs_i2c_wait_for_ack(adap);
 286         if (ret)
 287                 debug("MXS I2C: Failed writing address\n");
 288
 289         return ret;
 290 }
 291
 292 static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 293 {
 294         int ret;
 295         ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1);
 296         if (!ret)
 297                 ret = mxs_i2c_wait_for_ack(adap);
 298         mxs_i2c_reset(adap);
 299         return ret;
 300 }
 301
 302 static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 303 {
 304         mxs_i2c_reset(adap);
 305         mxs_i2c_set_bus_speed(adap, speed);
 306
 307         return;
 308 }
 309
 310 U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
 311                          mxs_i2c_if_read, mxs_i2c_if_write,
 312                          mxs_i2c_set_bus_speed,
 313                          CONFIG_SYS_I2C_SPEED, 0, 0)