2 * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
32 #undef REALLY_SLOW_IO /* most systems can safely undef this */
34 #include <linux/types.h>
35 #include <linux/module.h>
36 #include <linux/kernel.h>
37 #include <linux/delay.h>
38 #include <linux/platform_device.h>
40 #include <linux/init.h>
41 #include <linux/ide.h>
42 #include <linux/sysdev.h>
44 #include <linux/dma-mapping.h>
46 #include "ide-timing.h"
49 #include <asm/mach-au1x00/au1xxx.h>
50 #include <asm/mach-au1x00/au1xxx_dbdma.h>
52 #include <asm/mach-au1x00/au1xxx_ide.h>
54 #define DRV_NAME "au1200-ide"
55 #define DRV_VERSION "1.0"
56 #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
58 /* enable the burstmode in the dbdma */
59 #define IDE_AU1XXX_BURSTMODE 1
61 static _auide_hwif auide_hwif;
62 static int dbdma_init_done;
64 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
66 void auide_insw(unsigned long port, void *addr, u32 count)
68 _auide_hwif *ahwif = &auide_hwif;
72 if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
74 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
77 ctp = *((chan_tab_t **)ahwif->rx_chan);
79 while (dp->dscr_cmd0 & DSCR_CMD0_V)
81 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
84 void auide_outsw(unsigned long port, void *addr, u32 count)
86 _auide_hwif *ahwif = &auide_hwif;
90 if(!put_source_flags(ahwif->tx_chan, (void*)addr,
91 count << 1, DDMA_FLAGS_NOIE)) {
92 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
95 ctp = *((chan_tab_t **)ahwif->tx_chan);
97 while (dp->dscr_cmd0 & DSCR_CMD0_V)
99 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
104 static void auide_tune_drive(ide_drive_t *drive, byte pio)
110 /* get the best pio mode for the drive */
111 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
113 printk(KERN_INFO "%s: setting Au1XXX IDE to PIO mode%d\n",
117 mem_stcfg = au_readl(MEM_STCFG2);
122 mem_sttime = SBC_IDE_TIMING(PIO0);
124 /* set configuration for RCS2# */
125 mem_stcfg |= TS_MASK;
126 mem_stcfg &= ~TCSOE_MASK;
127 mem_stcfg &= ~TOECS_MASK;
128 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
132 mem_sttime = SBC_IDE_TIMING(PIO1);
134 /* set configuration for RCS2# */
135 mem_stcfg |= TS_MASK;
136 mem_stcfg &= ~TCSOE_MASK;
137 mem_stcfg &= ~TOECS_MASK;
138 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
142 mem_sttime = SBC_IDE_TIMING(PIO2);
144 /* set configuration for RCS2# */
145 mem_stcfg &= ~TS_MASK;
146 mem_stcfg &= ~TCSOE_MASK;
147 mem_stcfg &= ~TOECS_MASK;
148 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
152 mem_sttime = SBC_IDE_TIMING(PIO3);
154 /* set configuration for RCS2# */
155 mem_stcfg &= ~TS_MASK;
156 mem_stcfg &= ~TCSOE_MASK;
157 mem_stcfg &= ~TOECS_MASK;
158 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
163 mem_sttime = SBC_IDE_TIMING(PIO4);
165 /* set configuration for RCS2# */
166 mem_stcfg &= ~TS_MASK;
167 mem_stcfg &= ~TCSOE_MASK;
168 mem_stcfg &= ~TOECS_MASK;
169 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
173 au_writel(mem_sttime,MEM_STTIME2);
174 au_writel(mem_stcfg,MEM_STCFG2);
176 speed = pio + XFER_PIO_0;
177 ide_config_drive_speed(drive, speed);
180 static int auide_tune_chipset (ide_drive_t *drive, u8 speed)
186 mem_stcfg = au_readl(MEM_STCFG2);
188 if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
189 auide_tune_drive(drive, speed - XFER_PIO_0);
194 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
196 mem_sttime = SBC_IDE_TIMING(MDMA2);
198 /* set configuration for RCS2# */
199 mem_stcfg &= ~TS_MASK;
200 mem_stcfg &= ~TCSOE_MASK;
201 mem_stcfg &= ~TOECS_MASK;
202 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
206 mem_sttime = SBC_IDE_TIMING(MDMA1);
208 /* set configuration for RCS2# */
209 mem_stcfg &= ~TS_MASK;
210 mem_stcfg &= ~TCSOE_MASK;
211 mem_stcfg &= ~TOECS_MASK;
212 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
216 mem_sttime = SBC_IDE_TIMING(MDMA0);
218 /* set configuration for RCS2# */
219 mem_stcfg |= TS_MASK;
220 mem_stcfg &= ~TCSOE_MASK;
221 mem_stcfg &= ~TOECS_MASK;
222 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
230 if (ide_config_drive_speed(drive, speed))
233 au_writel(mem_sttime,MEM_STTIME2);
234 au_writel(mem_stcfg,MEM_STCFG2);
240 * Multi-Word DMA + DbDMA functions
243 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
245 static int auide_build_sglist(ide_drive_t *drive, struct request *rq)
247 ide_hwif_t *hwif = drive->hwif;
248 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
249 struct scatterlist *sg = hwif->sg_table;
251 ide_map_sg(drive, rq);
253 if (rq_data_dir(rq) == READ)
254 hwif->sg_dma_direction = DMA_FROM_DEVICE;
256 hwif->sg_dma_direction = DMA_TO_DEVICE;
258 return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
259 hwif->sg_dma_direction);
262 static int auide_build_dmatable(ide_drive_t *drive)
264 int i, iswrite, count = 0;
265 ide_hwif_t *hwif = HWIF(drive);
267 struct request *rq = HWGROUP(drive)->rq;
269 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
270 struct scatterlist *sg;
272 iswrite = (rq_data_dir(rq) == WRITE);
273 /* Save for interrupt context */
274 ahwif->drive = drive;
277 hwif->sg_nents = i = auide_build_sglist(drive, rq);
282 /* fill the descriptors */
284 while (i && sg_dma_len(sg)) {
288 cur_addr = sg_dma_address(sg);
289 cur_len = sg_dma_len(sg);
292 u32 flags = DDMA_FLAGS_NOIE;
293 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
295 if (++count >= PRD_ENTRIES) {
296 printk(KERN_WARNING "%s: DMA table too small\n",
298 goto use_pio_instead;
301 /* Lets enable intr for the last descriptor only */
303 flags = DDMA_FLAGS_IE;
305 flags = DDMA_FLAGS_NOIE;
308 if(!put_source_flags(ahwif->tx_chan,
309 (void*)(page_address(sg->page)
312 printk(KERN_ERR "%s failed %d\n",
313 __FUNCTION__, __LINE__);
317 if(!put_dest_flags(ahwif->rx_chan,
318 (void*)(page_address(sg->page)
321 printk(KERN_ERR "%s failed %d\n",
322 __FUNCTION__, __LINE__);
337 dma_unmap_sg(ahwif->dev,
340 hwif->sg_dma_direction);
342 return 0; /* revert to PIO for this request */
345 static int auide_dma_end(ide_drive_t *drive)
347 ide_hwif_t *hwif = HWIF(drive);
348 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
350 if (hwif->sg_nents) {
351 dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
352 hwif->sg_dma_direction);
359 static void auide_dma_start(ide_drive_t *drive )
364 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
366 /* issue cmd to drive */
367 ide_execute_command(drive, command, &ide_dma_intr,
371 static int auide_dma_setup(ide_drive_t *drive)
373 struct request *rq = HWGROUP(drive)->rq;
375 if (!auide_build_dmatable(drive)) {
376 ide_map_sg(drive, rq);
380 drive->waiting_for_dma = 1;
384 static int auide_dma_check(ide_drive_t *drive)
388 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
390 if( dbdma_init_done == 0 ){
391 auide_hwif.white_list = ide_in_drive_list(drive->id,
393 auide_hwif.black_list = ide_in_drive_list(drive->id,
395 auide_hwif.drive = drive;
396 auide_ddma_init(&auide_hwif);
401 /* Is the drive in our DMA black list? */
403 if ( auide_hwif.black_list ) {
404 drive->using_dma = 0;
406 /* Borrowed the warning message from ide-dma.c */
408 printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
409 drive->name, drive->id->model);
412 drive->using_dma = 1;
414 speed = ide_find_best_mode(drive, XFER_PIO | XFER_MWDMA);
416 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
417 return HWIF(drive)->ide_dma_on(drive);
419 return HWIF(drive)->ide_dma_off_quietly(drive);
422 static int auide_dma_test_irq(ide_drive_t *drive)
424 if (drive->waiting_for_dma == 0)
425 printk(KERN_WARNING "%s: ide_dma_test_irq \
426 called while not waiting\n", drive->name);
428 /* If dbdma didn't execute the STOP command yet, the
429 * active bit is still set
431 drive->waiting_for_dma++;
432 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
433 printk(KERN_WARNING "%s: timeout waiting for ddma to \
434 complete\n", drive->name);
441 static int auide_dma_host_on(ide_drive_t *drive)
446 static int auide_dma_on(ide_drive_t *drive)
448 drive->using_dma = 1;
449 return auide_dma_host_on(drive);
453 static int auide_dma_host_off(ide_drive_t *drive)
458 static int auide_dma_off_quietly(ide_drive_t *drive)
460 drive->using_dma = 0;
461 return auide_dma_host_off(drive);
464 static int auide_dma_lostirq(ide_drive_t *drive)
466 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
470 static void auide_ddma_tx_callback(int irq, void *param)
472 _auide_hwif *ahwif = (_auide_hwif*)param;
473 ahwif->drive->waiting_for_dma = 0;
476 static void auide_ddma_rx_callback(int irq, void *param)
478 _auide_hwif *ahwif = (_auide_hwif*)param;
479 ahwif->drive->waiting_for_dma = 0;
482 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
484 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
486 dev->dev_id = dev_id;
487 dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
488 dev->dev_intlevel = 0;
489 dev->dev_intpolarity = 0;
490 dev->dev_tsize = tsize;
491 dev->dev_devwidth = devwidth;
492 dev->dev_flags = flags;
495 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
497 static int auide_dma_timeout(ide_drive_t *drive)
499 // printk("%s\n", __FUNCTION__);
501 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
503 if (HWIF(drive)->ide_dma_test_irq(drive))
506 return HWIF(drive)->ide_dma_end(drive);
510 static int auide_ddma_init(_auide_hwif *auide) {
512 dbdev_tab_t source_dev_tab, target_dev_tab;
513 u32 dev_id, tsize, devwidth, flags;
514 ide_hwif_t *hwif = auide->hwif;
516 dev_id = AU1XXX_ATA_DDMA_REQ;
518 if (auide->white_list || auide->black_list) {
526 printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
527 printk(KERN_ERR " please read 'Documentation/mips/AU1xxx_IDE.README'");
530 #ifdef IDE_AU1XXX_BURSTMODE
531 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
533 flags = DEV_FLAGS_SYNC;
536 /* setup dev_tab for tx channel */
537 auide_init_dbdma_dev( &source_dev_tab,
539 tsize, devwidth, DEV_FLAGS_OUT | flags);
540 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
542 auide_init_dbdma_dev( &source_dev_tab,
544 tsize, devwidth, DEV_FLAGS_IN | flags);
545 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
547 /* We also need to add a target device for the DMA */
548 auide_init_dbdma_dev( &target_dev_tab,
549 (u32)DSCR_CMD0_ALWAYS,
550 tsize, devwidth, DEV_FLAGS_ANYUSE);
551 auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
553 /* Get a channel for TX */
554 auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
556 auide_ddma_tx_callback,
559 /* Get a channel for RX */
560 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
561 auide->target_dev_id,
562 auide_ddma_rx_callback,
565 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
567 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
570 hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
571 PRD_ENTRIES * PRD_BYTES, /* 1 Page */
572 &hwif->dmatable_dma, GFP_KERNEL);
574 au1xxx_dbdma_start( auide->tx_chan );
575 au1xxx_dbdma_start( auide->rx_chan );
581 static int auide_ddma_init( _auide_hwif *auide )
583 dbdev_tab_t source_dev_tab;
586 #ifdef IDE_AU1XXX_BURSTMODE
587 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
589 flags = DEV_FLAGS_SYNC;
592 /* setup dev_tab for tx channel */
593 auide_init_dbdma_dev( &source_dev_tab,
594 (u32)DSCR_CMD0_ALWAYS,
595 8, 32, DEV_FLAGS_OUT | flags);
596 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
598 auide_init_dbdma_dev( &source_dev_tab,
599 (u32)DSCR_CMD0_ALWAYS,
600 8, 32, DEV_FLAGS_IN | flags);
601 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
603 /* Get a channel for TX */
604 auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
609 /* Get a channel for RX */
610 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
615 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
617 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
620 au1xxx_dbdma_start( auide->tx_chan );
621 au1xxx_dbdma_start( auide->rx_chan );
627 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
630 unsigned long *ata_regs = hw->io_ports;
633 for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
634 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
637 /* set the Alternative Status register */
638 *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
641 static int au_ide_probe(struct device *dev)
643 struct platform_device *pdev = to_platform_device(dev);
644 _auide_hwif *ahwif = &auide_hwif;
646 struct resource *res;
649 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
650 char *mode = "MWDMA2";
651 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
652 char *mode = "PIO+DDMA(offload)";
655 memset(&auide_hwif, 0, sizeof(_auide_hwif));
659 ahwif->irq = platform_get_irq(pdev, 0);
661 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
664 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
668 if (ahwif->irq < 0) {
669 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
674 if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
675 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
680 ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
681 if (ahwif->regbase == 0) {
686 /* FIXME: This might possibly break PCMCIA IDE devices */
688 hwif = &ide_hwifs[pdev->id];
689 hw_regs_t *hw = &hwif->hw;
690 hwif->irq = hw->irq = ahwif->irq;
691 hwif->chipset = ide_au1xxx;
693 auide_setup_ports(hw, ahwif);
694 memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
696 hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
697 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
698 hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */
699 hwif->swdma_mask = 0x00;
701 hwif->mwdma_mask = 0x0;
702 hwif->swdma_mask = 0x0;
706 hwif->drives[0].unmask = 1;
707 hwif->drives[1].unmask = 1;
709 /* hold should be on in all cases */
714 /* If the user has selected DDMA assisted copies,
715 then set up a few local I/O function entry points
718 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
719 hwif->INSW = auide_insw;
720 hwif->OUTSW = auide_outsw;
723 hwif->tuneproc = &auide_tune_drive;
724 hwif->speedproc = &auide_tune_chipset;
726 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
727 hwif->ide_dma_off_quietly = &auide_dma_off_quietly;
728 hwif->ide_dma_timeout = &auide_dma_timeout;
730 hwif->ide_dma_check = &auide_dma_check;
731 hwif->dma_exec_cmd = &auide_dma_exec_cmd;
732 hwif->dma_start = &auide_dma_start;
733 hwif->ide_dma_end = &auide_dma_end;
734 hwif->dma_setup = &auide_dma_setup;
735 hwif->ide_dma_test_irq = &auide_dma_test_irq;
736 hwif->ide_dma_host_off = &auide_dma_host_off;
737 hwif->ide_dma_host_on = &auide_dma_host_on;
738 hwif->ide_dma_lostirq = &auide_dma_lostirq;
739 hwif->ide_dma_on = &auide_dma_on;
742 hwif->drives[0].autodma = hwif->autodma;
743 hwif->drives[1].autodma = hwif->autodma;
746 #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
750 hwif->select_data = 0; /* no chipset-specific code */
751 hwif->config_data = 0; /* no chipset-specific code */
753 hwif->drives[0].autodma = 0;
754 hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */
756 hwif->drives[0].no_io_32bit = 1;
758 auide_hwif.hwif = hwif;
759 hwif->hwif_data = &auide_hwif;
761 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
762 auide_ddma_init(&auide_hwif);
766 probe_hwif_init(hwif);
767 dev_set_drvdata(dev, hwif);
769 printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
775 static int au_ide_remove(struct device *dev)
777 struct platform_device *pdev = to_platform_device(dev);
778 struct resource *res;
779 ide_hwif_t *hwif = dev_get_drvdata(dev);
780 _auide_hwif *ahwif = &auide_hwif;
782 ide_unregister(hwif - ide_hwifs);
784 iounmap((void *)ahwif->regbase);
786 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
787 release_mem_region(res->start, res->end - res->start);
792 static struct device_driver au1200_ide_driver = {
793 .name = "au1200-ide",
794 .bus = &platform_bus_type,
795 .probe = au_ide_probe,
796 .remove = au_ide_remove,
799 static int __init au_ide_init(void)
801 return driver_register(&au1200_ide_driver);
804 static void __exit au_ide_exit(void)
806 driver_unregister(&au1200_ide_driver);
809 MODULE_LICENSE("GPL");
810 MODULE_DESCRIPTION("AU1200 IDE driver");
812 module_init(au_ide_init);
813 module_exit(au_ide_exit);