drivers/ide/mips/au1xxx-ide.c

   1 /*
   2  * linux/drivers/ide/mips/au1xxx-ide.c  version 01.30.00        Aug. 02 2005
   3  *
   4  * BRIEF MODULE DESCRIPTION
   5  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
   6  *
   7  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
   8  *
   9  * This program is free software; you can redistribute it and/or modify it under
  10  * the terms of the GNU General Public License as published by the Free Software
  11  * Foundation; either version 2 of the License, or (at your option) any later
  12  * version.
  13  *
  14  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  15  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  16  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
  17  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  18  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  19  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  20  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  21  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  23  * POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  * You should have received a copy of the GNU General Public License along with
  26  * this program; if not, write to the Free Software Foundation, Inc.,
  27  * 675 Mass Ave, Cambridge, MA 02139, USA.
  28  *
  29  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  30  *       Interface and Linux Device Driver" Application Note.
  31  */
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/platform_device.h>
  37
  38 #include <linux/init.h>
  39 #include <linux/ide.h>
  40 #include <linux/sysdev.h>
  41
  42 #include <linux/dma-mapping.h>
  43
  44 #include "ide-timing.h"
  45
  46 #include <asm/io.h>
  47 #include <asm/mach-au1x00/au1xxx.h>
  48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  49
  50 #include <asm/mach-au1x00/au1xxx_ide.h>
  51
  52 #define DRV_NAME        "au1200-ide"
  53 #define DRV_VERSION     "1.0"
  54 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
  55
  56 /* enable the burstmode in the dbdma */
  57 #define IDE_AU1XXX_BURSTMODE    1
  58
  59 static _auide_hwif auide_hwif;
  60 static int dbdma_init_done;
  61
  62 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
  63
  64 void auide_insw(unsigned long port, void *addr, u32 count)
  65 {
  66         _auide_hwif *ahwif = &auide_hwif;
  67         chan_tab_t *ctp;
  68         au1x_ddma_desc_t *dp;
  69
  70         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
  71                            DDMA_FLAGS_NOIE)) {
  72                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
  73                 return;
  74         }
  75         ctp = *((chan_tab_t **)ahwif->rx_chan);
  76         dp = ctp->cur_ptr;
  77         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  78                 ;
  79         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  80 }
  81
  82 void auide_outsw(unsigned long port, void *addr, u32 count)
  83 {
  84         _auide_hwif *ahwif = &auide_hwif;
  85         chan_tab_t *ctp;
  86         au1x_ddma_desc_t *dp;
  87
  88         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
  89                              count << 1, DDMA_FLAGS_NOIE)) {
  90                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
  91                 return;
  92         }
  93         ctp = *((chan_tab_t **)ahwif->tx_chan);
  94         dp = ctp->cur_ptr;
  95         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  96                 ;
  97         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  98 }
  99
 100 #endif
 101
 102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 103 {
 104         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 105
 106         /* set pio mode! */
 107         switch(pio) {
 108         case 0:
 109                 mem_sttime = SBC_IDE_TIMING(PIO0);
 110
 111                 /* set configuration for RCS2# */
 112                 mem_stcfg |= TS_MASK;
 113                 mem_stcfg &= ~TCSOE_MASK;
 114                 mem_stcfg &= ~TOECS_MASK;
 115                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
 116                 break;
 117
 118         case 1:
 119                 mem_sttime = SBC_IDE_TIMING(PIO1);
 120
 121                 /* set configuration for RCS2# */
 122                 mem_stcfg |= TS_MASK;
 123                 mem_stcfg &= ~TCSOE_MASK;
 124                 mem_stcfg &= ~TOECS_MASK;
 125                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
 126                 break;
 127
 128         case 2:
 129                 mem_sttime = SBC_IDE_TIMING(PIO2);
 130
 131                 /* set configuration for RCS2# */
 132                 mem_stcfg &= ~TS_MASK;
 133                 mem_stcfg &= ~TCSOE_MASK;
 134                 mem_stcfg &= ~TOECS_MASK;
 135                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
 136                 break;
 137
 138         case 3:
 139                 mem_sttime = SBC_IDE_TIMING(PIO3);
 140
 141                 /* set configuration for RCS2# */
 142                 mem_stcfg &= ~TS_MASK;
 143                 mem_stcfg &= ~TCSOE_MASK;
 144                 mem_stcfg &= ~TOECS_MASK;
 145                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
 146
 147                 break;
 148
 149         case 4:
 150                 mem_sttime = SBC_IDE_TIMING(PIO4);
 151
 152                 /* set configuration for RCS2# */
 153                 mem_stcfg &= ~TS_MASK;
 154                 mem_stcfg &= ~TCSOE_MASK;
 155                 mem_stcfg &= ~TOECS_MASK;
 156                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
 157                 break;
 158         }
 159
 160         au_writel(mem_sttime,MEM_STTIME2);
 161         au_writel(mem_stcfg,MEM_STCFG2);
 162 }
 163
 164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
 165 {
 166         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 167
 168         switch(speed) {
 169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 170         case XFER_MW_DMA_2:
 171                 mem_sttime = SBC_IDE_TIMING(MDMA2);
 172
 173                 /* set configuration for RCS2# */
 174                 mem_stcfg &= ~TS_MASK;
 175                 mem_stcfg &= ~TCSOE_MASK;
 176                 mem_stcfg &= ~TOECS_MASK;
 177                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
 178
 179                 break;
 180         case XFER_MW_DMA_1:
 181                 mem_sttime = SBC_IDE_TIMING(MDMA1);
 182
 183                 /* set configuration for RCS2# */
 184                 mem_stcfg &= ~TS_MASK;
 185                 mem_stcfg &= ~TCSOE_MASK;
 186                 mem_stcfg &= ~TOECS_MASK;
 187                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
 188
 189                 break;
 190         case XFER_MW_DMA_0:
 191                 mem_sttime = SBC_IDE_TIMING(MDMA0);
 192
 193                 /* set configuration for RCS2# */
 194                 mem_stcfg |= TS_MASK;
 195                 mem_stcfg &= ~TCSOE_MASK;
 196                 mem_stcfg &= ~TOECS_MASK;
 197                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
 198
 199                 break;
 200 #endif
 201         }
 202
 203         au_writel(mem_sttime,MEM_STTIME2);
 204         au_writel(mem_stcfg,MEM_STCFG2);
 205 }
 206
 207 /*
 208  * Multi-Word DMA + DbDMA functions
 209  */
 210
 211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 212
 213 static int auide_build_sglist(ide_drive_t *drive,  struct request *rq)
 214 {
 215         ide_hwif_t *hwif = drive->hwif;
 216         struct scatterlist *sg = hwif->sg_table;
 217
 218         ide_map_sg(drive, rq);
 219
 220         if (rq_data_dir(rq) == READ)
 221                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 222         else
 223                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 224
 225         return dma_map_sg(hwif->dev, sg, hwif->sg_nents,
 226                           hwif->sg_dma_direction);
 227 }
 228
 229 static int auide_build_dmatable(ide_drive_t *drive)
 230 {
 231         int i, iswrite, count = 0;
 232         ide_hwif_t *hwif = HWIF(drive);
 233
 234         struct request *rq = HWGROUP(drive)->rq;
 235
 236         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
 237         struct scatterlist *sg;
 238
 239         iswrite = (rq_data_dir(rq) == WRITE);
 240         /* Save for interrupt context */
 241         ahwif->drive = drive;
 242
 243         /* Build sglist */
 244         hwif->sg_nents = i = auide_build_sglist(drive, rq);
 245
 246         if (!i)
 247                 return 0;
 248
 249         /* fill the descriptors */
 250         sg = hwif->sg_table;
 251         while (i && sg_dma_len(sg)) {
 252                 u32 cur_addr;
 253                 u32 cur_len;
 254
 255                 cur_addr = sg_dma_address(sg);
 256                 cur_len = sg_dma_len(sg);
 257
 258                 while (cur_len) {
 259                         u32 flags = DDMA_FLAGS_NOIE;
 260                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
 261
 262                         if (++count >= PRD_ENTRIES) {
 263                                 printk(KERN_WARNING "%s: DMA table too small\n",
 264                                        drive->name);
 265                                 goto use_pio_instead;
 266                         }
 267
 268                         /* Lets enable intr for the last descriptor only */
 269                         if (1==i)
 270                                 flags = DDMA_FLAGS_IE;
 271                         else
 272                                 flags = DDMA_FLAGS_NOIE;
 273
 274                         if (iswrite) {
 275                                 if(!put_source_flags(ahwif->tx_chan,
 276                                                      (void*) sg_virt(sg),
 277                                                      tc, flags)) {
 278                                         printk(KERN_ERR "%s failed %d\n",
 279                                                __FUNCTION__, __LINE__);
 280                                 }
 281                         } else
 282                         {
 283                                 if(!put_dest_flags(ahwif->rx_chan,
 284                                                    (void*) sg_virt(sg),
 285                                                    tc, flags)) {
 286                                         printk(KERN_ERR "%s failed %d\n",
 287                                                __FUNCTION__, __LINE__);
 288                                 }
 289                         }
 290
 291                         cur_addr += tc;
 292                         cur_len -= tc;
 293                 }
 294                 sg = sg_next(sg);
 295                 i--;
 296         }
 297
 298         if (count)
 299                 return 1;
 300
 301  use_pio_instead:
 302         dma_unmap_sg(hwif->dev,
 303                      hwif->sg_table,
 304                      hwif->sg_nents,
 305                      hwif->sg_dma_direction);
 306
 307         return 0; /* revert to PIO for this request */
 308 }
 309
 310 static int auide_dma_end(ide_drive_t *drive)
 311 {
 312         ide_hwif_t *hwif = HWIF(drive);
 313
 314         if (hwif->sg_nents) {
 315                 dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->sg_nents,
 316                              hwif->sg_dma_direction);
 317                 hwif->sg_nents = 0;
 318         }
 319
 320         return 0;
 321 }
 322
 323 static void auide_dma_start(ide_drive_t *drive )
 324 {
 325 }
 326
 327
 328 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
 329 {
 330         /* issue cmd to drive */
 331         ide_execute_command(drive, command, &ide_dma_intr,
 332                             (2*WAIT_CMD), NULL);
 333 }
 334
 335 static int auide_dma_setup(ide_drive_t *drive)
 336 {
 337         struct request *rq = HWGROUP(drive)->rq;
 338
 339         if (!auide_build_dmatable(drive)) {
 340                 ide_map_sg(drive, rq);
 341                 return 1;
 342         }
 343
 344         drive->waiting_for_dma = 1;
 345         return 0;
 346 }
 347
 348 static u8 auide_mdma_filter(ide_drive_t *drive)
 349 {
 350         /*
 351          * FIXME: ->white_list and ->black_list are based on completely bogus
 352          * ->ide_dma_check implementation which didn't set neither the host
 353          * controller timings nor the device for the desired transfer mode.
 354          *
 355          * They should be either removed or 0x00 MWDMA mask should be
 356          * returned for devices on the ->black_list.
 357          */
 358
 359         if (dbdma_init_done == 0) {
 360                 auide_hwif.white_list = ide_in_drive_list(drive->id,
 361                                                           dma_white_list);
 362                 auide_hwif.black_list = ide_in_drive_list(drive->id,
 363                                                           dma_black_list);
 364                 auide_hwif.drive = drive;
 365                 auide_ddma_init(&auide_hwif);
 366                 dbdma_init_done = 1;
 367         }
 368
 369         /* Is the drive in our DMA black list? */
 370         if (auide_hwif.black_list)
 371                 printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
 372                                     drive->name, drive->id->model);
 373
 374         return drive->hwif->mwdma_mask;
 375 }
 376
 377 static int auide_dma_test_irq(ide_drive_t *drive)
 378 {
 379         if (drive->waiting_for_dma == 0)
 380                 printk(KERN_WARNING "%s: ide_dma_test_irq \
 381                                      called while not waiting\n", drive->name);
 382
 383         /* If dbdma didn't execute the STOP command yet, the
 384          * active bit is still set
 385          */
 386         drive->waiting_for_dma++;
 387         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
 388                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
 389                                      complete\n", drive->name);
 390                 return 1;
 391         }
 392         udelay(10);
 393         return 0;
 394 }
 395
 396 static void auide_dma_host_set(ide_drive_t *drive, int on)
 397 {
 398 }
 399
 400 static void auide_dma_lost_irq(ide_drive_t *drive)
 401 {
 402         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 403 }
 404
 405 static void auide_ddma_tx_callback(int irq, void *param)
 406 {
 407         _auide_hwif *ahwif = (_auide_hwif*)param;
 408         ahwif->drive->waiting_for_dma = 0;
 409 }
 410
 411 static void auide_ddma_rx_callback(int irq, void *param)
 412 {
 413         _auide_hwif *ahwif = (_auide_hwif*)param;
 414         ahwif->drive->waiting_for_dma = 0;
 415 }
 416
 417 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 418
 419 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
 420 {
 421         dev->dev_id          = dev_id;
 422         dev->dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
 423         dev->dev_intlevel    = 0;
 424         dev->dev_intpolarity = 0;
 425         dev->dev_tsize       = tsize;
 426         dev->dev_devwidth    = devwidth;
 427         dev->dev_flags       = flags;
 428 }
 429
 430 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 431
 432 static void auide_dma_timeout(ide_drive_t *drive)
 433 {
 434         ide_hwif_t *hwif = HWIF(drive);
 435
 436         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 437
 438         if (hwif->ide_dma_test_irq(drive))
 439                 return;
 440
 441         hwif->ide_dma_end(drive);
 442 }
 443
 444
 445 static int auide_ddma_init(_auide_hwif *auide) {
 446
 447         dbdev_tab_t source_dev_tab, target_dev_tab;
 448         u32 dev_id, tsize, devwidth, flags;
 449         ide_hwif_t *hwif = auide->hwif;
 450
 451         dev_id   = AU1XXX_ATA_DDMA_REQ;
 452
 453         if (auide->white_list || auide->black_list) {
 454                 tsize    = 8;
 455                 devwidth = 32;
 456         }
 457         else {
 458                 tsize    = 1;
 459                 devwidth = 16;
 460
 461                 printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
 462                 printk(KERN_ERR "            please read 'Documentation/mips/AU1xxx_IDE.README'");
 463         }
 464
 465 #ifdef IDE_AU1XXX_BURSTMODE
 466         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 467 #else
 468         flags = DEV_FLAGS_SYNC;
 469 #endif
 470
 471         /* setup dev_tab for tx channel */
 472         auide_init_dbdma_dev( &source_dev_tab,
 473                               dev_id,
 474                               tsize, devwidth, DEV_FLAGS_OUT | flags);
 475         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 476
 477         auide_init_dbdma_dev( &source_dev_tab,
 478                               dev_id,
 479                               tsize, devwidth, DEV_FLAGS_IN | flags);
 480         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 481
 482         /* We also need to add a target device for the DMA */
 483         auide_init_dbdma_dev( &target_dev_tab,
 484                               (u32)DSCR_CMD0_ALWAYS,
 485                               tsize, devwidth, DEV_FLAGS_ANYUSE);
 486         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
 487
 488         /* Get a channel for TX */
 489         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
 490                                                  auide->tx_dev_id,
 491                                                  auide_ddma_tx_callback,
 492                                                  (void*)auide);
 493
 494         /* Get a channel for RX */
 495         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 496                                                  auide->target_dev_id,
 497                                                  auide_ddma_rx_callback,
 498                                                  (void*)auide);
 499
 500         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 501                                                              NUM_DESCRIPTORS);
 502         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 503                                                              NUM_DESCRIPTORS);
 504
 505         hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev,
 506                                                 PRD_ENTRIES * PRD_BYTES,        /* 1 Page */
 507                                                 &hwif->dmatable_dma, GFP_KERNEL);
 508
 509         au1xxx_dbdma_start( auide->tx_chan );
 510         au1xxx_dbdma_start( auide->rx_chan );
 511
 512         return 0;
 513 }
 514 #else
 515
 516 static int auide_ddma_init( _auide_hwif *auide )
 517 {
 518         dbdev_tab_t source_dev_tab;
 519         int flags;
 520
 521 #ifdef IDE_AU1XXX_BURSTMODE
 522         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 523 #else
 524         flags = DEV_FLAGS_SYNC;
 525 #endif
 526
 527         /* setup dev_tab for tx channel */
 528         auide_init_dbdma_dev( &source_dev_tab,
 529                               (u32)DSCR_CMD0_ALWAYS,
 530                               8, 32, DEV_FLAGS_OUT | flags);
 531         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 532
 533         auide_init_dbdma_dev( &source_dev_tab,
 534                               (u32)DSCR_CMD0_ALWAYS,
 535                               8, 32, DEV_FLAGS_IN | flags);
 536         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 537
 538         /* Get a channel for TX */
 539         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
 540                                                  auide->tx_dev_id,
 541                                                  NULL,
 542                                                  (void*)auide);
 543
 544         /* Get a channel for RX */
 545         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 546                                                  DSCR_CMD0_ALWAYS,
 547                                                  NULL,
 548                                                  (void*)auide);
 549
 550         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 551                                                              NUM_DESCRIPTORS);
 552         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 553                                                              NUM_DESCRIPTORS);
 554
 555         au1xxx_dbdma_start( auide->tx_chan );
 556         au1xxx_dbdma_start( auide->rx_chan );
 557
 558         return 0;
 559 }
 560 #endif
 561
 562 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
 563 {
 564         int i;
 565         unsigned long *ata_regs = hw->io_ports;
 566
 567         /* FIXME? */
 568         for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
 569                 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
 570         }
 571
 572         /* set the Alternative Status register */
 573         *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
 574 }
 575
 576 static int au_ide_probe(struct device *dev)
 577 {
 578         struct platform_device *pdev = to_platform_device(dev);
 579         _auide_hwif *ahwif = &auide_hwif;
 580         ide_hwif_t *hwif;
 581         struct resource *res;
 582         int ret = 0;
 583         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 584         hw_regs_t hw;
 585
 586 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 587         char *mode = "MWDMA2";
 588 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
 589         char *mode = "PIO+DDMA(offload)";
 590 #endif
 591
 592         memset(&auide_hwif, 0, sizeof(_auide_hwif));
 593         ahwif->irq = platform_get_irq(pdev, 0);
 594
 595         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 596
 597         if (res == NULL) {
 598                 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
 599                 ret = -ENODEV;
 600                 goto out;
 601         }
 602         if (ahwif->irq < 0) {
 603                 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
 604                 ret = -ENODEV;
 605                 goto out;
 606         }
 607
 608         if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
 609                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
 610                 ret =  -EBUSY;
 611                 goto out;
 612         }
 613
 614         ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
 615         if (ahwif->regbase == 0) {
 616                 ret = -ENOMEM;
 617                 goto out;
 618         }
 619
 620         /* FIXME:  This might possibly break PCMCIA IDE devices */
 621
 622         hwif                            = &ide_hwifs[pdev->id];
 623
 624         memset(&hw, 0, sizeof(hw));
 625         auide_setup_ports(&hw, ahwif);
 626         hw.irq = ahwif->irq;
 627         hw.chipset = ide_au1xxx;
 628
 629         ide_init_port_hw(hwif, &hw);
 630
 631         hwif->dev = dev;
 632
 633         hwif->ultra_mask                = 0x0;  /* Disable Ultra DMA */
 634 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 635         hwif->mwdma_mask                = 0x07; /* Multimode-2 DMA  */
 636         hwif->swdma_mask                = 0x00;
 637 #else
 638         hwif->mwdma_mask                = 0x0;
 639         hwif->swdma_mask                = 0x0;
 640 #endif
 641
 642         hwif->pio_mask = ATA_PIO4;
 643         hwif->host_flags = IDE_HFLAG_POST_SET_MODE;
 644
 645         hwif->drives[0].unmask          = 1;
 646         hwif->drives[1].unmask          = 1;
 647
 648         /* hold should be on in all cases */
 649         hwif->hold                      = 1;
 650
 651         hwif->mmio  = 1;
 652
 653         /* If the user has selected DDMA assisted copies,
 654            then set up a few local I/O function entry points
 655         */
 656
 657 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 658         hwif->INSW                      = auide_insw;
 659         hwif->OUTSW                     = auide_outsw;
 660 #endif
 661
 662         hwif->set_pio_mode              = &au1xxx_set_pio_mode;
 663         hwif->set_dma_mode              = &auide_set_dma_mode;
 664
 665 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 666         hwif->dma_timeout               = &auide_dma_timeout;
 667
 668         hwif->mdma_filter               = &auide_mdma_filter;
 669
 670         hwif->dma_host_set              = &auide_dma_host_set;
 671         hwif->dma_exec_cmd              = &auide_dma_exec_cmd;
 672         hwif->dma_start                 = &auide_dma_start;
 673         hwif->ide_dma_end               = &auide_dma_end;
 674         hwif->dma_setup                 = &auide_dma_setup;
 675         hwif->ide_dma_test_irq          = &auide_dma_test_irq;
 676         hwif->dma_lost_irq              = &auide_dma_lost_irq;
 677 #endif
 678         hwif->channel                   = 0;
 679         hwif->select_data               = 0;    /* no chipset-specific code */
 680         hwif->config_data               = 0;    /* no chipset-specific code */
 681
 682         hwif->drives[0].autotune        = 1;    /* 1=autotune, 2=noautotune, 0=default */
 683         hwif->drives[1].autotune        = 1;
 684
 685         hwif->drives[0].no_io_32bit     = 1;
 686         hwif->drives[1].no_io_32bit     = 1;
 687
 688         auide_hwif.hwif                 = hwif;
 689         hwif->hwif_data                 = &auide_hwif;
 690
 691 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 692         auide_ddma_init(&auide_hwif);
 693         dbdma_init_done = 1;
 694 #endif
 695
 696         idx[0] = hwif->index;
 697
 698         ide_device_add(idx);
 699
 700         dev_set_drvdata(dev, hwif);
 701
 702         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
 703
 704  out:
 705         return ret;
 706 }
 707
 708 static int au_ide_remove(struct device *dev)
 709 {
 710         struct platform_device *pdev = to_platform_device(dev);
 711         struct resource *res;
 712         ide_hwif_t *hwif = dev_get_drvdata(dev);
 713         _auide_hwif *ahwif = &auide_hwif;
 714
 715         ide_unregister(hwif - ide_hwifs);
 716
 717         iounmap((void *)ahwif->regbase);
 718
 719         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 720         release_mem_region(res->start, res->end - res->start);
 721
 722         return 0;
 723 }
 724
 725 static struct device_driver au1200_ide_driver = {
 726         .name           = "au1200-ide",
 727         .bus            = &platform_bus_type,
 728         .probe          = au_ide_probe,
 729         .remove         = au_ide_remove,
 730 };
 731
 732 static int __init au_ide_init(void)
 733 {
 734         return driver_register(&au1200_ide_driver);
 735 }
 736
 737 static void __exit au_ide_exit(void)
 738 {
 739         driver_unregister(&au1200_ide_driver);
 740 }
 741
 742 MODULE_LICENSE("GPL");
 743 MODULE_DESCRIPTION("AU1200 IDE driver");
 744
 745 module_init(au_ide_init);
 746 module_exit(au_ide_exit);