2 * linux/drivers/ide/pci/aec62xx.c Version 0.24 May 24, 2007
4 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
9 #include <linux/module.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/delay.h>
13 #include <linux/hdreg.h>
14 #include <linux/ide.h>
15 #include <linux/init.h>
19 struct chipset_bus_clock_list_entry {
25 static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
26 { XFER_UDMA_6, 0x31, 0x07 },
27 { XFER_UDMA_5, 0x31, 0x06 },
28 { XFER_UDMA_4, 0x31, 0x05 },
29 { XFER_UDMA_3, 0x31, 0x04 },
30 { XFER_UDMA_2, 0x31, 0x03 },
31 { XFER_UDMA_1, 0x31, 0x02 },
32 { XFER_UDMA_0, 0x31, 0x01 },
34 { XFER_MW_DMA_2, 0x31, 0x00 },
35 { XFER_MW_DMA_1, 0x31, 0x00 },
36 { XFER_MW_DMA_0, 0x0a, 0x00 },
37 { XFER_PIO_4, 0x31, 0x00 },
38 { XFER_PIO_3, 0x33, 0x00 },
39 { XFER_PIO_2, 0x08, 0x00 },
40 { XFER_PIO_1, 0x0a, 0x00 },
41 { XFER_PIO_0, 0x00, 0x00 },
45 static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
46 { XFER_UDMA_6, 0x41, 0x06 },
47 { XFER_UDMA_5, 0x41, 0x05 },
48 { XFER_UDMA_4, 0x41, 0x04 },
49 { XFER_UDMA_3, 0x41, 0x03 },
50 { XFER_UDMA_2, 0x41, 0x02 },
51 { XFER_UDMA_1, 0x41, 0x01 },
52 { XFER_UDMA_0, 0x41, 0x01 },
54 { XFER_MW_DMA_2, 0x41, 0x00 },
55 { XFER_MW_DMA_1, 0x42, 0x00 },
56 { XFER_MW_DMA_0, 0x7a, 0x00 },
57 { XFER_PIO_4, 0x41, 0x00 },
58 { XFER_PIO_3, 0x43, 0x00 },
59 { XFER_PIO_2, 0x78, 0x00 },
60 { XFER_PIO_1, 0x7a, 0x00 },
61 { XFER_PIO_0, 0x70, 0x00 },
66 ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
70 * TO DO: active tuning and correction of cards without a bios.
72 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
74 for ( ; chipset_table->xfer_speed ; chipset_table++)
75 if (chipset_table->xfer_speed == speed) {
76 return chipset_table->chipset_settings;
78 return chipset_table->chipset_settings;
81 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
83 for ( ; chipset_table->xfer_speed ; chipset_table++)
84 if (chipset_table->xfer_speed == speed) {
85 return chipset_table->ultra_settings;
87 return chipset_table->ultra_settings;
90 static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
92 ide_hwif_t *hwif = HWIF(drive);
93 struct pci_dev *dev = hwif->pci_dev;
95 u8 speed = ide_rate_filter(drive, xferspeed);
96 u8 ultra = 0, ultra_conf = 0;
97 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
100 local_irq_save(flags);
101 /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
102 pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
103 tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
104 d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
105 pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
109 pci_read_config_byte(dev, 0x54, &ultra);
110 tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
111 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
112 tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
113 pci_write_config_byte(dev, 0x54, tmp2);
114 local_irq_restore(flags);
115 return(ide_config_drive_speed(drive, speed));
118 static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
120 ide_hwif_t *hwif = HWIF(drive);
121 struct pci_dev *dev = hwif->pci_dev;
122 u8 speed = ide_rate_filter(drive, xferspeed);
123 u8 unit = (drive->select.b.unit & 0x01);
124 u8 tmp1 = 0, tmp2 = 0;
125 u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
128 local_irq_save(flags);
129 /* high 4-bits: Active, low 4-bits: Recovery */
130 pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
131 drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
132 pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
134 pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
135 tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
136 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
137 tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
138 pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
139 local_irq_restore(flags);
140 return(ide_config_drive_speed(drive, speed));
143 static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
145 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
146 (void) HWIF(drive)->speedproc(drive, pio + XFER_PIO_0);
149 static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
151 if (ide_tune_dma(drive))
154 if (ide_use_fast_pio(drive))
155 aec62xx_tune_drive(drive, 255);
160 static void aec62xx_dma_lost_irq (ide_drive_t *drive)
162 switch (HWIF(drive)->pci_dev->device) {
163 case PCI_DEVICE_ID_ARTOP_ATP860:
164 case PCI_DEVICE_ID_ARTOP_ATP860R:
165 case PCI_DEVICE_ID_ARTOP_ATP865:
166 case PCI_DEVICE_ID_ARTOP_ATP865R:
167 printk(" AEC62XX time out ");
173 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
175 int bus_speed = system_bus_clock();
177 if (dev->resource[PCI_ROM_RESOURCE].start) {
178 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
179 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
180 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
184 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
186 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
188 /* These are necessary to get AEC6280 Macintosh cards to work */
189 if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
190 (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
191 u8 reg49h = 0, reg4ah = 0;
192 /* Clear reset and test bits. */
193 pci_read_config_byte(dev, 0x49, ®49h);
194 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
195 /* Enable chip interrupt output. */
196 pci_read_config_byte(dev, 0x4a, ®4ah);
197 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
198 /* Enable burst mode. */
199 pci_read_config_byte(dev, 0x4a, ®4ah);
200 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
206 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
208 struct pci_dev *dev = hwif->pci_dev;
209 u8 reg54 = 0, mask = hwif->channel ? 0xf0 : 0x0f;
212 hwif->tuneproc = &aec62xx_tune_drive;
214 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
216 hwif->mate->serialized = hwif->serialized = 1;
217 hwif->speedproc = &aec6210_tune_chipset;
219 hwif->speedproc = &aec6260_tune_chipset;
221 if (!hwif->dma_base) {
222 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
226 hwif->ultra_mask = hwif->cds->udma_mask;
227 hwif->mwdma_mask = 0x07;
229 hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate;
230 hwif->dma_lost_irq = &aec62xx_dma_lost_irq;
232 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
233 spin_lock_irqsave(&ide_lock, flags);
234 pci_read_config_byte (dev, 0x54, ®54);
235 pci_write_config_byte(dev, 0x54, (reg54 & ~mask));
236 spin_unlock_irqrestore(&ide_lock, flags);
237 } else if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
238 u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
240 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
242 hwif->cbl = (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
247 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
250 static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
252 return ide_setup_pci_device(dev, d);
255 static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
257 unsigned long dma_base = pci_resource_start(dev, 4);
259 if (inb(dma_base + 2) & 0x10) {
260 d->name = (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) ?
261 "AEC6880R" : "AEC6880";
262 d->udma_mask = 0x7f; /* udma0-6 */
265 return ide_setup_pci_device(dev, d);
268 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
271 .init_setup = init_setup_aec62xx,
272 .init_chipset = init_chipset_aec62xx,
273 .init_hwif = init_hwif_aec62xx,
276 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
277 .bootable = OFF_BOARD,
278 .udma_mask = 0x07, /* udma0-2 */
281 .init_setup = init_setup_aec62xx,
282 .init_chipset = init_chipset_aec62xx,
283 .init_hwif = init_hwif_aec62xx,
285 .autodma = NOAUTODMA,
286 .bootable = OFF_BOARD,
287 .udma_mask = 0x1f, /* udma0-4 */
290 .init_setup = init_setup_aec62xx,
291 .init_chipset = init_chipset_aec62xx,
292 .init_hwif = init_hwif_aec62xx,
295 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
296 .bootable = NEVER_BOARD,
297 .udma_mask = 0x1f, /* udma0-4 */
300 .init_setup = init_setup_aec6x80,
301 .init_chipset = init_chipset_aec62xx,
302 .init_hwif = init_hwif_aec62xx,
305 .bootable = OFF_BOARD,
306 .udma_mask = 0x3f, /* udma0-5 */
309 .init_setup = init_setup_aec6x80,
310 .init_chipset = init_chipset_aec62xx,
311 .init_hwif = init_hwif_aec62xx,
314 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
315 .bootable = OFF_BOARD,
316 .udma_mask = 0x3f, /* udma0-5 */
321 * aec62xx_init_one - called when a AEC is found
322 * @dev: the aec62xx device
323 * @id: the matching pci id
325 * Called when the PCI registration layer (or the IDE initialization)
326 * finds a device matching our IDE device tables.
328 * NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
329 * chips, pass a local copy of 'struct pci_device_id' down the call chain.
332 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
334 ide_pci_device_t d = aec62xx_chipsets[id->driver_data];
336 return d.init_setup(dev, &d);
339 static struct pci_device_id aec62xx_pci_tbl[] = {
340 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
341 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
342 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
343 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
344 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
347 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
349 static struct pci_driver driver = {
350 .name = "AEC62xx_IDE",
351 .id_table = aec62xx_pci_tbl,
352 .probe = aec62xx_init_one,
355 static int __init aec62xx_ide_init(void)
357 return ide_pci_register_driver(&driver);
360 module_init(aec62xx_ide_init);
362 MODULE_AUTHOR("Andre Hedrick");
363 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
364 MODULE_LICENSE("GPL");