2 * linux/drivers/ide/pci/hpt366.c Version 1.11 Aug 11, 2007
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
21 * Note that final HPT370 support was done by force extraction of GPL.
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
56 * Alan Cox <alan@redhat.com>
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * does not allow for this speed anyway
65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * their primary channel is kind of virtual, it isn't tied to any pins)
67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
68 * HPT37x chip family; save space by introducing the separate transfer mode
69 * table in which the mode lookup is done
70 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
71 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
72 * read it only from the function 0 of HPT374 chips
73 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
74 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
75 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
76 * they tamper with its fields
77 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
78 * since they may tamper with its fields
79 * - prefix the driver startup messages with the real chip name
80 * - claim the extra 240 bytes of I/O space for all chips
81 * - optimize the UltraDMA filtering and the drive list lookup code
82 * - use pci_get_slot() to get to the function 1 of HPT36x/374
83 * - cache offset of the channel's misc. control registers (MCRs) being used
84 * throughout the driver
85 * - only touch the relevant MCR when detecting the cable type on HPT374's
87 * - rename all the register related variables consistently
88 * - move all the interrupt twiddling code from the speedproc handlers into
89 * init_hwif_hpt366(), also grouping all the DMA related code together there
90 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
91 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
92 * when setting an UltraDMA mode
93 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
94 * the best possible one
95 * - clean up DMA timeout handling for HPT370
96 * - switch to using the enumeration type to differ between the numerous chip
97 * variants, matching PCI device/revision ID with the chip type early, at the
99 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
100 * stop duplicating it for each channel by storing the pointer in the pci_dev
101 * structure: first, at the init_setup stage, point it to a static "template"
102 * with only the chip type and its specific base DPLL frequency, the highest
103 * UltraDMA mode, and the chip settings table pointer filled, then, at the
104 * init_chipset stage, allocate per-chip instance and fill it with the rest
105 * of the necessary information
106 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
107 * switch to calculating PCI clock frequency based on the chip's base DPLL
109 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
110 * anything newer than HPT370/A (except HPT374 that is not capable of this
111 * mode according to the manual)
112 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
113 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
114 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
115 * the register setting lists into the table indexed by the clock selected
116 * - set the correct hwif->ultra_mask for each individual chip
117 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
120 #include <linux/types.h>
121 #include <linux/module.h>
122 #include <linux/kernel.h>
123 #include <linux/delay.h>
124 #include <linux/timer.h>
125 #include <linux/mm.h>
126 #include <linux/ioport.h>
127 #include <linux/blkdev.h>
128 #include <linux/hdreg.h>
130 #include <linux/interrupt.h>
131 #include <linux/pci.h>
132 #include <linux/init.h>
133 #include <linux/ide.h>
135 #include <asm/uaccess.h>
139 /* various tuning parameters */
140 #define HPT_RESET_STATE_ENGINE
141 #undef HPT_DELAY_INTERRUPT
142 #define HPT_SERIALIZE_IO 0
144 static const char *quirk_drives[] = {
145 "QUANTUM FIREBALLlct08 08",
146 "QUANTUM FIREBALLP KA6.4",
147 "QUANTUM FIREBALLP LM20.4",
148 "QUANTUM FIREBALLP LM20.5",
152 static const char *bad_ata100_5[] = {
171 static const char *bad_ata66_4[] = {
187 "MAXTOR STM3320620A",
191 static const char *bad_ata66_3[] = {
196 static const char *bad_ata33[] = {
197 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
198 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
199 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
201 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
202 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
203 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
207 static u8 xfer_speeds[] = {
227 /* Key for bus clock timings
230 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
232 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
234 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
236 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
238 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
239 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
240 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
242 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
243 * task file register access.
246 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
251 static u32 forty_base_hpt36x[] = {
252 /* XFER_UDMA_6 */ 0x900fd943,
253 /* XFER_UDMA_5 */ 0x900fd943,
254 /* XFER_UDMA_4 */ 0x900fd943,
255 /* XFER_UDMA_3 */ 0x900ad943,
256 /* XFER_UDMA_2 */ 0x900bd943,
257 /* XFER_UDMA_1 */ 0x9008d943,
258 /* XFER_UDMA_0 */ 0x9008d943,
260 /* XFER_MW_DMA_2 */ 0xa008d943,
261 /* XFER_MW_DMA_1 */ 0xa010d955,
262 /* XFER_MW_DMA_0 */ 0xa010d9fc,
264 /* XFER_PIO_4 */ 0xc008d963,
265 /* XFER_PIO_3 */ 0xc010d974,
266 /* XFER_PIO_2 */ 0xc010d997,
267 /* XFER_PIO_1 */ 0xc010d9c7,
268 /* XFER_PIO_0 */ 0xc018d9d9
271 static u32 thirty_three_base_hpt36x[] = {
272 /* XFER_UDMA_6 */ 0x90c9a731,
273 /* XFER_UDMA_5 */ 0x90c9a731,
274 /* XFER_UDMA_4 */ 0x90c9a731,
275 /* XFER_UDMA_3 */ 0x90cfa731,
276 /* XFER_UDMA_2 */ 0x90caa731,
277 /* XFER_UDMA_1 */ 0x90cba731,
278 /* XFER_UDMA_0 */ 0x90c8a731,
280 /* XFER_MW_DMA_2 */ 0xa0c8a731,
281 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
282 /* XFER_MW_DMA_0 */ 0xa0c8a797,
284 /* XFER_PIO_4 */ 0xc0c8a731,
285 /* XFER_PIO_3 */ 0xc0c8a742,
286 /* XFER_PIO_2 */ 0xc0d0a753,
287 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
288 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
291 static u32 twenty_five_base_hpt36x[] = {
292 /* XFER_UDMA_6 */ 0x90c98521,
293 /* XFER_UDMA_5 */ 0x90c98521,
294 /* XFER_UDMA_4 */ 0x90c98521,
295 /* XFER_UDMA_3 */ 0x90cf8521,
296 /* XFER_UDMA_2 */ 0x90cf8521,
297 /* XFER_UDMA_1 */ 0x90cb8521,
298 /* XFER_UDMA_0 */ 0x90cb8521,
300 /* XFER_MW_DMA_2 */ 0xa0ca8521,
301 /* XFER_MW_DMA_1 */ 0xa0ca8532,
302 /* XFER_MW_DMA_0 */ 0xa0ca8575,
304 /* XFER_PIO_4 */ 0xc0ca8521,
305 /* XFER_PIO_3 */ 0xc0ca8532,
306 /* XFER_PIO_2 */ 0xc0ca8542,
307 /* XFER_PIO_1 */ 0xc0d08572,
308 /* XFER_PIO_0 */ 0xc0d08585
311 static u32 thirty_three_base_hpt37x[] = {
312 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
313 /* XFER_UDMA_5 */ 0x12446231,
314 /* XFER_UDMA_4 */ 0x12446231,
315 /* XFER_UDMA_3 */ 0x126c6231,
316 /* XFER_UDMA_2 */ 0x12486231,
317 /* XFER_UDMA_1 */ 0x124c6233,
318 /* XFER_UDMA_0 */ 0x12506297,
320 /* XFER_MW_DMA_2 */ 0x22406c31,
321 /* XFER_MW_DMA_1 */ 0x22406c33,
322 /* XFER_MW_DMA_0 */ 0x22406c97,
324 /* XFER_PIO_4 */ 0x06414e31,
325 /* XFER_PIO_3 */ 0x06414e42,
326 /* XFER_PIO_2 */ 0x06414e53,
327 /* XFER_PIO_1 */ 0x06814e93,
328 /* XFER_PIO_0 */ 0x06814ea7
331 static u32 fifty_base_hpt37x[] = {
332 /* XFER_UDMA_6 */ 0x12848242,
333 /* XFER_UDMA_5 */ 0x12848242,
334 /* XFER_UDMA_4 */ 0x12ac8242,
335 /* XFER_UDMA_3 */ 0x128c8242,
336 /* XFER_UDMA_2 */ 0x120c8242,
337 /* XFER_UDMA_1 */ 0x12148254,
338 /* XFER_UDMA_0 */ 0x121882ea,
340 /* XFER_MW_DMA_2 */ 0x22808242,
341 /* XFER_MW_DMA_1 */ 0x22808254,
342 /* XFER_MW_DMA_0 */ 0x228082ea,
344 /* XFER_PIO_4 */ 0x0a81f442,
345 /* XFER_PIO_3 */ 0x0a81f443,
346 /* XFER_PIO_2 */ 0x0a81f454,
347 /* XFER_PIO_1 */ 0x0ac1f465,
348 /* XFER_PIO_0 */ 0x0ac1f48a
351 static u32 sixty_six_base_hpt37x[] = {
352 /* XFER_UDMA_6 */ 0x1c869c62,
353 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
354 /* XFER_UDMA_4 */ 0x1c8a9c62,
355 /* XFER_UDMA_3 */ 0x1c8e9c62,
356 /* XFER_UDMA_2 */ 0x1c929c62,
357 /* XFER_UDMA_1 */ 0x1c9a9c62,
358 /* XFER_UDMA_0 */ 0x1c829c62,
360 /* XFER_MW_DMA_2 */ 0x2c829c62,
361 /* XFER_MW_DMA_1 */ 0x2c829c66,
362 /* XFER_MW_DMA_0 */ 0x2c829d2e,
364 /* XFER_PIO_4 */ 0x0c829c62,
365 /* XFER_PIO_3 */ 0x0c829c84,
366 /* XFER_PIO_2 */ 0x0c829ca6,
367 /* XFER_PIO_1 */ 0x0d029d26,
368 /* XFER_PIO_0 */ 0x0d029d5e
371 #define HPT366_DEBUG_DRIVE_INFO 0
372 #define HPT371_ALLOW_ATA133_6 1
373 #define HPT302_ALLOW_ATA133_6 1
374 #define HPT372_ALLOW_ATA133_6 1
375 #define HPT370_ALLOW_ATA100_5 0
376 #define HPT366_ALLOW_ATA66_4 1
377 #define HPT366_ALLOW_ATA66_3 1
378 #define HPT366_MAX_DEVS 8
380 /* Supported ATA clock frequencies */
391 * Hold all the HighPoint chip information in one place.
395 u8 chip_type; /* Chip type */
396 u8 max_ultra; /* Max. UltraDMA mode allowed */
397 u8 dpll_clk; /* DPLL clock in MHz */
398 u8 pci_clk; /* PCI clock in MHz */
399 u32 **settings; /* Chipset settings table */
402 /* Supported HighPoint chips */
417 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
418 twenty_five_base_hpt36x,
419 thirty_three_base_hpt36x,
425 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
427 thirty_three_base_hpt37x,
430 sixty_six_base_hpt37x
433 static struct hpt_info hpt36x __devinitdata = {
435 .max_ultra = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? 4 : 3) : 2,
436 .dpll_clk = 0, /* no DPLL */
437 .settings = hpt36x_settings
440 static struct hpt_info hpt370 __devinitdata = {
442 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
444 .settings = hpt37x_settings
447 static struct hpt_info hpt370a __devinitdata = {
448 .chip_type = HPT370A,
449 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
451 .settings = hpt37x_settings
454 static struct hpt_info hpt374 __devinitdata = {
458 .settings = hpt37x_settings
461 static struct hpt_info hpt372 __devinitdata = {
463 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
465 .settings = hpt37x_settings
468 static struct hpt_info hpt372a __devinitdata = {
469 .chip_type = HPT372A,
470 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
472 .settings = hpt37x_settings
475 static struct hpt_info hpt302 __devinitdata = {
477 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
479 .settings = hpt37x_settings
482 static struct hpt_info hpt371 __devinitdata = {
484 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
486 .settings = hpt37x_settings
489 static struct hpt_info hpt372n __devinitdata = {
490 .chip_type = HPT372N,
491 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
493 .settings = hpt37x_settings
496 static struct hpt_info hpt302n __devinitdata = {
497 .chip_type = HPT302N,
498 .max_ultra = HPT302_ALLOW_ATA133_6 ? 6 : 5,
500 .settings = hpt37x_settings
503 static struct hpt_info hpt371n __devinitdata = {
504 .chip_type = HPT371N,
505 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
507 .settings = hpt37x_settings
510 static int check_in_drive_list(ide_drive_t *drive, const char **list)
512 struct hd_driveid *id = drive->id;
515 if (!strcmp(*list++,id->model))
521 * Note for the future; the SATA hpt37x we must set
522 * either PIO or UDMA modes 0,4,5
525 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
527 struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev);
530 switch (info->chip_type) {
532 if (!HPT370_ALLOW_ATA100_5 ||
533 check_in_drive_list(drive, bad_ata100_5))
538 if (!HPT370_ALLOW_ATA100_5 ||
539 check_in_drive_list(drive, bad_ata100_5))
545 if (!HPT366_ALLOW_ATA66_4 ||
546 check_in_drive_list(drive, bad_ata66_4))
551 if (!HPT366_ALLOW_ATA66_3 ||
552 check_in_drive_list(drive, bad_ata66_3))
559 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
562 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
567 * Lookup the transfer mode table to get the index into
570 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
572 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
573 if (xfer_speeds[i] == speed)
576 * NOTE: info->settings only points to the pointer
577 * to the list of the actual register values
579 return (*info->settings)[i];
582 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
584 ide_hwif_t *hwif = HWIF(drive);
585 struct pci_dev *dev = hwif->pci_dev;
586 struct hpt_info *info = pci_get_drvdata(dev);
587 u8 speed = ide_rate_filter(drive, xferspeed);
588 u8 itr_addr = drive->dn ? 0x44 : 0x40;
590 u32 itr_mask, new_itr;
592 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */
593 if (drive->media != ide_disk)
594 speed = min_t(u8, speed, XFER_PIO_4);
596 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
597 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
599 new_itr = get_speed_setting(speed, info);
602 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
603 * to avoid problems handling I/O errors later
605 pci_read_config_dword(dev, itr_addr, &old_itr);
606 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
607 new_itr &= ~0xc0000000;
609 pci_write_config_dword(dev, itr_addr, new_itr);
611 return ide_config_drive_speed(drive, speed);
614 static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
616 ide_hwif_t *hwif = HWIF(drive);
617 struct pci_dev *dev = hwif->pci_dev;
618 struct hpt_info *info = pci_get_drvdata(dev);
619 u8 speed = ide_rate_filter(drive, xferspeed);
620 u8 itr_addr = 0x40 + (drive->dn * 4);
622 u32 itr_mask, new_itr;
624 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */
625 if (drive->media != ide_disk)
626 speed = min_t(u8, speed, XFER_PIO_4);
628 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
629 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
631 new_itr = get_speed_setting(speed, info);
633 pci_read_config_dword(dev, itr_addr, &old_itr);
634 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
636 if (speed < XFER_MW_DMA_0)
637 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
638 pci_write_config_dword(dev, itr_addr, new_itr);
640 return ide_config_drive_speed(drive, speed);
643 static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
645 ide_hwif_t *hwif = HWIF(drive);
646 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
648 if (info->chip_type >= HPT370)
649 return hpt37x_tune_chipset(drive, speed);
650 else /* hpt368: hpt_minimum_revision(dev, 2) */
651 return hpt36x_tune_chipset(drive, speed);
654 static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
656 pio = ide_get_best_pio_mode(drive, pio, 4);
657 (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
660 static int hpt3xx_quirkproc(ide_drive_t *drive)
662 struct hd_driveid *id = drive->id;
663 const char **list = quirk_drives;
666 if (strstr(id->model, *list++))
671 static void hpt3xx_intrproc(ide_drive_t *drive)
673 ide_hwif_t *hwif = HWIF(drive);
675 if (drive->quirk_list)
677 /* drives in the quirk_list may not like intr setups/cleanups */
678 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
681 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
683 ide_hwif_t *hwif = HWIF(drive);
684 struct pci_dev *dev = hwif->pci_dev;
685 struct hpt_info *info = pci_get_drvdata(dev);
687 if (drive->quirk_list) {
688 if (info->chip_type >= HPT370) {
691 pci_read_config_byte(dev, 0x5a, &scr1);
692 if (((scr1 & 0x10) >> 4) != mask) {
697 pci_write_config_byte(dev, 0x5a, scr1);
701 disable_irq(hwif->irq);
703 enable_irq (hwif->irq);
706 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
710 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
712 drive->init_speed = 0;
714 if (ide_tune_dma(drive))
717 if (ide_use_fast_pio(drive))
718 hpt3xx_tune_drive(drive, 255);
724 * This is specific to the HPT366 UDMA chipset
725 * by HighPoint|Triones Technologies, Inc.
727 static void hpt366_dma_lost_irq(ide_drive_t *drive)
729 struct pci_dev *dev = HWIF(drive)->pci_dev;
730 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
732 pci_read_config_byte(dev, 0x50, &mcr1);
733 pci_read_config_byte(dev, 0x52, &mcr3);
734 pci_read_config_byte(dev, 0x5a, &scr1);
735 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
736 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
738 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
739 ide_dma_lost_irq(drive);
742 static void hpt370_clear_engine(ide_drive_t *drive)
744 ide_hwif_t *hwif = HWIF(drive);
746 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
750 static void hpt370_irq_timeout(ide_drive_t *drive)
752 ide_hwif_t *hwif = HWIF(drive);
756 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
757 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
759 /* get DMA command mode */
760 dma_cmd = hwif->INB(hwif->dma_command);
762 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
763 hpt370_clear_engine(drive);
766 static void hpt370_ide_dma_start(ide_drive_t *drive)
768 #ifdef HPT_RESET_STATE_ENGINE
769 hpt370_clear_engine(drive);
771 ide_dma_start(drive);
774 static int hpt370_ide_dma_end(ide_drive_t *drive)
776 ide_hwif_t *hwif = HWIF(drive);
777 u8 dma_stat = hwif->INB(hwif->dma_status);
779 if (dma_stat & 0x01) {
782 dma_stat = hwif->INB(hwif->dma_status);
784 hpt370_irq_timeout(drive);
786 return __ide_dma_end(drive);
789 static void hpt370_dma_timeout(ide_drive_t *drive)
791 hpt370_irq_timeout(drive);
792 ide_dma_timeout(drive);
795 /* returns 1 if DMA IRQ issued, 0 otherwise */
796 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
798 ide_hwif_t *hwif = HWIF(drive);
802 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
804 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
808 dma_stat = inb(hwif->dma_status);
809 /* return 1 if INTR asserted */
813 if (!drive->waiting_for_dma)
814 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
815 drive->name, __FUNCTION__);
819 static int hpt374_ide_dma_end(ide_drive_t *drive)
821 ide_hwif_t *hwif = HWIF(drive);
822 struct pci_dev *dev = hwif->pci_dev;
823 u8 mcr = 0, mcr_addr = hwif->select_data;
824 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
826 pci_read_config_byte(dev, 0x6a, &bwsr);
827 pci_read_config_byte(dev, mcr_addr, &mcr);
829 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
830 return __ide_dma_end(drive);
834 * hpt3xxn_set_clock - perform clock switching dance
835 * @hwif: hwif to switch
836 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
838 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
841 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
843 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
845 if ((scr2 & 0x7f) == mode)
848 /* Tristate the bus */
849 hwif->OUTB(0x80, hwif->dma_master + 0x73);
850 hwif->OUTB(0x80, hwif->dma_master + 0x77);
852 /* Switch clock and reset channels */
853 hwif->OUTB(mode, hwif->dma_master + 0x7b);
854 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
857 * Reset the state machines.
858 * NOTE: avoid accidentally enabling the disabled channels.
860 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
861 hwif->dma_master + 0x70);
862 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
863 hwif->dma_master + 0x74);
866 hwif->OUTB(0x00, hwif->dma_master + 0x79);
868 /* Reconnect channels to bus */
869 hwif->OUTB(0x00, hwif->dma_master + 0x73);
870 hwif->OUTB(0x00, hwif->dma_master + 0x77);
874 * hpt3xxn_rw_disk - prepare for I/O
875 * @drive: drive for command
876 * @rq: block request structure
878 * This is called when a disk I/O is issued to HPT3xxN.
879 * We need it because of the clock switching.
882 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
884 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
888 * Set/get power state for a drive.
889 * NOTE: affects both drives on each channel.
891 * When we turn the power back on, we need to re-initialize things.
893 #define TRISTATE_BIT 0x8000
895 static int hpt3xx_busproc(ide_drive_t *drive, int state)
897 ide_hwif_t *hwif = HWIF(drive);
898 struct pci_dev *dev = hwif->pci_dev;
899 u8 mcr_addr = hwif->select_data + 2;
900 u8 resetmask = hwif->channel ? 0x80 : 0x40;
904 hwif->bus_state = state;
906 /* Grab the status. */
907 pci_read_config_word(dev, mcr_addr, &mcr);
908 pci_read_config_byte(dev, 0x59, &bsr2);
911 * Set the state. We don't set it if we don't need to do so.
912 * Make sure that the drive knows that it has failed if it's off.
916 if (!(bsr2 & resetmask))
918 hwif->drives[0].failures = hwif->drives[1].failures = 0;
920 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
921 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
924 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
926 mcr &= ~TRISTATE_BIT;
928 case BUSSTATE_TRISTATE:
929 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
937 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
938 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
940 pci_write_config_word(dev, mcr_addr, mcr);
941 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
946 * hpt37x_calibrate_dpll - calibrate the DPLL
949 * Perform a calibration cycle on the DPLL.
950 * Returns 1 if this succeeds
952 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
954 u32 dpll = (f_high << 16) | f_low | 0x100;
958 pci_write_config_dword(dev, 0x5c, dpll);
960 /* Wait for oscillator ready */
961 for(i = 0; i < 0x5000; ++i) {
963 pci_read_config_byte(dev, 0x5b, &scr2);
967 /* See if it stays ready (we'll just bail out if it's not yet) */
968 for(i = 0; i < 0x1000; ++i) {
969 pci_read_config_byte(dev, 0x5b, &scr2);
970 /* DPLL destabilized? */
974 /* Turn off tuning, we have the DPLL set */
975 pci_read_config_dword (dev, 0x5c, &dpll);
976 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
980 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
982 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
983 unsigned long io_base = pci_resource_start(dev, 4);
984 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
986 enum ata_clock clock;
989 printk(KERN_ERR "%s: out of memory!\n", name);
994 * Copy everything from a static "template" structure
995 * to just allocated per-chip hpt_info structure.
997 memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info));
998 chip_type = info->chip_type;
1000 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1001 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1002 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1003 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1006 * First, try to estimate the PCI clock frequency...
1008 if (chip_type >= HPT370) {
1013 /* Interrupt force enable. */
1014 pci_read_config_byte(dev, 0x5a, &scr1);
1016 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1019 * HighPoint does this for HPT372A.
1020 * NOTE: This register is only writeable via I/O space.
1022 if (chip_type == HPT372A)
1023 outb(0x0e, io_base + 0x9c);
1026 * Default to PCI clock. Make sure MA15/16 are set to output
1027 * to prevent drives having problems with 40-pin cables.
1029 pci_write_config_byte(dev, 0x5b, 0x23);
1032 * We'll have to read f_CNT value in order to determine
1033 * the PCI clock frequency according to the following ratio:
1035 * f_CNT = Fpci * 192 / Fdpll
1037 * First try reading the register in which the HighPoint BIOS
1038 * saves f_CNT value before reprogramming the DPLL from its
1039 * default setting (which differs for the various chips).
1041 * NOTE: This register is only accessible via I/O space;
1042 * HPT374 BIOS only saves it for the function 0, so we have to
1043 * always read it from there -- no need to check the result of
1044 * pci_get_slot() for the function 0 as the whole device has
1045 * been already "pinned" (via function 1) in init_setup_hpt374()
1047 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1048 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1050 unsigned long io_base = pci_resource_start(dev1, 4);
1052 temp = inl(io_base + 0x90);
1055 temp = inl(io_base + 0x90);
1058 * In case the signature check fails, we'll have to
1059 * resort to reading the f_CNT register itself in hopes
1060 * that nobody has touched the DPLL yet...
1062 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1065 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1068 /* Calculate the average value of f_CNT. */
1069 for (temp = i = 0; i < 128; i++) {
1070 pci_read_config_word(dev, 0x78, &f_cnt);
1071 temp += f_cnt & 0x1ff;
1076 f_cnt = temp & 0x1ff;
1078 dpll_clk = info->dpll_clk;
1079 pci_clk = (f_cnt * dpll_clk) / 192;
1081 /* Clamp PCI clock to bands. */
1084 else if(pci_clk < 45)
1086 else if(pci_clk < 55)
1091 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1092 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1096 pci_read_config_dword(dev, 0x40, &itr1);
1098 /* Detect PCI clock by looking at cmd_high_time. */
1099 switch((itr1 >> 8) & 0x07) {
1113 /* Let's assume we'll use PCI clock for the ATA clock... */
1116 clock = ATA_CLOCK_25MHZ;
1120 clock = ATA_CLOCK_33MHZ;
1123 clock = ATA_CLOCK_40MHZ;
1126 clock = ATA_CLOCK_50MHZ;
1129 clock = ATA_CLOCK_66MHZ;
1134 * Only try the DPLL if we don't have a table for the PCI clock that
1135 * we are running at for HPT370/A, always use it for anything newer...
1137 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1138 * We also don't like using the DPLL because this causes glitches
1139 * on PRST-/SRST- when the state engine gets reset...
1141 if (chip_type >= HPT374 || info->settings[clock] == NULL) {
1142 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1146 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1147 * supported/enabled, use 50 MHz DPLL clock otherwise...
1149 if (info->max_ultra == 6) {
1151 clock = ATA_CLOCK_66MHZ;
1152 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1154 clock = ATA_CLOCK_50MHZ;
1157 if (info->settings[clock] == NULL) {
1158 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1163 /* Select the DPLL clock. */
1164 pci_write_config_byte(dev, 0x5b, 0x21);
1167 * Adjust the DPLL based upon PCI clock, enable it,
1168 * and wait for stabilization...
1170 f_low = (pci_clk * 48) / dpll_clk;
1172 for (adjust = 0; adjust < 8; adjust++) {
1173 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1177 * See if it'll settle at a fractionally different clock
1180 f_low -= adjust >> 1;
1182 f_low += adjust >> 1;
1185 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1190 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1192 /* Mark the fact that we're not using the DPLL. */
1195 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1199 * Advance the table pointer to a slot which points to the list
1200 * of the register values settings matching the clock being used.
1202 info->settings += clock;
1204 /* Store the clock frequencies. */
1205 info->dpll_clk = dpll_clk;
1206 info->pci_clk = pci_clk;
1208 /* Point to this chip's own instance of the hpt_info structure. */
1209 pci_set_drvdata(dev, info);
1211 if (chip_type >= HPT370) {
1215 * Reset the state engines.
1216 * NOTE: Avoid accidentally enabling the disabled channels.
1218 pci_read_config_byte (dev, 0x50, &mcr1);
1219 pci_read_config_byte (dev, 0x54, &mcr4);
1220 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1221 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1226 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1227 * the MISC. register to stretch the UltraDMA Tss timing.
1228 * NOTE: This register is only writeable via I/O space.
1230 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1232 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1237 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1239 struct pci_dev *dev = hwif->pci_dev;
1240 struct hpt_info *info = pci_get_drvdata(dev);
1241 int serialize = HPT_SERIALIZE_IO;
1242 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1243 u8 chip_type = info->chip_type;
1244 u8 new_mcr, old_mcr = 0;
1246 /* Cache the channel's MISC. control registers' offset */
1247 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1249 hwif->tuneproc = &hpt3xx_tune_drive;
1250 hwif->speedproc = &hpt3xx_tune_chipset;
1251 hwif->quirkproc = &hpt3xx_quirkproc;
1252 hwif->intrproc = &hpt3xx_intrproc;
1253 hwif->maskproc = &hpt3xx_maskproc;
1254 hwif->busproc = &hpt3xx_busproc;
1256 if (chip_type <= HPT370A)
1257 hwif->udma_filter = &hpt3xx_udma_filter;
1260 * HPT3xxN chips have some complications:
1262 * - on 33 MHz PCI we must clock switch
1263 * - on 66 MHz PCI we must NOT use the PCI clock
1265 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1267 * Clock is shared between the channels,
1268 * so we'll have to serialize them... :-(
1271 hwif->rw_disk = &hpt3xxn_rw_disk;
1274 /* Serialize access to this device if needed */
1275 if (serialize && hwif->mate)
1276 hwif->serialized = hwif->mate->serialized = 1;
1279 * Disable the "fast interrupt" prediction. Don't hold off
1280 * on interrupts. (== 0x01 despite what the docs say)
1282 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1284 if (info->chip_type >= HPT374)
1285 new_mcr = old_mcr & ~0x07;
1286 else if (info->chip_type >= HPT370) {
1290 #ifdef HPT_DELAY_INTERRUPT
1295 } else /* HPT366 and HPT368 */
1296 new_mcr = old_mcr & ~0x80;
1298 if (new_mcr != old_mcr)
1299 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1301 if (!hwif->dma_base) {
1302 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1306 hwif->ultra_mask = hwif->cds->udma_mask;
1307 hwif->mwdma_mask = 0x07;
1310 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1311 * address lines to access an external EEPROM. To read valid
1312 * cable detect state the pins must be enabled as inputs.
1314 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1316 * HPT374 PCI function 1
1317 * - set bit 15 of reg 0x52 to enable TCBLID as input
1318 * - set bit 15 of reg 0x56 to enable FCBLID as input
1320 u8 mcr_addr = hwif->select_data + 2;
1323 pci_read_config_word (dev, mcr_addr, &mcr);
1324 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1325 /* now read cable id register */
1326 pci_read_config_byte (dev, 0x5a, &scr1);
1327 pci_write_config_word(dev, mcr_addr, mcr);
1328 } else if (chip_type >= HPT370) {
1330 * HPT370/372 and 374 pcifn 0
1331 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1335 pci_read_config_byte (dev, 0x5b, &scr2);
1336 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1337 /* now read cable id register */
1338 pci_read_config_byte (dev, 0x5a, &scr1);
1339 pci_write_config_byte(dev, 0x5b, scr2);
1341 pci_read_config_byte (dev, 0x5a, &scr1);
1343 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1344 hwif->cbl = (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1346 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1348 if (chip_type >= HPT374) {
1349 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1350 hwif->ide_dma_end = &hpt374_ide_dma_end;
1351 } else if (chip_type >= HPT370) {
1352 hwif->dma_start = &hpt370_ide_dma_start;
1353 hwif->ide_dma_end = &hpt370_ide_dma_end;
1354 hwif->dma_timeout = &hpt370_dma_timeout;
1356 hwif->dma_lost_irq = &hpt366_dma_lost_irq;
1360 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1363 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1365 struct pci_dev *dev = hwif->pci_dev;
1366 u8 masterdma = 0, slavedma = 0;
1367 u8 dma_new = 0, dma_old = 0;
1368 unsigned long flags;
1370 dma_old = hwif->INB(dmabase + 2);
1372 local_irq_save(flags);
1375 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1376 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1378 if (masterdma & 0x30) dma_new |= 0x20;
1379 if ( slavedma & 0x30) dma_new |= 0x40;
1380 if (dma_new != dma_old)
1381 hwif->OUTB(dma_new, dmabase + 2);
1383 local_irq_restore(flags);
1385 ide_setup_dma(hwif, dmabase, 8);
1388 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1390 struct pci_dev *dev2;
1392 if (PCI_FUNC(dev->devfn) & 1)
1395 pci_set_drvdata(dev, &hpt374);
1397 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1400 pci_set_drvdata(dev2, &hpt374);
1402 if (dev2->irq != dev->irq) {
1403 /* FIXME: we need a core pci_set_interrupt() */
1404 dev2->irq = dev->irq;
1405 printk(KERN_WARNING "%s: PCI config space interrupt "
1406 "fixed.\n", d->name);
1408 ret = ide_setup_pci_devices(dev, dev2, d);
1413 return ide_setup_pci_device(dev, d);
1416 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1418 pci_set_drvdata(dev, &hpt372n);
1420 return ide_setup_pci_device(dev, d);
1423 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1425 struct hpt_info *info;
1428 if (dev->revision > 1) {
1429 d->name = "HPT371N";
1436 * HPT371 chips physically have only one channel, the secondary one,
1437 * but the primary channel registers do exist! Go figure...
1438 * So, we manually disable the non-existing channel here
1439 * (if the BIOS hasn't done this already).
1441 pci_read_config_byte(dev, 0x50, &mcr1);
1443 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1445 pci_set_drvdata(dev, info);
1447 return ide_setup_pci_device(dev, d);
1450 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1452 struct hpt_info *info;
1454 if (dev->revision > 1) {
1455 d->name = "HPT372N";
1460 pci_set_drvdata(dev, info);
1462 return ide_setup_pci_device(dev, d);
1465 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1467 struct hpt_info *info;
1469 if (dev->revision > 1) {
1470 d->name = "HPT302N";
1475 pci_set_drvdata(dev, info);
1477 return ide_setup_pci_device(dev, d);
1480 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1482 struct pci_dev *dev2;
1483 u8 rev = dev->revision;
1484 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1485 "HPT370", "HPT370A", "HPT372",
1487 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1488 &hpt370, &hpt370a, &hpt372,
1491 if (PCI_FUNC(dev->devfn) & 1)
1499 * HPT36x chips have one channel per function and have
1500 * both channel enable bits located differently and visible
1501 * to both functions -- really stupid design decision... :-(
1502 * Bit 4 is for the primary channel, bit 5 for the secondary.
1504 d->host_flags |= IDE_HFLAG_SINGLE;
1505 d->enablebits[0].mask = d->enablebits[0].val = 0x10;
1507 d->udma_mask = HPT366_ALLOW_ATA66_3 ?
1508 (HPT366_ALLOW_ATA66_4 ? 0x1f : 0x0f) : 0x07;
1512 d->udma_mask = HPT370_ALLOW_ATA100_5 ? 0x3f : 0x1f;
1519 d->udma_mask = HPT372_ALLOW_ATA133_6 ? 0x7f : 0x3f;
1523 d->name = chipset_names[rev];
1525 pci_set_drvdata(dev, info[rev]);
1530 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1531 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1534 pci_set_drvdata(dev2, info[rev]);
1537 * Now we'll have to force both channels enabled if
1538 * at least one of them has been enabled by BIOS...
1540 pci_read_config_byte(dev, 0x50, &mcr1);
1542 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1544 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1545 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1546 if (pin1 != pin2 && dev->irq == dev2->irq) {
1547 d->bootable = ON_BOARD;
1548 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1549 d->name, pin1, pin2);
1551 ret = ide_setup_pci_devices(dev, dev2, d);
1557 return ide_setup_pci_device(dev, d);
1560 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1563 .init_setup = init_setup_hpt366,
1564 .init_chipset = init_chipset_hpt366,
1565 .init_hwif = init_hwif_hpt366,
1566 .init_dma = init_dma_hpt366,
1568 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1569 .bootable = OFF_BOARD,
1571 .pio_mask = ATA_PIO4,
1574 .init_setup = init_setup_hpt372a,
1575 .init_chipset = init_chipset_hpt366,
1576 .init_hwif = init_hwif_hpt366,
1577 .init_dma = init_dma_hpt366,
1579 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1580 .udma_mask = HPT372_ALLOW_ATA133_6 ? 0x7f : 0x3f,
1581 .bootable = OFF_BOARD,
1583 .pio_mask = ATA_PIO4,
1586 .init_setup = init_setup_hpt302,
1587 .init_chipset = init_chipset_hpt366,
1588 .init_hwif = init_hwif_hpt366,
1589 .init_dma = init_dma_hpt366,
1591 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1592 .udma_mask = HPT302_ALLOW_ATA133_6 ? 0x7f : 0x3f,
1593 .bootable = OFF_BOARD,
1595 .pio_mask = ATA_PIO4,
1598 .init_setup = init_setup_hpt371,
1599 .init_chipset = init_chipset_hpt366,
1600 .init_hwif = init_hwif_hpt366,
1601 .init_dma = init_dma_hpt366,
1603 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1604 .udma_mask = HPT371_ALLOW_ATA133_6 ? 0x7f : 0x3f,
1605 .bootable = OFF_BOARD,
1607 .pio_mask = ATA_PIO4,
1610 .init_setup = init_setup_hpt374,
1611 .init_chipset = init_chipset_hpt366,
1612 .init_hwif = init_hwif_hpt366,
1613 .init_dma = init_dma_hpt366,
1615 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1617 .bootable = OFF_BOARD,
1619 .pio_mask = ATA_PIO4,
1622 .init_setup = init_setup_hpt372n,
1623 .init_chipset = init_chipset_hpt366,
1624 .init_hwif = init_hwif_hpt366,
1625 .init_dma = init_dma_hpt366,
1627 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1628 .udma_mask = HPT372_ALLOW_ATA133_6 ? 0x7f : 0x3f,
1629 .bootable = OFF_BOARD,
1631 .pio_mask = ATA_PIO4,
1636 * hpt366_init_one - called when an HPT366 is found
1637 * @dev: the hpt366 device
1638 * @id: the matching pci id
1640 * Called when the PCI registration layer (or the IDE initialization)
1641 * finds a device matching our IDE device tables.
1643 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1644 * structure depending on the chip's revision, we'd better pass a local
1645 * copy down the call chain...
1647 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1649 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1651 return d.init_setup(dev, &d);
1654 static struct pci_device_id hpt366_pci_tbl[] = {
1655 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1656 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1657 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1658 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1659 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1660 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1663 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1665 static struct pci_driver driver = {
1666 .name = "HPT366_IDE",
1667 .id_table = hpt366_pci_tbl,
1668 .probe = hpt366_init_one,
1671 static int __init hpt366_ide_init(void)
1673 return ide_pci_register_driver(&driver);
1676 module_init(hpt366_ide_init);
1678 MODULE_AUTHOR("Andre Hedrick");
1679 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1680 MODULE_LICENSE("GPL");