2 * linux/drivers/ide/pci/piix.c Version 0.52 Jul 14, 2007
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
7 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
9 * May be copied or modified under the terms of the GNU General Public License
11 * PIO mode setting function for Intel chipsets.
12 * For use instead of BIOS settings.
20 * | PIO 0 | c0 | 80 | 0 |
21 * | PIO 2 | SW2 | d0 | 90 | 4 |
22 * | PIO 3 | MW1 | e1 | a1 | 9 |
23 * | PIO 4 | MW2 | e3 | a3 | b |
25 * sitre = word40 & 0x4000; primary
26 * sitre = word42 & 0x4000; secondary
28 * 44 8421|8421 hdd|hdb
30 * 48 8421 hdd|hdc|hdb|hda udma enabled
42 * ata-33/82801AB ata-66/82801AA
43 * 00|00 udma 0 00|00 reserved
44 * 01|01 udma 1 01|01 udma 3
45 * 10|10 udma 2 10|10 udma 4
46 * 11|11 reserved 11|11 reserved
48 * 54 8421|8421 ata66 drive|ata66 enable
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
52 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
53 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48);
54 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
55 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54);
58 * Publically available from Intel web site. Errata documentation
59 * is also publically available. As an aide to anyone hacking on this
60 * driver the list of errata that are relevant is below.going back to
61 * PIIX4. Older device documentation is now a bit tricky to find.
66 * PIIX4 errata #9 - Only on ultra obscure hw
67 * ICH3 errata #13 - Not observed to affect real hw
70 * Things we must deal with
71 * PIIX4 errata #10 - BM IDE hang with non UDMA
72 * (must stop/start dma to recover)
73 * 440MX errata #15 - As PIIX4 errata #10
74 * PIIX4 errata #15 - Must not read control registers
75 * during a PIO transfer
76 * 440MX errata #13 - As PIIX4 errata #15
77 * ICH2 errata #21 - DMA mode 0 doesn't work right
78 * ICH0/1 errata #55 - As ICH2 errata #21
79 * ICH2 spec c #9 - Extra operations needed to handle
80 * drive hotswap [NOT YET SUPPORTED]
81 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
82 * and must be dword aligned
83 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
85 * Should have been BIOS fixed:
86 * 450NX: errata #19 - DMA hangs on old 450NX
87 * 450NX: errata #20 - DMA hangs on old 450NX
88 * 450NX: errata #25 - Corruption with DMA on old 450NX
89 * ICH3 errata #15 - IDE deadlock under high load
90 * (BIOS must set dev 31 fn 0 bit 23)
91 * ICH3 errata #18 - Don't use native mode
94 #include <linux/types.h>
95 #include <linux/module.h>
96 #include <linux/kernel.h>
97 #include <linux/ioport.h>
98 #include <linux/pci.h>
99 #include <linux/hdreg.h>
100 #include <linux/ide.h>
101 #include <linux/delay.h>
102 #include <linux/init.h>
106 static int no_piix_dma;
109 * piix_set_pio_mode - set host controller for PIO mode
111 * @pio: PIO mode number
113 * Set the interface PIO mode based upon the settings done by AMI BIOS.
116 static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
118 ide_hwif_t *hwif = HWIF(drive);
119 struct pci_dev *dev = hwif->pci_dev;
120 int is_slave = drive->dn & 1;
121 int master_port = hwif->channel ? 0x42 : 0x40;
122 int slave_port = 0x44;
126 static DEFINE_SPINLOCK(tune_lock);
130 static const u8 timings[][2]= {
138 * Master vs slave is synchronized above us but the slave register is
139 * shared by the two hwifs so the corner case of two slave timeouts in
140 * parallel must be locked.
142 spin_lock_irqsave(&tune_lock, flags);
143 pci_read_config_word(dev, master_port, &master_data);
146 control |= 1; /* Programmable timing on */
147 if (drive->media == ide_disk)
148 control |= 4; /* Prefetch, post write */
150 control |= 2; /* IORDY */
152 master_data |= 0x4000;
153 master_data &= ~0x0070;
155 /* Set PPE, IE and TIME */
156 master_data |= control << 4;
158 pci_read_config_byte(dev, slave_port, &slave_data);
159 slave_data &= hwif->channel ? 0x0f : 0xf0;
160 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
161 (hwif->channel ? 4 : 0);
163 master_data &= ~0x3307;
165 /* enable PPE, IE and TIME */
166 master_data |= control;
168 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
170 pci_write_config_word(dev, master_port, master_data);
172 pci_write_config_byte(dev, slave_port, slave_data);
173 spin_unlock_irqrestore(&tune_lock, flags);
177 * piix_set_dma_mode - set host controller for DMA mode
181 * Set a PIIX host controller to the desired DMA mode. This involves
182 * programming the right timing data into the PCI configuration space.
185 static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
187 ide_hwif_t *hwif = HWIF(drive);
188 struct pci_dev *dev = hwif->pci_dev;
189 u8 maslave = hwif->channel ? 0x42 : 0x40;
190 int a_speed = 3 << (drive->dn * 4);
191 int u_flag = 1 << drive->dn;
192 int v_flag = 0x01 << drive->dn;
193 int w_flag = 0x10 << drive->dn;
197 u8 reg48, reg54, reg55, pio;
199 pci_read_config_word(dev, maslave, ®4042);
200 sitre = (reg4042 & 0x4000) ? 1 : 0;
201 pci_read_config_byte(dev, 0x48, ®48);
202 pci_read_config_word(dev, 0x4a, ®4a);
203 pci_read_config_byte(dev, 0x54, ®54);
204 pci_read_config_byte(dev, 0x55, ®55);
208 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
211 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
212 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
215 case XFER_SW_DMA_2: break;
219 if (speed >= XFER_UDMA_0) {
220 if (!(reg48 & u_flag))
221 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
222 if (speed == XFER_UDMA_5) {
223 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
225 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
227 if ((reg4a & a_speed) != u_speed)
228 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
229 if (speed > XFER_UDMA_2) {
230 if (!(reg54 & v_flag))
231 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
233 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
237 const u8 mwdma_to_pio[] = { 0, 3, 4 };
240 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
242 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
244 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
246 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
248 if (speed >= XFER_MW_DMA_0)
249 pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
251 pio = 2; /* only SWDMA2 is allowed */
254 piix_set_pio_mode(drive, pio);
258 * piix_config_drive_xfer_rate - set up an IDE device
259 * @drive: IDE drive to configure
261 * Set up the PIIX interface for the best available speed on this
262 * interface, preferring DMA to PIO.
265 static int piix_config_drive_xfer_rate (ide_drive_t *drive)
267 drive->init_speed = 0;
269 if (ide_tune_dma(drive))
272 if (ide_use_fast_pio(drive))
273 ide_set_max_pio(drive);
279 * piix_is_ichx - check if ICHx
280 * @dev: PCI device to check
282 * returns 1 if ICHx, 0 otherwise.
284 static int piix_is_ichx(struct pci_dev *dev)
286 switch (dev->device) {
287 case PCI_DEVICE_ID_INTEL_82801EB_1:
288 case PCI_DEVICE_ID_INTEL_82801AA_1:
289 case PCI_DEVICE_ID_INTEL_82801AB_1:
290 case PCI_DEVICE_ID_INTEL_82801BA_8:
291 case PCI_DEVICE_ID_INTEL_82801BA_9:
292 case PCI_DEVICE_ID_INTEL_82801CA_10:
293 case PCI_DEVICE_ID_INTEL_82801CA_11:
294 case PCI_DEVICE_ID_INTEL_82801DB_1:
295 case PCI_DEVICE_ID_INTEL_82801DB_10:
296 case PCI_DEVICE_ID_INTEL_82801DB_11:
297 case PCI_DEVICE_ID_INTEL_82801EB_11:
298 case PCI_DEVICE_ID_INTEL_82801E_11:
299 case PCI_DEVICE_ID_INTEL_ESB_2:
300 case PCI_DEVICE_ID_INTEL_ICH6_19:
301 case PCI_DEVICE_ID_INTEL_ICH7_21:
302 case PCI_DEVICE_ID_INTEL_ESB2_18:
303 case PCI_DEVICE_ID_INTEL_ICH8_6:
311 * init_chipset_piix - set up the PIIX chipset
312 * @dev: PCI device to set up
313 * @name: Name of the device
315 * Initialize the PCI device as required. For the PIIX this turns
316 * out to be nice and simple
319 static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
321 if (piix_is_ichx(dev)) {
322 unsigned int extra = 0;
323 pci_read_config_dword(dev, 0x54, &extra);
324 pci_write_config_dword(dev, 0x54, extra|0x400);
331 * piix_dma_clear_irq - clear BMDMA status
332 * @drive: IDE drive to clear
334 * Called from ide_intr() for PIO interrupts
335 * to clear BMDMA status as needed by ICHx
337 static void piix_dma_clear_irq(ide_drive_t *drive)
339 ide_hwif_t *hwif = HWIF(drive);
342 /* clear the INTR & ERROR bits */
343 dma_stat = hwif->INB(hwif->dma_status);
344 /* Should we force the bit as well ? */
345 hwif->OUTB(dma_stat, hwif->dma_status);
355 * List of laptops that use short cables rather than 80 wire
358 static const struct ich_laptop ich_laptop[] = {
359 /* devid, subvendor, subdev */
360 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
361 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
362 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
363 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
368 static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
370 struct pci_dev *pdev = hwif->pci_dev;
371 const struct ich_laptop *lap = &ich_laptop[0];
372 u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
374 /* check for specials */
375 while (lap->device) {
376 if (lap->device == pdev->device &&
377 lap->subvendor == pdev->subsystem_vendor &&
378 lap->subdevice == pdev->subsystem_device) {
379 return ATA_CBL_PATA40_SHORT;
384 pci_read_config_byte(pdev, 0x54, ®54h);
386 return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
390 * init_hwif_piix - fill in the hwif for the PIIX
391 * @hwif: IDE interface
393 * Set up the ide_hwif_t for the PIIX interface according to the
394 * capabilities of the hardware.
397 static void __devinit init_hwif_piix(ide_hwif_t *hwif)
401 hwif->irq = hwif->channel ? 15 : 14;
402 #endif /* CONFIG_IA64 */
404 if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
405 /* This is a painful system best to let it self tune for now */
411 hwif->set_pio_mode = &piix_set_pio_mode;
412 hwif->set_dma_mode = &piix_set_dma_mode;
414 hwif->drives[0].autotune = 1;
415 hwif->drives[1].autotune = 1;
420 /* ICHx need to clear the bmdma status for all interrupts */
421 if (piix_is_ichx(hwif->pci_dev))
422 hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
426 hwif->ultra_mask = hwif->cds->udma_mask;
427 hwif->mwdma_mask = 0x06;
428 hwif->swdma_mask = 0x04;
430 if (hwif->ultra_mask & 0x78) {
431 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
432 hwif->cbl = piix_cable_detect(hwif);
436 hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
438 hwif->ide_dma_check = &piix_config_drive_xfer_rate;
442 hwif->drives[1].autodma = hwif->autodma;
443 hwif->drives[0].autodma = hwif->autodma;
446 #define DECLARE_PIIX_DEV(name_str, udma) \
449 .init_chipset = init_chipset_piix, \
450 .init_hwif = init_hwif_piix, \
451 .autodma = AUTODMA, \
452 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
453 .bootable = ON_BOARD, \
454 .pio_mask = ATA_PIO4, \
458 static ide_pci_device_t piix_pci_info[] __devinitdata = {
459 /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */
460 /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */
464 * MPIIX actually has only a single IDE channel mapped to
465 * the primary or secondary ports depending on the value
466 * of the bit 14 of the IDETIM register at offset 0x6c
469 .init_hwif = init_hwif_piix,
471 .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
472 .bootable = ON_BOARD,
473 .host_flags = IDE_HFLAG_ISA_PORTS,
474 .pio_mask = ATA_PIO4,
477 /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */
478 /* 4 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
479 /* 5 */ DECLARE_PIIX_DEV("ICH0", 0x07), /* udma0-2 */
480 /* 6 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
481 /* 7 */ DECLARE_PIIX_DEV("ICH", 0x1f), /* udma0-4 */
482 /* 8 */ DECLARE_PIIX_DEV("PIIX4", 0x1f), /* udma0-4 */
483 /* 9 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
484 /* 10 */ DECLARE_PIIX_DEV("ICH2", 0x3f), /* udma0-5 */
485 /* 11 */ DECLARE_PIIX_DEV("ICH2M", 0x3f), /* udma0-5 */
486 /* 12 */ DECLARE_PIIX_DEV("ICH3M", 0x3f), /* udma0-5 */
487 /* 13 */ DECLARE_PIIX_DEV("ICH3", 0x3f), /* udma0-5 */
488 /* 14 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
489 /* 15 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
490 /* 16 */ DECLARE_PIIX_DEV("C-ICH", 0x3f), /* udma0-5 */
491 /* 17 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
492 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", 0x3f), /* udma0-5 */
493 /* 19 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
494 /* 20 */ DECLARE_PIIX_DEV("ICH6", 0x3f), /* udma0-5 */
495 /* 21 */ DECLARE_PIIX_DEV("ICH7", 0x3f), /* udma0-5 */
496 /* 22 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
497 /* 23 */ DECLARE_PIIX_DEV("ESB2", 0x3f), /* udma0-5 */
498 /* 24 */ DECLARE_PIIX_DEV("ICH8M", 0x3f), /* udma0-5 */
502 * piix_init_one - called when a PIIX is found
503 * @dev: the piix device
504 * @id: the matching pci id
506 * Called when the PCI registration layer (or the IDE initialization)
507 * finds a device matching our IDE device tables.
510 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
512 ide_pci_device_t *d = &piix_pci_info[id->driver_data];
514 return ide_setup_pci_device(dev, d);
518 * piix_check_450nx - Check for problem 450NX setup
520 * Check for the present of 450NX errata #19 and errata #25. If
521 * they are found, disable use of DMA IDE
524 static void __devinit piix_check_450nx(void)
526 struct pci_dev *pdev = NULL;
528 while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
530 /* Look for 450NX PXB. Check for problem configurations
531 A PCI quirk checks bit 6 already */
532 pci_read_config_word(pdev, 0x41, &cfg);
533 /* Only on the original revision: IDE DMA can hang */
534 if (pdev->revision == 0x00)
536 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
537 else if (cfg & (1<<14) && pdev->revision < 5)
541 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
543 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
546 static struct pci_device_id piix_pci_tbl[] = {
547 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
548 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
549 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
550 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
551 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
552 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
553 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
554 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
555 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
556 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
557 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
558 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
559 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
560 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
561 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
562 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
563 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
564 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
565 #ifdef CONFIG_BLK_DEV_IDE_SATA
566 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
568 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
569 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
570 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
571 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22},
572 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23},
573 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24},
576 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
578 static struct pci_driver driver = {
580 .id_table = piix_pci_tbl,
581 .probe = piix_init_one,
584 static int __init piix_ide_init(void)
587 return ide_pci_register_driver(&driver);
590 module_init(piix_ide_init);
592 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
593 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
594 MODULE_LICENSE("GPL");