2 * linux/drivers/ide/pci/piix.c Version 0.46 December 3, 2006
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
7 * Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com>
9 * May be copied or modified under the terms of the GNU General Public License
11 * PIO mode setting function for Intel chipsets.
12 * For use instead of BIOS settings.
20 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
21 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
22 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
23 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
25 * sitre = word40 & 0x4000; primary
26 * sitre = word42 & 0x4000; secondary
28 * 44 8421|8421 hdd|hdb
30 * 48 8421 hdd|hdc|hdb|hda udma enabled
42 * ata-33/82801AB ata-66/82801AA
43 * 00|00 udma 0 00|00 reserved
44 * 01|01 udma 1 01|01 udma 3
45 * 10|10 udma 2 10|10 udma 4
46 * 11|11 reserved 11|11 reserved
48 * 54 8421|8421 ata66 drive|ata66 enable
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
52 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
53 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48);
54 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
55 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54);
58 * Publically available from Intel web site. Errata documentation
59 * is also publically available. As an aide to anyone hacking on this
60 * driver the list of errata that are relevant is below.going back to
61 * PIIX4. Older device documentation is now a bit tricky to find.
66 * PIIX4 errata #9 - Only on ultra obscure hw
67 * ICH3 errata #13 - Not observed to affect real hw
70 * Things we must deal with
71 * PIIX4 errata #10 - BM IDE hang with non UDMA
72 * (must stop/start dma to recover)
73 * 440MX errata #15 - As PIIX4 errata #10
74 * PIIX4 errata #15 - Must not read control registers
75 * during a PIO transfer
76 * 440MX errata #13 - As PIIX4 errata #15
77 * ICH2 errata #21 - DMA mode 0 doesn't work right
78 * ICH0/1 errata #55 - As ICH2 errata #21
79 * ICH2 spec c #9 - Extra operations needed to handle
80 * drive hotswap [NOT YET SUPPORTED]
81 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
82 * and must be dword aligned
83 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
85 * Should have been BIOS fixed:
86 * 450NX: errata #19 - DMA hangs on old 450NX
87 * 450NX: errata #20 - DMA hangs on old 450NX
88 * 450NX: errata #25 - Corruption with DMA on old 450NX
89 * ICH3 errata #15 - IDE deadlock under high load
90 * (BIOS must set dev 31 fn 0 bit 23)
91 * ICH3 errata #18 - Don't use native mode
94 #include <linux/types.h>
95 #include <linux/module.h>
96 #include <linux/kernel.h>
97 #include <linux/ioport.h>
98 #include <linux/pci.h>
99 #include <linux/hdreg.h>
100 #include <linux/ide.h>
101 #include <linux/delay.h>
102 #include <linux/init.h>
106 static int no_piix_dma;
109 * piix_ratemask - compute rate mask for PIIX IDE
110 * @drive: IDE drive to compute for
112 * Returns the available modes for the PIIX IDE controller.
115 static u8 piix_ratemask (ide_drive_t *drive)
117 struct pci_dev *dev = HWIF(drive)->pci_dev;
120 switch(dev->device) {
121 case PCI_DEVICE_ID_INTEL_82801EB_1:
124 /* UDMA 100 capable */
125 case PCI_DEVICE_ID_INTEL_82801BA_8:
126 case PCI_DEVICE_ID_INTEL_82801BA_9:
127 case PCI_DEVICE_ID_INTEL_82801CA_10:
128 case PCI_DEVICE_ID_INTEL_82801CA_11:
129 case PCI_DEVICE_ID_INTEL_82801E_11:
130 case PCI_DEVICE_ID_INTEL_82801DB_1:
131 case PCI_DEVICE_ID_INTEL_82801DB_10:
132 case PCI_DEVICE_ID_INTEL_82801DB_11:
133 case PCI_DEVICE_ID_INTEL_82801EB_11:
134 case PCI_DEVICE_ID_INTEL_ESB_2:
135 case PCI_DEVICE_ID_INTEL_ICH6_19:
136 case PCI_DEVICE_ID_INTEL_ICH7_21:
137 case PCI_DEVICE_ID_INTEL_ESB2_18:
138 case PCI_DEVICE_ID_INTEL_ICH8_6:
141 /* UDMA 66 capable */
142 case PCI_DEVICE_ID_INTEL_82801AA_1:
143 case PCI_DEVICE_ID_INTEL_82372FB_1:
146 /* UDMA 33 capable */
147 case PCI_DEVICE_ID_INTEL_82371AB:
148 case PCI_DEVICE_ID_INTEL_82443MX_1:
149 case PCI_DEVICE_ID_INTEL_82451NX:
150 case PCI_DEVICE_ID_INTEL_82801AB_1:
152 /* Non UDMA capable (MWDMA2) */
153 case PCI_DEVICE_ID_INTEL_82371SB_1:
154 case PCI_DEVICE_ID_INTEL_82371FB_1:
155 case PCI_DEVICE_ID_INTEL_82371FB_0:
156 case PCI_DEVICE_ID_INTEL_82371MX:
162 * If we are UDMA66 capable fall back to UDMA33
163 * if the drive cannot see an 80pin cable.
165 if (!eighty_ninty_three(drive))
166 mode = min_t(u8, mode, 1);
171 * piix_dma_2_pio - return the PIO mode matching DMA
172 * @xfer_rate: transfer speed
174 * Returns the nearest equivalent PIO timing for the PIO or DMA
175 * mode requested by the controller.
178 static u8 piix_dma_2_pio (u8 xfer_rate) {
208 * piix_tune_drive - tune a drive attached to a PIIX
209 * @drive: drive to tune
210 * @pio: desired PIO mode
212 * Set the interface PIO mode based upon the settings done by AMI BIOS
213 * (might be useful if drive is not registered in CMOS for any reason).
215 static void piix_tune_drive (ide_drive_t *drive, u8 pio)
217 ide_hwif_t *hwif = HWIF(drive);
218 struct pci_dev *dev = hwif->pci_dev;
219 int is_slave = drive->dn & 1;
220 int master_port = hwif->channel ? 0x42 : 0x40;
221 int slave_port = 0x44;
225 static DEFINE_SPINLOCK(tune_lock);
229 static const u8 timings[][2]= {
236 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
239 * Master vs slave is synchronized above us but the slave register is
240 * shared by the two hwifs so the corner case of two slave timeouts in
241 * parallel must be locked.
243 spin_lock_irqsave(&tune_lock, flags);
244 pci_read_config_word(dev, master_port, &master_data);
247 control |= 1; /* Programmable timing on */
248 if (drive->media == ide_disk)
249 control |= 4; /* Prefetch, post write */
251 control |= 2; /* IORDY */
253 master_data |= 0x4000;
254 master_data &= ~0x0070;
256 /* enable PPE, IE and TIME */
257 master_data = master_data | (control << 4);
259 pci_read_config_byte(dev, slave_port, &slave_data);
260 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
261 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
263 master_data &= ~0x3307;
265 /* enable PPE, IE and TIME */
266 master_data = master_data | control;
268 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
270 pci_write_config_word(dev, master_port, master_data);
272 pci_write_config_byte(dev, slave_port, slave_data);
273 spin_unlock_irqrestore(&tune_lock, flags);
277 * piix_tune_chipset - tune a PIIX interface
278 * @drive: IDE drive to tune
279 * @xferspeed: speed to configure
281 * Set a PIIX interface channel to the desired speeds. This involves
282 * requires the right timing data into the PIIX configuration space
283 * then setting the drive parameters appropriately
286 static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
288 ide_hwif_t *hwif = HWIF(drive);
289 struct pci_dev *dev = hwif->pci_dev;
290 u8 maslave = hwif->channel ? 0x42 : 0x40;
291 u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed);
292 int a_speed = 3 << (drive->dn * 4);
293 int u_flag = 1 << drive->dn;
294 int v_flag = 0x01 << drive->dn;
295 int w_flag = 0x10 << drive->dn;
299 u8 reg48, reg54, reg55;
301 pci_read_config_word(dev, maslave, ®4042);
302 sitre = (reg4042 & 0x4000) ? 1 : 0;
303 pci_read_config_byte(dev, 0x48, ®48);
304 pci_read_config_word(dev, 0x4a, ®4a);
305 pci_read_config_byte(dev, 0x54, ®54);
306 pci_read_config_byte(dev, 0x55, ®55);
310 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
313 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
314 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
317 case XFER_SW_DMA_2: break;
321 case XFER_PIO_0: break;
325 if (speed >= XFER_UDMA_0) {
326 if (!(reg48 & u_flag))
327 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
328 if (speed == XFER_UDMA_5) {
329 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
331 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
333 if ((reg4a & a_speed) != u_speed)
334 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
335 if (speed > XFER_UDMA_2) {
336 if (!(reg54 & v_flag))
337 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
339 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
342 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
344 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
346 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
348 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
351 piix_tune_drive(drive, piix_dma_2_pio(speed));
352 return (ide_config_drive_speed(drive, speed));
356 * piix_config_drive_for_dma - configure drive for DMA
357 * @drive: IDE drive to configure
359 * Set up a PIIX interface channel for the best available speed.
360 * We prefer UDMA if it is available and then MWDMA. If DMA is
361 * not available we switch to PIO and return 0.
364 static int piix_config_drive_for_dma (ide_drive_t *drive)
366 u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
369 * If no DMA speed was available or the chipset has DMA bugs
370 * then disable DMA and use PIO
375 (void) piix_tune_chipset(drive, speed);
376 return ide_dma_enable(drive);
380 * piix_config_drive_xfer_rate - set up an IDE device
381 * @drive: IDE drive to configure
383 * Set up the PIIX interface for the best available speed on this
384 * interface, preferring DMA to PIO.
387 static int piix_config_drive_xfer_rate (ide_drive_t *drive)
389 ide_hwif_t *hwif = HWIF(drive);
391 drive->init_speed = 0;
393 if (ide_use_dma(drive) && piix_config_drive_for_dma(drive))
394 return hwif->ide_dma_on(drive);
396 if (ide_use_fast_pio(drive))
397 /* Find best PIO mode. */
398 (void) hwif->speedproc(drive, XFER_PIO_0 +
399 ide_get_best_pio_mode(drive, 255, 4, NULL));
401 return hwif->ide_dma_off_quietly(drive);
405 * piix_is_ichx - check if ICHx
406 * @dev: PCI device to check
408 * returns 1 if ICHx, 0 otherwise.
410 static int piix_is_ichx(struct pci_dev *dev)
412 switch (dev->device) {
413 case PCI_DEVICE_ID_INTEL_82801EB_1:
414 case PCI_DEVICE_ID_INTEL_82801AA_1:
415 case PCI_DEVICE_ID_INTEL_82801AB_1:
416 case PCI_DEVICE_ID_INTEL_82801BA_8:
417 case PCI_DEVICE_ID_INTEL_82801BA_9:
418 case PCI_DEVICE_ID_INTEL_82801CA_10:
419 case PCI_DEVICE_ID_INTEL_82801CA_11:
420 case PCI_DEVICE_ID_INTEL_82801DB_1:
421 case PCI_DEVICE_ID_INTEL_82801DB_10:
422 case PCI_DEVICE_ID_INTEL_82801DB_11:
423 case PCI_DEVICE_ID_INTEL_82801EB_11:
424 case PCI_DEVICE_ID_INTEL_82801E_11:
425 case PCI_DEVICE_ID_INTEL_ESB_2:
426 case PCI_DEVICE_ID_INTEL_ICH6_19:
427 case PCI_DEVICE_ID_INTEL_ICH7_21:
428 case PCI_DEVICE_ID_INTEL_ESB2_18:
429 case PCI_DEVICE_ID_INTEL_ICH8_6:
437 * init_chipset_piix - set up the PIIX chipset
438 * @dev: PCI device to set up
439 * @name: Name of the device
441 * Initialize the PCI device as required. For the PIIX this turns
442 * out to be nice and simple
445 static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
447 if (piix_is_ichx(dev)) {
448 unsigned int extra = 0;
449 pci_read_config_dword(dev, 0x54, &extra);
450 pci_write_config_dword(dev, 0x54, extra|0x400);
457 * piix_dma_clear_irq - clear BMDMA status
458 * @drive: IDE drive to clear
460 * Called from ide_intr() for PIO interrupts
461 * to clear BMDMA status as needed by ICHx
463 static void piix_dma_clear_irq(ide_drive_t *drive)
465 ide_hwif_t *hwif = HWIF(drive);
468 /* clear the INTR & ERROR bits */
469 dma_stat = hwif->INB(hwif->dma_status);
470 /* Should we force the bit as well ? */
471 hwif->OUTB(dma_stat, hwif->dma_status);
474 static int __devinit piix_cable_detect(ide_hwif_t *hwif)
476 struct pci_dev *dev = hwif->pci_dev;
477 u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
479 pci_read_config_byte(dev, 0x54, ®54h);
481 return (reg54h & mask) ? 1 : 0;
485 * init_hwif_piix - fill in the hwif for the PIIX
486 * @hwif: IDE interface
488 * Set up the ide_hwif_t for the PIIX interface according to the
489 * capabilities of the hardware.
492 static void __devinit init_hwif_piix(ide_hwif_t *hwif)
496 hwif->irq = hwif->channel ? 15 : 14;
497 #endif /* CONFIG_IA64 */
499 if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
500 /* This is a painful system best to let it self tune for now */
505 hwif->tuneproc = &piix_tune_drive;
506 hwif->speedproc = &piix_tune_chipset;
507 hwif->drives[0].autotune = 1;
508 hwif->drives[1].autotune = 1;
513 /* ICHx need to clear the bmdma status for all interrupts */
514 if (piix_is_ichx(hwif->pci_dev))
515 hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
518 hwif->ultra_mask = 0x3f;
519 hwif->mwdma_mask = 0x06;
520 hwif->swdma_mask = 0x04;
522 switch(hwif->pci_dev->device) {
523 case PCI_DEVICE_ID_INTEL_82371FB_0:
524 case PCI_DEVICE_ID_INTEL_82371FB_1:
525 case PCI_DEVICE_ID_INTEL_82371SB_1:
526 hwif->ultra_mask = 0x80;
528 case PCI_DEVICE_ID_INTEL_82371AB:
529 case PCI_DEVICE_ID_INTEL_82443MX_1:
530 case PCI_DEVICE_ID_INTEL_82451NX:
531 case PCI_DEVICE_ID_INTEL_82801AB_1:
532 hwif->ultra_mask = 0x07;
535 if (!hwif->udma_four)
536 hwif->udma_four = piix_cable_detect(hwif);
541 hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
543 hwif->ide_dma_check = &piix_config_drive_xfer_rate;
547 hwif->drives[1].autodma = hwif->autodma;
548 hwif->drives[0].autodma = hwif->autodma;
551 #define DECLARE_PIIX_DEV(name_str) \
554 .init_chipset = init_chipset_piix, \
555 .init_hwif = init_hwif_piix, \
557 .autodma = AUTODMA, \
558 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
559 .bootable = ON_BOARD, \
562 static ide_pci_device_t piix_pci_info[] __devinitdata = {
563 /* 0 */ DECLARE_PIIX_DEV("PIIXa"),
564 /* 1 */ DECLARE_PIIX_DEV("PIIXb"),
568 * MPIIX actually has only a single IDE channel mapped to
569 * the primary or secondary ports depending on the value
570 * of the bit 14 of the IDETIM register at offset 0x6c
573 .init_hwif = init_hwif_piix,
576 .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
577 .bootable = ON_BOARD,
578 .flags = IDEPCI_FLAG_ISA_PORTS
581 /* 3 */ DECLARE_PIIX_DEV("PIIX3"),
582 /* 4 */ DECLARE_PIIX_DEV("PIIX4"),
583 /* 5 */ DECLARE_PIIX_DEV("ICH0"),
584 /* 6 */ DECLARE_PIIX_DEV("PIIX4"),
585 /* 7 */ DECLARE_PIIX_DEV("ICH"),
586 /* 8 */ DECLARE_PIIX_DEV("PIIX4"),
587 /* 9 */ DECLARE_PIIX_DEV("PIIX4"),
588 /* 10 */ DECLARE_PIIX_DEV("ICH2"),
589 /* 11 */ DECLARE_PIIX_DEV("ICH2M"),
590 /* 12 */ DECLARE_PIIX_DEV("ICH3M"),
591 /* 13 */ DECLARE_PIIX_DEV("ICH3"),
592 /* 14 */ DECLARE_PIIX_DEV("ICH4"),
593 /* 15 */ DECLARE_PIIX_DEV("ICH5"),
594 /* 16 */ DECLARE_PIIX_DEV("C-ICH"),
595 /* 17 */ DECLARE_PIIX_DEV("ICH4"),
596 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"),
597 /* 19 */ DECLARE_PIIX_DEV("ICH5"),
598 /* 20 */ DECLARE_PIIX_DEV("ICH6"),
599 /* 21 */ DECLARE_PIIX_DEV("ICH7"),
600 /* 22 */ DECLARE_PIIX_DEV("ICH4"),
601 /* 23 */ DECLARE_PIIX_DEV("ESB2"),
602 /* 24 */ DECLARE_PIIX_DEV("ICH8M"),
606 * piix_init_one - called when a PIIX is found
607 * @dev: the piix device
608 * @id: the matching pci id
610 * Called when the PCI registration layer (or the IDE initialization)
611 * finds a device matching our IDE device tables.
614 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
616 ide_pci_device_t *d = &piix_pci_info[id->driver_data];
618 return ide_setup_pci_device(dev, d);
622 * piix_check_450nx - Check for problem 450NX setup
624 * Check for the present of 450NX errata #19 and errata #25. If
625 * they are found, disable use of DMA IDE
628 static void __devinit piix_check_450nx(void)
630 struct pci_dev *pdev = NULL;
633 while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
635 /* Look for 450NX PXB. Check for problem configurations
636 A PCI quirk checks bit 6 already */
637 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
638 pci_read_config_word(pdev, 0x41, &cfg);
639 /* Only on the original revision: IDE DMA can hang */
642 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
643 else if(cfg & (1<<14) && rev < 5)
647 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
649 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
652 static struct pci_device_id piix_pci_tbl[] = {
653 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
654 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
655 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
656 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
657 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
658 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
659 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
660 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
661 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
662 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
663 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
664 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
665 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
666 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
667 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
668 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
669 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
670 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
671 #ifdef CONFIG_BLK_DEV_IDE_SATA
672 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
674 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
675 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
676 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
677 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22},
678 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23},
679 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24},
682 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
684 static struct pci_driver driver = {
686 .id_table = piix_pci_tbl,
687 .probe = piix_init_one,
690 static int __init piix_ide_init(void)
693 return ide_pci_register_driver(&driver);
696 module_init(piix_ide_init);
698 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
699 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
700 MODULE_LICENSE("GPL");