2 * linux/drivers/ide/pci/sl82c105.c
4 * SL82C105/Winbond 553 IDE driver
8 * Drive tuning added from Rebel.com's kernel sources
9 * -- Russell King (15/11/98) linux@arm.linux.org.uk
11 * Merge in Russell's HW workarounds, fix various problems
12 * with the timing registers setup.
13 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
15 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
18 #include <linux/types.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/timer.h>
23 #include <linux/ioport.h>
24 #include <linux/interrupt.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/pci.h>
28 #include <linux/ide.h>
36 #define DBG(arg) printk arg
41 * SL82C105 PCI config register 0x40 bits.
43 #define CTRL_IDE_IRQB (1 << 30)
44 #define CTRL_IDE_IRQA (1 << 28)
45 #define CTRL_LEGIRQ (1 << 11)
46 #define CTRL_P1F16 (1 << 5)
47 #define CTRL_P1EN (1 << 4)
48 #define CTRL_P0F16 (1 << 1)
49 #define CTRL_P0EN (1 << 0)
52 * Convert a PIO mode and cycle time to the required on/off times
53 * for the interface. This has protection against runaway timings.
55 static unsigned int get_pio_timings(ide_pio_data_t *p)
57 unsigned int cmd_on, cmd_off;
59 cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
60 cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
68 return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00);
72 * Configure the chipset for PIO mode.
74 static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio)
76 struct pci_dev *dev = HWIF(drive)->pci_dev;
77 int reg = 0x44 + drive->dn * 4;
81 DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio));
83 pio = ide_get_best_pio_mode(drive, pio, 5, &p);
85 drive->drive_data = drv_ctrl = get_pio_timings(&p);
87 if (!drive->using_dma) {
89 * If we are actually using MW DMA, then we can not
90 * reprogram the interface drive control register.
92 pci_write_config_word(dev, reg, drv_ctrl);
93 pci_read_config_word (dev, reg, &drv_ctrl);
96 printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
97 ide_xfer_verbose(pio + XFER_PIO_0), p.cycle_time, drv_ctrl);
103 * Configure the drive and the chipset for DMA
105 static int config_for_dma (ide_drive_t *drive)
107 ide_hwif_t *hwif = HWIF(drive);
108 struct pci_dev *dev = hwif->pci_dev;
111 DBG(("config_for_dma(drive:%s)\n", drive->name));
113 reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
115 if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0)
118 pci_write_config_word(dev, reg, 0x0240);
124 * Check to see if the drive and
125 * chipset is capable of DMA mode
128 static int sl82c105_check_drive (ide_drive_t *drive)
130 ide_hwif_t *hwif = HWIF(drive);
132 DBG(("sl82c105_check_drive(drive:%s)\n", drive->name));
135 struct hd_driveid *id = drive->id;
140 if (!id || !(id->capability & 1))
143 /* Consult the list of known "bad" drives */
144 if (__ide_dma_bad_drive(drive))
147 if (id->field_valid & 2) {
148 if ((id->dma_mword & hwif->mwdma_mask) ||
149 (id->dma_1word & hwif->swdma_mask))
153 if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150)
161 * The SL82C105 holds off all IDE interrupts while in DMA mode until
162 * all DMA activity is completed. Sometimes this causes problems (eg,
163 * when the drive wants to report an error condition).
165 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
166 * state machine. We need to kick this to work around various bugs.
168 static inline void sl82c105_reset_host(struct pci_dev *dev)
172 pci_read_config_word(dev, 0x7e, &val);
173 pci_write_config_word(dev, 0x7e, val | (1 << 2));
174 pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
178 * If we get an IRQ timeout, it might be that the DMA state machine
179 * got confused. Fix from Todd Inglett. Details from Winbond.
181 * This function is called when the IDE timer expires, the drive
182 * indicates that it is READY, and we were waiting for DMA to complete.
184 static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive)
186 ide_hwif_t *hwif = HWIF(drive);
187 struct pci_dev *dev = hwif->pci_dev;
188 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
189 unsigned long dma_base = hwif->dma_base;
191 printk("sl82c105: lost IRQ: resetting host\n");
194 * Check the raw interrupt from the drive.
196 pci_read_config_dword(dev, 0x40, &val);
198 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
201 * Was DMA enabled? If so, disable it - we're resetting the
202 * host. The IDE layer will be handling the drive for us.
206 outb(val & ~1, dma_base);
207 printk("sl82c105: DMA was enabled\n");
210 sl82c105_reset_host(dev);
212 /* ide_dmaproc would return 1, so we do as well */
217 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
218 * Winbond recommend that the DMA state machine is reset prior to
219 * setting the bus master DMA enable bit.
221 * The generic IDE core will have disabled the BMEN bit before this
222 * function is called.
224 static void sl82c105_ide_dma_start(ide_drive_t *drive)
226 ide_hwif_t *hwif = HWIF(drive);
227 struct pci_dev *dev = hwif->pci_dev;
229 sl82c105_reset_host(dev);
230 ide_dma_start(drive);
233 static int sl82c105_ide_dma_timeout(ide_drive_t *drive)
235 ide_hwif_t *hwif = HWIF(drive);
236 struct pci_dev *dev = hwif->pci_dev;
238 DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name));
240 sl82c105_reset_host(dev);
241 return __ide_dma_timeout(drive);
244 static int sl82c105_ide_dma_on (ide_drive_t *drive)
246 DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
248 if (config_for_dma(drive))
250 printk(KERN_INFO "%s: DMA enabled\n", drive->name);
251 return __ide_dma_on(drive);
254 static void sl82c105_dma_off_quietly(ide_drive_t *drive)
256 struct pci_dev *dev = HWIF(drive)->pci_dev;
257 int reg = 0x44 + drive->dn * 4;
259 DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
261 pci_write_config_word(dev, reg, drive->drive_data);
263 ide_dma_off_quietly(drive);
267 * Ok, that is nasty, but we must make sure the DMA timings
268 * won't be used for a PIO access. The solution here is
269 * to make sure the 16 bits mode is diabled on the channel
270 * when DMA is enabled, thus causing the chip to use PIO0
271 * timings for those operations.
273 static void sl82c105_selectproc(ide_drive_t *drive)
275 ide_hwif_t *hwif = HWIF(drive);
276 struct pci_dev *dev = hwif->pci_dev;
279 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
281 mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
282 old = val = (u32)pci_get_drvdata(dev);
283 if (drive->using_dma)
288 pci_write_config_dword(dev, 0x40, val);
289 pci_set_drvdata(dev, (void *)val);
294 * ATA reset will clear the 16 bits mode in the control
295 * register, we need to update our cache
297 static void sl82c105_resetproc(ide_drive_t *drive)
299 struct pci_dev *dev = HWIF(drive)->pci_dev;
302 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
304 pci_read_config_dword(dev, 0x40, &val);
305 pci_set_drvdata(dev, (void *)val);
309 * We only deal with PIO mode here - DMA mode 'using_dma' is not
310 * initialised at the point that this function is called.
312 static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
314 DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio));
316 pio = sl82c105_tune_pio(drive, pio);
317 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
321 * Return the revision of the Winbond bridge
322 * which this function is part of.
324 static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
326 struct pci_dev *bridge;
330 * The bridge should be part of the same device, but function 0.
332 bridge = pci_find_slot(dev->bus->number,
333 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
338 * Make sure it is a Winbond 553 and is an ISA bridge.
340 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
341 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
342 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA)
346 * We need to find function 0's revision, not function 1
348 pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
354 * Enable the PCI device
356 * --BenH: It's arch fixup code that should enable channels that
357 * have not been enabled by firmware. I decided we can still enable
358 * channel 0 here at least, but channel 1 has to be enabled by
359 * firmware or arch code. We still set both to 16 bits mode.
361 static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
365 DBG(("init_chipset_sl82c105()\n"));
367 pci_read_config_dword(dev, 0x40, &val);
368 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
369 pci_write_config_dword(dev, 0x40, val);
370 pci_set_drvdata(dev, (void *)val);
376 * Initialise the chip
378 static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
382 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
384 hwif->tuneproc = &sl82c105_tune_drive;
385 hwif->selectproc = &sl82c105_selectproc;
386 hwif->resetproc = &sl82c105_resetproc;
389 * We support 32-bit I/O on this interface, and
390 * it doesn't have problems with interrupts.
392 hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
393 hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
396 * We always autotune PIO, this is done before DMA is checked,
397 * so there's no risk of accidentally disabling DMA
399 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
402 hwif->mwdma_mask = 0;
403 hwif->swdma_mask = 0;
409 rev = sl82c105_bridge_revision(hwif->pci_dev);
412 * Never ever EVER under any circumstances enable
413 * DMA when the bridge is this old.
415 printk(" %s: Winbond 553 bridge revision %d, BM-DMA disabled\n",
419 hwif->mwdma_mask = 0x04;
421 hwif->ide_dma_check = &sl82c105_check_drive;
422 hwif->ide_dma_on = &sl82c105_ide_dma_on;
423 hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
424 hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq;
425 hwif->dma_start = &sl82c105_ide_dma_start;
426 hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;
430 hwif->drives[0].autodma = hwif->autodma;
431 hwif->drives[1].autodma = hwif->autodma;
434 hwif->serialized = hwif->mate->serialized = 1;
438 static ide_pci_device_t sl82c105_chipset __devinitdata = {
440 .init_chipset = init_chipset_sl82c105,
441 .init_hwif = init_hwif_sl82c105,
443 .autodma = NOAUTODMA,
444 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
445 .bootable = ON_BOARD,
448 static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
450 return ide_setup_pci_device(dev, &sl82c105_chipset);
453 static struct pci_device_id sl82c105_pci_tbl[] = {
454 { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
457 MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
459 static struct pci_driver driver = {
460 .name = "W82C105_IDE",
461 .id_table = sl82c105_pci_tbl,
462 .probe = sl82c105_init_one,
465 static int __init sl82c105_ide_init(void)
467 return ide_pci_register_driver(&driver);
470 module_init(sl82c105_ide_init);
472 MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
473 MODULE_LICENSE("GPL");