drivers/ide/pdc202xx_old.c

   1 /*
   2  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   3  *  Copyright (C) 2006-2007, 2009       MontaVista Software, Inc.
   4  *  Copyright (C) 2007-2010             Bartlomiej Zolnierkiewicz
   5  *
   6  *  Portions Copyright (C) 1999 Promise Technology, Inc.
   7  *  Author: Frank Tiernan (frankt@promise.com)
   8  *  Released under terms of General Public License
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/delay.h>
  15 #include <linux/blkdev.h>
  16 #include <linux/pci.h>
  17 #include <linux/init.h>
  18 #include <linux/ide.h>
  19
  20 #include <asm/io.h>
  21
  22 #define DRV_NAME "pdc202xx_old"
  23
  24 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
  25 {
  26         ide_hwif_t *hwif        = drive->hwif;
  27         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  28         u8 drive_pci            = 0x60 + (drive->dn << 2);
  29
  30         u8                      AP = 0, BP = 0, CP = 0;
  31         u8                      TA = 0, TB = 0, TC = 0;
  32
  33         pci_read_config_byte(dev, drive_pci,     &AP);
  34         pci_read_config_byte(dev, drive_pci + 1, &BP);
  35         pci_read_config_byte(dev, drive_pci + 2, &CP);
  36
  37         switch(speed) {
  38                 case XFER_UDMA_5:
  39                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
  40                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
  41                 case XFER_UDMA_3:
  42                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
  43                 case XFER_UDMA_0:
  44                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
  45                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
  46                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
  47                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
  48                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
  49                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
  50                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
  51                 case XFER_PIO_0:
  52                 default:                TA = 0x09; TB = 0x13; break;
  53         }
  54
  55         if (speed < XFER_SW_DMA_0) {
  56                 /*
  57                  * preserve SYNC_INT / ERDDY_EN bits while clearing
  58                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
  59                  */
  60                 AP &= ~0x3f;
  61                 if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
  62                         AP |= 0x20;     /* set IORDY_EN bit */
  63                 if (drive->media == ide_disk)
  64                         AP |= 0x10;     /* set Prefetch_EN bit */
  65                 /* clear PB[4:0] bits of register B */
  66                 BP &= ~0x1f;
  67                 pci_write_config_byte(dev, drive_pci,     AP | TA);
  68                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
  69         } else {
  70                 /* clear MB[2:0] bits of register B */
  71                 BP &= ~0xe0;
  72                 /* clear MC[3:0] bits of register C */
  73                 CP &= ~0x0f;
  74                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
  75                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
  76         }
  77 }
  78
  79 static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  80 {
  81         pdc202xx_set_mode(drive, drive->pio_mode);
  82 }
  83
  84 static int pdc202xx_test_irq(ide_hwif_t *hwif)
  85 {
  86         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  87         unsigned long high_16   = pci_resource_start(dev, 4);
  88         u8 sc1d                 = inb(high_16 + 0x1d);
  89
  90         if (hwif->channel) {
  91                 /*
  92                  * bit 7: error, bit 6: interrupting,
  93                  * bit 5: FIFO full, bit 4: FIFO empty
  94                  */
  95                 return ((sc1d & 0x50) == 0x40) ? 1 : 0;
  96         } else  {
  97                 /*
  98                  * bit 3: error, bit 2: interrupting,
  99                  * bit 1: FIFO full, bit 0: FIFO empty
 100                  */
 101                 return ((sc1d & 0x05) == 0x04) ? 1 : 0;
 102         }
 103 }
 104
 105 static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
 106 {
 107         struct pci_dev *dev = to_pci_dev(hwif->dev);
 108         u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
 109
 110         pci_read_config_word(dev, 0x50, &CIS);
 111
 112         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 113 }
 114
 115 /*
 116  * Set the control register to use the 66MHz system
 117  * clock for UDMA 3/4/5 mode operation when necessary.
 118  *
 119  * FIXME: this register is shared by both channels, some locking is needed
 120  *
 121  * It may also be possible to leave the 66MHz clock on
 122  * and readjust the timing parameters.
 123  */
 124 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 125 {
 126         unsigned long clock_reg = hwif->extra_base + 0x01;
 127         u8 clock = inb(clock_reg);
 128
 129         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 130 }
 131
 132 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 133 {
 134         unsigned long clock_reg = hwif->extra_base + 0x01;
 135         u8 clock = inb(clock_reg);
 136
 137         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 138 }
 139
 140 static void pdc2026x_init_hwif(ide_hwif_t *hwif)
 141 {
 142         pdc_old_disable_66MHz_clock(hwif);
 143 }
 144
 145 static void pdc202xx_dma_start(ide_drive_t *drive)
 146 {
 147         if (drive->current_speed > XFER_UDMA_2)
 148                 pdc_old_enable_66MHz_clock(drive->hwif);
 149         if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
 150                 ide_hwif_t *hwif        = drive->hwif;
 151                 struct request *rq      = hwif->rq;
 152                 unsigned long high_16   = hwif->extra_base - 16;
 153                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 154                 u32 word_count  = 0;
 155                 u8 clock = inb(high_16 + 0x11);
 156
 157                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 158                 word_count = (blk_rq_sectors(rq) << 8);
 159                 word_count = (rq_data_dir(rq) == READ) ?
 160                                         word_count | 0x05000000 :
 161                                         word_count | 0x06000000;
 162                 outl(word_count, atapi_reg);
 163         }
 164         ide_dma_start(drive);
 165 }
 166
 167 static int pdc202xx_dma_end(ide_drive_t *drive)
 168 {
 169         if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
 170                 ide_hwif_t *hwif        = drive->hwif;
 171                 unsigned long high_16   = hwif->extra_base - 16;
 172                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 173                 u8 clock                = 0;
 174
 175                 outl(0, atapi_reg); /* zero out extra */
 176                 clock = inb(high_16 + 0x11);
 177                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 178         }
 179         if (drive->current_speed > XFER_UDMA_2)
 180                 pdc_old_disable_66MHz_clock(drive->hwif);
 181         return ide_dma_end(drive);
 182 }
 183
 184 static int init_chipset_pdc202xx(struct pci_dev *dev)
 185 {
 186         unsigned long dmabase = pci_resource_start(dev, 4);
 187         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 188
 189         if (dmabase == 0)
 190                 goto out;
 191
 192         udma_speed_flag = inb(dmabase | 0x1f);
 193         primary_mode    = inb(dmabase | 0x1a);
 194         secondary_mode  = inb(dmabase | 0x1b);
 195         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 196                 "Primary %s Mode " \
 197                 "Secondary %s Mode.\n", pci_name(dev),
 198                 (udma_speed_flag & 1) ? "EN" : "DIS",
 199                 (primary_mode & 1) ? "MASTER" : "PCI",
 200                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 201
 202         if (!(udma_speed_flag & 1)) {
 203                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 204                         pci_name(dev), udma_speed_flag,
 205                         (udma_speed_flag|1));
 206                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 207                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 208         }
 209 out:
 210         return 0;
 211 }
 212
 213 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
 214                                            const char *name)
 215 {
 216         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 217                 u8 irq = 0, irq2 = 0;
 218                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 219                 /* 0xbc */
 220                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 221                 if (irq != irq2) {
 222                         pci_write_config_byte(dev,
 223                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 224                         printk(KERN_INFO "%s %s: PCI config space interrupt "
 225                                 "mirror fixed\n", name, pci_name(dev));
 226                 }
 227         }
 228 }
 229
 230 #define IDE_HFLAGS_PDC202XX \
 231         (IDE_HFLAG_ERROR_STOPS_FIFO | \
 232          IDE_HFLAG_OFF_BOARD)
 233
 234 static const struct ide_port_ops pdc20246_port_ops = {
 235         .set_pio_mode           = pdc202xx_set_pio_mode,
 236         .set_dma_mode           = pdc202xx_set_mode,
 237         .test_irq               = pdc202xx_test_irq,
 238 };
 239
 240 static const struct ide_port_ops pdc2026x_port_ops = {
 241         .set_pio_mode           = pdc202xx_set_pio_mode,
 242         .set_dma_mode           = pdc202xx_set_mode,
 243         .cable_detect           = pdc2026x_cable_detect,
 244 };
 245
 246 static const struct ide_dma_ops pdc2026x_dma_ops = {
 247         .dma_host_set           = ide_dma_host_set,
 248         .dma_setup              = ide_dma_setup,
 249         .dma_start              = pdc202xx_dma_start,
 250         .dma_end                = pdc202xx_dma_end,
 251         .dma_test_irq           = ide_dma_test_irq,
 252         .dma_lost_irq           = ide_dma_lost_irq,
 253         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 254         .dma_sff_read_status    = ide_dma_sff_read_status,
 255 };
 256
 257 #define DECLARE_PDC2026X_DEV(udma, sectors) \
 258         { \
 259                 .name           = DRV_NAME, \
 260                 .init_chipset   = init_chipset_pdc202xx, \
 261                 .init_hwif      = pdc2026x_init_hwif, \
 262                 .port_ops       = &pdc2026x_port_ops, \
 263                 .dma_ops        = &pdc2026x_dma_ops, \
 264                 .host_flags     = IDE_HFLAGS_PDC202XX, \
 265                 .pio_mask       = ATA_PIO4, \
 266                 .mwdma_mask     = ATA_MWDMA2, \
 267                 .udma_mask      = udma, \
 268                 .max_sectors    = sectors, \
 269         }
 270
 271 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
 272         {       /* 0: PDC20246 */
 273                 .name           = DRV_NAME,
 274                 .init_chipset   = init_chipset_pdc202xx,
 275                 .port_ops       = &pdc20246_port_ops,
 276                 .dma_ops        = &sff_dma_ops,
 277                 .host_flags     = IDE_HFLAGS_PDC202XX,
 278                 .pio_mask       = ATA_PIO4,
 279                 .mwdma_mask     = ATA_MWDMA2,
 280                 .udma_mask      = ATA_UDMA2,
 281         },
 282
 283         /* 1: PDC2026{2,3} */
 284         DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
 285         /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
 286         DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
 287 };
 288
 289 /**
 290  *      pdc202xx_init_one       -       called when a PDC202xx is found
 291  *      @dev: the pdc202xx device
 292  *      @id: the matching pci id
 293  *
 294  *      Called when the PCI registration layer (or the IDE initialization)
 295  *      finds a device matching our IDE device tables.
 296  */
 297
 298 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 299 {
 300         const struct ide_port_info *d;
 301         u8 idx = id->driver_data;
 302
 303         d = &pdc202xx_chipsets[idx];
 304
 305         if (idx < 2)
 306                 pdc202ata4_fixup_irq(dev, d->name);
 307
 308         if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
 309                 struct pci_dev *bridge = dev->bus->self;
 310
 311                 if (bridge &&
 312                     bridge->vendor == PCI_VENDOR_ID_INTEL &&
 313                     (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
 314                      bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
 315                         printk(KERN_INFO DRV_NAME " %s: skipping Promise "
 316                                 "PDC20265 attached to I2O RAID controller\n",
 317                                 pci_name(dev));
 318                         return -ENODEV;
 319                 }
 320         }
 321
 322         return ide_pci_init_one(dev, d, NULL);
 323 }
 324
 325 static const struct pci_device_id pdc202xx_pci_tbl[] = {
 326         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
 327         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
 328         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
 329         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
 330         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
 331         { 0, },
 332 };
 333 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 334
 335 static struct pci_driver pdc202xx_pci_driver = {
 336         .name           = "Promise_Old_IDE",
 337         .id_table       = pdc202xx_pci_tbl,
 338         .probe          = pdc202xx_init_one,
 339         .remove         = ide_pci_remove,
 340         .suspend        = ide_pci_suspend,
 341         .resume         = ide_pci_resume,
 342 };
 343
 344 static int __init pdc202xx_ide_init(void)
 345 {
 346         return ide_pci_register_driver(&pdc202xx_pci_driver);
 347 }
 348
 349 static void __exit pdc202xx_ide_exit(void)
 350 {
 351         pci_unregister_driver(&pdc202xx_pci_driver);
 352 }
 353
 354 module_init(pdc202xx_ide_init);
 355 module_exit(pdc202xx_ide_exit);
 356
 357 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz");
 358 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 359 MODULE_LICENSE("GPL");