2 * linux/drivers/ide/ppc/ide-m8xx.c
4 * Copyright (C) 2000, 2001 Wolfgang Denk, wd@denx.de
5 * Modified for direct IDE interface
6 * by Thomas Lange, thomas@corelatus.com
7 * Modified for direct IDE interface on 8xx without using the PCMCIA
9 * by Steven.Scholz@imc-berlin.de
10 * Moved out of arch/ppc/kernel/m8xx_setup.c, other minor cleanups
11 * by Mathew Locke <mattl@mvista.com>
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
17 #include <linux/stddef.h>
18 #include <linux/unistd.h>
19 #include <linux/ptrace.h>
20 #include <linux/slab.h>
21 #include <linux/user.h>
22 #include <linux/a.out.h>
23 #include <linux/tty.h>
24 #include <linux/major.h>
25 #include <linux/interrupt.h>
26 #include <linux/reboot.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/ide.h>
30 #include <linux/bootmem.h>
32 #include <asm/mpc8xx.h>
34 #include <asm/processor.h>
35 #include <asm/residual.h>
37 #include <asm/pgtable.h>
39 #include <asm/8xx_immap.h>
40 #include <asm/machdep.h>
43 static int identify (volatile u8 *p);
44 static void print_fixed (volatile u8 *p);
45 static void print_funcid (int func);
46 static int check_ide_device (unsigned long base);
48 static void ide_interrupt_ack (void *dev);
49 static void m8xx_ide_tuneproc(ide_drive_t *drive, u8 pio);
51 typedef struct ide_ioport_desc {
52 unsigned long base_off; /* Offset to PCMCIA memory */
53 unsigned long reg_off[IDE_NR_PORTS]; /* controller register offsets */
57 ide_ioport_desc_t ioport_dsc[MAX_HWIFS] = {
58 #ifdef IDE0_BASE_OFFSET
62 IDE0_ERROR_REG_OFFSET,
63 IDE0_NSECTOR_REG_OFFSET,
64 IDE0_SECTOR_REG_OFFSET,
67 IDE0_SELECT_REG_OFFSET,
68 IDE0_STATUS_REG_OFFSET,
69 IDE0_CONTROL_REG_OFFSET,
74 #ifdef IDE1_BASE_OFFSET
78 IDE1_ERROR_REG_OFFSET,
79 IDE1_NSECTOR_REG_OFFSET,
80 IDE1_SECTOR_REG_OFFSET,
83 IDE1_SELECT_REG_OFFSET,
84 IDE1_STATUS_REG_OFFSET,
85 IDE1_CONTROL_REG_OFFSET,
90 #endif /* IDE1_BASE_OFFSET */
91 #endif /* IDE0_BASE_OFFSET */
94 ide_pio_timings_t ide_pio_clocks[6];
95 int hold_time[6] = {30, 20, 15, 10, 10, 10 }; /* PIO Mode 5 with IORDY (nonstandard) */
98 * Warning: only 1 (ONE) PCMCIA slot supported here,
99 * which must be correctly initialized by the firmware (PPCBoot).
101 static int _slot_ = -1; /* will be read from PCMCIA registers */
103 /* Make clock cycles and always round up */
104 #define PCMCIA_MK_CLKS( t, T ) (( (t) * ((T)/1000000) + 999U ) / 1000U )
112 m8xx_ide_default_irq(unsigned long base)
114 #ifdef CONFIG_BLK_DEV_MPC8xx_IDE
115 if (base >= MAX_HWIFS)
118 printk("[%d] m8xx_ide_default_irq %d\n",__LINE__,ioport_dsc[base].irq);
120 return (ioport_dsc[base].irq);
127 m8xx_ide_default_io_base(int index)
132 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
133 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
136 * The TQM850L hardware has two pins swapped! Grrrrgh!
138 #ifdef CONFIG_TQM850L
139 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
140 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
142 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
143 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
146 #if defined(CONFIG_BLK_DEV_MPC8xx_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
147 #define PCMCIA_SCHLVL IDE0_INTERRUPT /* Status Change Interrupt Level */
148 static int pcmcia_schlvl = PCMCIA_SCHLVL;
152 * See include/linux/ide.h for definition of hw_regs_t (p, base)
156 * m8xx_ide_init_hwif_ports for a direct IDE interface _using_
158 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
160 m8xx_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
161 unsigned long ctrl_port, int *irq)
163 unsigned long *p = hw->io_ports;
170 volatile pcmcia_win_t *win;
171 volatile pcmconf8xx_t *pcmp;
176 static unsigned long pcmcia_base = 0;
183 pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
187 * Read out PCMCIA registers. Since the reset values
188 * are undefined, we sure hope that they have been
192 /* Scan all registers for valid settings */
193 pcmcia_phy_base = 0xFFFFFFFF;
195 /* br0 is start of brX and orX regs */
196 win = (pcmcia_win_t *) \
197 (&(((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0));
198 for (i = 0; i < 8; i++) {
199 if (win->or & 1) { /* This bank is marked as valid */
200 if (win->br < pcmcia_phy_base) {
201 pcmcia_phy_base = win->br;
203 if ((win->br + PCMCIA_MEM_SIZE) > pcmcia_phy_end) {
204 pcmcia_phy_end = win->br + PCMCIA_MEM_SIZE;
206 /* Check which slot that has been defined */
207 _slot_ = (win->or >> 2) & 1;
213 printk ("PCMCIA slot %c: phys mem %08x...%08x (size %08x)\n",
215 pcmcia_phy_base, pcmcia_phy_end,
216 pcmcia_phy_end - pcmcia_phy_base);
218 pcmcia_base=(unsigned long)ioremap(pcmcia_phy_base,
219 pcmcia_phy_end-pcmcia_phy_base);
222 printk ("PCMCIA virt base: %08lx\n", pcmcia_base);
224 /* Compute clock cycles for PIO timings */
225 for (i=0; i<6; ++i) {
226 bd_t *binfo = (bd_t *)__res;
229 PCMCIA_MK_CLKS (hold_time[i],
231 ide_pio_clocks[i].setup_time =
232 PCMCIA_MK_CLKS (ide_pio_timings[i].setup_time,
234 ide_pio_clocks[i].active_time =
235 PCMCIA_MK_CLKS (ide_pio_timings[i].active_time,
237 ide_pio_clocks[i].cycle_time =
238 PCMCIA_MK_CLKS (ide_pio_timings[i].cycle_time,
241 printk ("PIO mode %d timings: %d/%d/%d => %d/%d/%d\n",
243 ide_pio_clocks[i].setup_time,
244 ide_pio_clocks[i].active_time,
245 ide_pio_clocks[i].hold_time,
246 ide_pio_clocks[i].cycle_time,
247 ide_pio_timings[i].setup_time,
248 ide_pio_timings[i].active_time,
249 ide_pio_timings[i].hold_time,
250 ide_pio_timings[i].cycle_time);
255 if (data_port >= MAX_HWIFS)
259 printk ("PCMCIA slot has not been defined! Using A as default\n");
263 #ifdef CONFIG_IDE_8xx_PCCARD
266 printk ("PIPR = 0x%08X slot %c ==> mask = 0x%X\n",
269 M8XX_PCMCIA_CD1(_slot_) | M8XX_PCMCIA_CD2(_slot_) );
272 if (pcmp->pcmc_pipr & (M8XX_PCMCIA_CD1(_slot_)|M8XX_PCMCIA_CD2(_slot_))) {
273 printk ("No card in slot %c: PIPR=%08x\n",
274 'A' + _slot_, (u32) pcmp->pcmc_pipr);
275 return; /* No card in slot */
278 check_ide_device (pcmcia_base);
280 #endif /* CONFIG_IDE_8xx_PCCARD */
282 base = pcmcia_base + ioport_dsc[data_port].base_off;
284 printk ("base: %08x + %08x = %08x\n",
285 pcmcia_base, ioport_dsc[data_port].base_off, base);
288 for (i = 0; i < IDE_NR_PORTS; ++i) {
290 printk ("port[%d]: %08x + %08x = %08x\n",
293 ioport_dsc[data_port].reg_off[i],
294 i, base + ioport_dsc[data_port].reg_off[i]);
296 *p++ = base + ioport_dsc[data_port].reg_off[i];
300 #ifdef CONFIG_IDE_8xx_PCCARD
303 *irq = ioport_dsc[data_port].irq;
305 pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcrb;
307 pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcra;
310 reg |= mk_int_int_mask (pcmcia_schlvl) << 24;
311 reg |= mk_int_int_mask (pcmcia_schlvl) << 16;
313 #else /* direct connected IDE drive, i.e. external IRQ, not the PCMCIA irq */
314 *irq = ioport_dsc[data_port].irq;
315 #endif /* CONFIG_IDE_8xx_PCCARD */
318 /* register routine to tune PIO mode */
319 ide_hwifs[data_port].tuneproc = m8xx_ide_tuneproc;
321 hw->ack_intr = (ide_ack_intr_t *) ide_interrupt_ack;
322 /* Enable Harddisk Interrupt,
323 * and make it edge sensitive
325 /* (11-18) Set edge detect for irq, no wakeup from low power mode */
326 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
327 (0x80000000 >> ioport_dsc[data_port].irq);
329 #ifdef CONFIG_IDE_8xx_PCCARD
330 /* Make sure we don't get garbage irq */
331 ((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pscr = 0xFFFF;
333 /* Enable falling edge irq */
334 pcmp->pcmc_per = 0x100000 >> (16 * _slot_);
335 #endif /* CONFIG_IDE_8xx_PCCARD */
336 } /* m8xx_ide_init_hwif_ports() using 8xx internal PCMCIA interface */
337 #endif /* CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT */
340 * m8xx_ide_init_hwif_ports for a direct IDE interface _not_ using
341 * MPC8xx's internal PCMCIA interface
343 #if defined(CONFIG_IDE_EXT_DIRECT)
344 void m8xx_ide_init_hwif_ports (hw_regs_t *hw,
345 unsigned long data_port, unsigned long ctrl_port, int *irq)
347 unsigned long *p = hw->io_ports;
352 static unsigned long ide_base = 0;
362 * - add code to read ORx, BRx
364 ide_phy_base = CFG_ATA_BASE_ADDR;
365 ide_phy_end = CFG_ATA_BASE_ADDR + 0x200;
367 printk ("IDE phys mem : %08x...%08x (size %08x)\n",
368 ide_phy_base, ide_phy_end,
369 ide_phy_end - ide_phy_base);
371 ide_base=(unsigned long)ioremap(ide_phy_base,
372 ide_phy_end-ide_phy_base);
375 printk ("IDE virt base: %08lx\n", ide_base);
379 if (data_port >= MAX_HWIFS)
382 base = ide_base + ioport_dsc[data_port].base_off;
384 printk ("base: %08x + %08x = %08x\n",
385 ide_base, ioport_dsc[data_port].base_off, base);
388 for (i = 0; i < IDE_NR_PORTS; ++i) {
390 printk ("port[%d]: %08x + %08x = %08x\n",
393 ioport_dsc[data_port].reg_off[i],
394 i, base + ioport_dsc[data_port].reg_off[i]);
396 *p++ = base + ioport_dsc[data_port].reg_off[i];
400 /* direct connected IDE drive, i.e. external IRQ */
401 *irq = ioport_dsc[data_port].irq;
404 /* register routine to tune PIO mode */
405 ide_hwifs[data_port].tuneproc = m8xx_ide_tuneproc;
407 hw->ack_intr = (ide_ack_intr_t *) ide_interrupt_ack;
408 /* Enable Harddisk Interrupt,
409 * and make it edge sensitive
411 /* (11-18) Set edge detect for irq, no wakeup from low power mode */
412 ((immap_t *) IMAP_ADDR)->im_siu_conf.sc_siel |=
413 (0x80000000 >> ioport_dsc[data_port].irq);
414 } /* m8xx_ide_init_hwif_ports() for CONFIG_IDE_8xx_DIRECT */
416 #endif /* CONFIG_IDE_8xx_DIRECT */
419 /* -------------------------------------------------------------------- */
424 #define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */
425 #define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */
426 #define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */
430 /* Calculate PIO timings */
432 m8xx_ide_tuneproc(ide_drive_t *drive, u8 pio)
434 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
435 volatile pcmconf8xx_t *pcmp;
436 ulong timing, mask, reg;
439 pio = ide_get_best_pio_mode(drive, pio, 4);
442 printk("%s[%d] %s: best PIO mode: %d\n",
443 __FILE__,__LINE__,__FUNCTION__, pio);
446 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
447 pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
449 mask = ~(PCMCIA_SHT(0xFF) | PCMCIA_SST(0xFF) | PCMCIA_SL(0xFF));
451 timing = PCMCIA_SHT(hold_time[pio] )
452 | PCMCIA_SST(ide_pio_clocks[pio].setup_time )
453 | PCMCIA_SL (ide_pio_clocks[pio].active_time)
457 printk ("Setting timing bits 0x%08lx in PCMCIA controller\n", timing);
459 if ((reg = pcmp->pcmc_por0 & mask) != 0)
460 pcmp->pcmc_por0 = reg | timing;
462 if ((reg = pcmp->pcmc_por1 & mask) != 0)
463 pcmp->pcmc_por1 = reg | timing;
465 if ((reg = pcmp->pcmc_por2 & mask) != 0)
466 pcmp->pcmc_por2 = reg | timing;
468 if ((reg = pcmp->pcmc_por3 & mask) != 0)
469 pcmp->pcmc_por3 = reg | timing;
471 if ((reg = pcmp->pcmc_por4 & mask) != 0)
472 pcmp->pcmc_por4 = reg | timing;
474 if ((reg = pcmp->pcmc_por5 & mask) != 0)
475 pcmp->pcmc_por5 = reg | timing;
477 if ((reg = pcmp->pcmc_por6 & mask) != 0)
478 pcmp->pcmc_por6 = reg | timing;
480 if ((reg = pcmp->pcmc_por7 & mask) != 0)
481 pcmp->pcmc_por7 = reg | timing;
483 #elif defined(CONFIG_IDE_EXT_DIRECT)
485 printk("%s[%d] %s: not implemented yet!\n",
486 __FILE__,__LINE__,__FUNCTION__);
487 #endif /* defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_PCMCIA */
491 ide_interrupt_ack (void *dev)
493 #ifdef CONFIG_IDE_8xx_PCCARD
496 #if (PCMCIA_SOCKETS_NO == 2)
500 /* get interrupt sources */
502 pscr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr;
503 pipr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr;
506 * report only if both card detect signals are the same
508 * we depend on that CD2 is the bit to the left of CD1...
512 printk("PCMCIA slot has not been defined! Using A as default\n");
516 if(((pipr & M8XX_PCMCIA_CD2(_slot_)) >> 1) ^
517 (pipr & M8XX_PCMCIA_CD1(_slot_)) ) {
518 printk ("card detect interrupt\n");
520 /* clear the interrupt sources */
521 ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr = pscr;
523 #else /* ! CONFIG_IDE_8xx_PCCARD */
525 * Only CONFIG_IDE_8xx_PCCARD is using the interrupt of the
526 * MPC8xx's PCMCIA controller, so there is nothing to be done here
527 * for CONFIG_IDE_8xx_DIRECT and CONFIG_IDE_EXT_DIRECT.
528 * The interrupt is handled somewhere else. -- Steven
530 #endif /* CONFIG_IDE_8xx_PCCARD */
538 #define CISTPL_NULL 0x00
539 #define CISTPL_DEVICE 0x01
540 #define CISTPL_LONGLINK_CB 0x02
541 #define CISTPL_INDIRECT 0x03
542 #define CISTPL_CONFIG_CB 0x04
543 #define CISTPL_CFTABLE_ENTRY_CB 0x05
544 #define CISTPL_LONGLINK_MFC 0x06
545 #define CISTPL_BAR 0x07
546 #define CISTPL_PWR_MGMNT 0x08
547 #define CISTPL_EXTDEVICE 0x09
548 #define CISTPL_CHECKSUM 0x10
549 #define CISTPL_LONGLINK_A 0x11
550 #define CISTPL_LONGLINK_C 0x12
551 #define CISTPL_LINKTARGET 0x13
552 #define CISTPL_NO_LINK 0x14
553 #define CISTPL_VERS_1 0x15
554 #define CISTPL_ALTSTR 0x16
555 #define CISTPL_DEVICE_A 0x17
556 #define CISTPL_JEDEC_C 0x18
557 #define CISTPL_JEDEC_A 0x19
558 #define CISTPL_CONFIG 0x1a
559 #define CISTPL_CFTABLE_ENTRY 0x1b
560 #define CISTPL_DEVICE_OC 0x1c
561 #define CISTPL_DEVICE_OA 0x1d
562 #define CISTPL_DEVICE_GEO 0x1e
563 #define CISTPL_DEVICE_GEO_A 0x1f
564 #define CISTPL_MANFID 0x20
565 #define CISTPL_FUNCID 0x21
566 #define CISTPL_FUNCE 0x22
567 #define CISTPL_SWIL 0x23
568 #define CISTPL_END 0xff
571 * CIS Function ID codes
573 #define CISTPL_FUNCID_MULTI 0x00
574 #define CISTPL_FUNCID_MEMORY 0x01
575 #define CISTPL_FUNCID_SERIAL 0x02
576 #define CISTPL_FUNCID_PARALLEL 0x03
577 #define CISTPL_FUNCID_FIXED 0x04
578 #define CISTPL_FUNCID_VIDEO 0x05
579 #define CISTPL_FUNCID_NETWORK 0x06
580 #define CISTPL_FUNCID_AIMS 0x07
581 #define CISTPL_FUNCID_SCSI 0x08
584 * Fixed Disk FUNCE codes
586 #define CISTPL_IDE_INTERFACE 0x01
588 #define CISTPL_FUNCE_IDE_IFACE 0x01
589 #define CISTPL_FUNCE_IDE_MASTER 0x02
590 #define CISTPL_FUNCE_IDE_SLAVE 0x03
592 /* First feature byte */
593 #define CISTPL_IDE_SILICON 0x04
594 #define CISTPL_IDE_UNIQUE 0x08
595 #define CISTPL_IDE_DUAL 0x10
597 /* Second feature byte */
598 #define CISTPL_IDE_HAS_SLEEP 0x01
599 #define CISTPL_IDE_HAS_STANDBY 0x02
600 #define CISTPL_IDE_HAS_IDLE 0x04
601 #define CISTPL_IDE_LOW_POWER 0x08
602 #define CISTPL_IDE_REG_INHIBIT 0x10
603 #define CISTPL_IDE_HAS_INDEX 0x20
604 #define CISTPL_IDE_IOIS16 0x40
607 /* -------------------------------------------------------------------- */
610 #define MAX_TUPEL_SZ 512
611 #define MAX_FEATURES 4
613 static int check_ide_device (unsigned long base)
615 volatile u8 *ident = NULL;
616 volatile u8 *feature_p[MAX_FEATURES];
617 volatile u8 *p, *start;
621 unsigned short config_base = 0;
626 printk ("PCMCIA MEM: %08lX\n", base);
628 start = p = (volatile u8 *) base;
630 while ((p - start) < MAX_TUPEL_SZ) {
634 if (code == 0xFF) { /* End of chain */
640 { volatile u8 *q = p;
641 printk ("\nTuple code %02x length %d\n\tData:",
644 for (i = 0; i < len; ++i) {
645 printk (" %02x", *q);
649 #endif /* DEBUG_PCMCIA */
658 if (n_features < MAX_FEATURES)
659 feature_p[n_features++] = p;
662 config_base = (*(p+6) << 8) + (*(p+4));
669 found = identify (ident);
671 if (func_id != ((u8)~0)) {
672 print_funcid (func_id);
674 if (func_id == CISTPL_FUNCID_FIXED)
677 return (1); /* no disk drive */
680 for (i=0; i<n_features; ++i) {
681 print_fixed (feature_p[i]);
685 printk ("unknown card type\n");
689 /* set level mode irq and I/O mapped device in config reg*/
690 *((u8 *)(base + config_base)) = 0x41;
695 /* ------------------------------------------------------------------------- */
697 static void print_funcid (int func)
700 case CISTPL_FUNCID_MULTI:
701 printk (" Multi-Function");
703 case CISTPL_FUNCID_MEMORY:
706 case CISTPL_FUNCID_SERIAL:
707 printk (" Serial Port");
709 case CISTPL_FUNCID_PARALLEL:
710 printk (" Parallel Port");
712 case CISTPL_FUNCID_FIXED:
713 printk (" Fixed Disk");
715 case CISTPL_FUNCID_VIDEO:
716 printk (" Video Adapter");
718 case CISTPL_FUNCID_NETWORK:
719 printk (" Network Adapter");
721 case CISTPL_FUNCID_AIMS:
722 printk (" AIMS Card");
724 case CISTPL_FUNCID_SCSI:
725 printk (" SCSI Adapter");
734 /* ------------------------------------------------------------------------- */
736 static void print_fixed (volatile u8 *p)
742 case CISTPL_FUNCE_IDE_IFACE:
745 printk ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
746 printk (" interface ");
749 case CISTPL_FUNCE_IDE_MASTER:
750 case CISTPL_FUNCE_IDE_SLAVE:
754 printk ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
756 if (f1 & CISTPL_IDE_UNIQUE)
757 printk (" [unique]");
759 printk ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
761 if (f2 & CISTPL_IDE_HAS_SLEEP)
764 if (f2 & CISTPL_IDE_HAS_STANDBY)
765 printk (" [standby]");
767 if (f2 & CISTPL_IDE_HAS_IDLE)
770 if (f2 & CISTPL_IDE_LOW_POWER)
771 printk (" [low power]");
773 if (f2 & CISTPL_IDE_REG_INHIBIT)
774 printk (" [reg inhibit]");
776 if (f2 & CISTPL_IDE_HAS_INDEX)
779 if (f2 & CISTPL_IDE_IOIS16)
780 printk (" [IOis16]");
788 /* ------------------------------------------------------------------------- */
791 #define MAX_IDENT_CHARS 64
792 #define MAX_IDENT_FIELDS 4
794 static u8 *known_cards[] = {
799 static int identify (volatile u8 *p)
801 u8 id_str[MAX_IDENT_CHARS];
808 return (0); /* Don't know */
813 for (i=0; i<=4 && !done; ++i, p+=2) {
814 while ((data = *p) != '\0') {
820 if (t == &id_str[MAX_IDENT_CHARS-1]) {
830 while (--t > id_str) {
836 printk ("Card ID: %s\n", id_str);
838 for (card=known_cards; *card; ++card) {
839 if (strcmp(*card, id_str) == 0) { /* found! */
844 return (0); /* don't know */
847 void m8xx_ide_init(void)
849 ppc_ide_md.default_irq = m8xx_ide_default_irq;
850 ppc_ide_md.default_io_base = m8xx_ide_default_io_base;
851 ppc_ide_md.ide_init_hwif = m8xx_ide_init_hwif_ports;