2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2010, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
53 /* un-comment DEBUG to enable pr_debug() statements */
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/clockchips.h>
59 #include <linux/hrtimer.h> /* ktime_get_real() */
60 #include <trace/events/power.h>
61 #include <linux/sched.h>
63 #define INTEL_IDLE_VERSION "0.4"
64 #define PREFIX "intel_idle: "
66 #define MWAIT_SUBSTATE_MASK (0xf)
67 #define MWAIT_CSTATE_MASK (0xf)
68 #define MWAIT_SUBSTATE_SIZE (4)
69 #define MWAIT_MAX_NUM_CSTATES 8
70 #define CPUID_MWAIT_LEAF (5)
71 #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
72 #define CPUID5_ECX_INTERRUPT_BREAK (0x2)
74 static struct cpuidle_driver intel_idle_driver = {
78 /* intel_idle.max_cstate=0 disables driver */
79 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
81 static unsigned int mwait_substates;
83 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
84 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
86 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
87 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
89 static struct cpuidle_state *cpuidle_state_table;
92 * States are indexed by the cstate number,
93 * which is also the index into the MWAIT hint array.
96 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
100 .desc = "MWAIT 0x00",
101 .driver_data = (void *) 0x00,
102 .flags = CPUIDLE_FLAG_TIME_VALID,
104 .target_residency = 6,
105 .enter = &intel_idle },
108 .desc = "MWAIT 0x10",
109 .driver_data = (void *) 0x10,
110 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
112 .target_residency = 80,
113 .enter = &intel_idle },
116 .desc = "MWAIT 0x20",
117 .driver_data = (void *) 0x20,
118 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
120 .target_residency = 800,
121 .enter = &intel_idle },
124 static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
128 .desc = "MWAIT 0x00",
129 .driver_data = (void *) 0x00,
130 .flags = CPUIDLE_FLAG_TIME_VALID,
132 .target_residency = 4,
133 .enter = &intel_idle },
136 .desc = "MWAIT 0x10",
137 .driver_data = (void *) 0x10,
138 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
140 .target_residency = 160,
141 .enter = &intel_idle },
144 .desc = "MWAIT 0x20",
145 .driver_data = (void *) 0x20,
146 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
148 .target_residency = 208,
149 .enter = &intel_idle },
152 .desc = "MWAIT 0x30",
153 .driver_data = (void *) 0x30,
154 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
156 .target_residency = 300,
157 .enter = &intel_idle },
160 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
164 .desc = "MWAIT 0x00",
165 .driver_data = (void *) 0x00,
166 .flags = CPUIDLE_FLAG_TIME_VALID,
168 .target_residency = 4,
169 .enter = &intel_idle },
172 .desc = "MWAIT 0x10",
173 .driver_data = (void *) 0x10,
174 .flags = CPUIDLE_FLAG_TIME_VALID,
176 .target_residency = 80,
177 .enter = &intel_idle },
181 .desc = "MWAIT 0x30",
182 .driver_data = (void *) 0x30,
183 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
185 .target_residency = 400,
186 .enter = &intel_idle },
190 .desc = "MWAIT 0x52",
191 .driver_data = (void *) 0x52,
192 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
194 .target_residency = 560,
195 .enter = &intel_idle },
200 * @dev: cpuidle_device
201 * @state: cpuidle state
204 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
206 unsigned long ecx = 1; /* break on interrupt flag */
207 unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
209 ktime_t kt_before, kt_after;
211 int cpu = smp_processor_id();
213 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
218 * leave_mm() to avoid costly and often unnecessary wakeups
219 * for flushing the user TLB's associated with the active mm.
221 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
224 if (!(lapic_timer_reliable_states & (1 << (cstate))))
225 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
227 kt_before = ktime_get_real();
229 stop_critical_timings();
231 trace_power_start(POWER_CSTATE, (eax >> 4) + 1, cpu);
233 if (!need_resched()) {
235 __monitor((void *)¤t_thread_info()->flags, 0, 0);
241 start_critical_timings();
243 kt_after = ktime_get_real();
244 usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
248 if (!(lapic_timer_reliable_states & (1 << (cstate))))
249 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
257 static int intel_idle_probe(void)
259 unsigned int eax, ebx, ecx;
261 if (max_cstate == 0) {
262 pr_debug(PREFIX "disabled\n");
266 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
269 if (!boot_cpu_has(X86_FEATURE_MWAIT))
272 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
275 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
277 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
278 !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
281 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
283 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
284 lapic_timer_reliable_states = 0xFFFFFFFF;
286 if (boot_cpu_data.x86 != 6) /* family 6 */
289 switch (boot_cpu_data.x86_model) {
291 case 0x1A: /* Core i7, Xeon 5500 series */
292 case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
293 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
294 case 0x2E: /* Nehalem-EX Xeon */
295 case 0x2F: /* Westmere-EX Xeon */
296 lapic_timer_reliable_states = (1 << 1); /* C1 */
298 case 0x25: /* Westmere */
299 case 0x2C: /* Westmere */
300 cpuidle_state_table = nehalem_cstates;
303 case 0x1C: /* 28 - Atom Processor */
304 case 0x26: /* 38 - Lincroft Atom Processor */
305 lapic_timer_reliable_states = (1 << 1); /* C1 */
306 cpuidle_state_table = atom_cstates;
310 case 0x2D: /* SNB Xeon */
311 cpuidle_state_table = snb_cstates;
314 case 0x17: /* 23 - Core 2 Duo */
315 lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
319 pr_debug(PREFIX "does not run on family %d model %d\n",
320 boot_cpu_data.x86, boot_cpu_data.x86_model);
324 pr_debug(PREFIX "v" INTEL_IDLE_VERSION
325 " model 0x%X\n", boot_cpu_data.x86_model);
327 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
328 lapic_timer_reliable_states);
333 * intel_idle_cpuidle_devices_uninit()
334 * unregister, free cpuidle_devices
336 static void intel_idle_cpuidle_devices_uninit(void)
339 struct cpuidle_device *dev;
341 for_each_online_cpu(i) {
342 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
343 cpuidle_unregister_device(dev);
346 free_percpu(intel_idle_cpuidle_devices);
350 * intel_idle_cpuidle_devices_init()
351 * allocate, initialize, register cpuidle_devices
353 static int intel_idle_cpuidle_devices_init(void)
356 struct cpuidle_device *dev;
358 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
359 if (intel_idle_cpuidle_devices == NULL)
362 for_each_online_cpu(i) {
363 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
365 dev->state_count = 1;
367 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
370 if (cstate > max_cstate) {
371 printk(PREFIX "max_cstate %d reached\n",
376 /* does the state exist in CPUID.MWAIT? */
377 num_substates = (mwait_substates >> ((cstate) * 4))
378 & MWAIT_SUBSTATE_MASK;
379 if (num_substates == 0)
381 /* is the state not enabled? */
382 if (cpuidle_state_table[cstate].enter == NULL) {
383 /* does the driver not know about the state? */
384 if (*cpuidle_state_table[cstate].name == '\0')
385 pr_debug(PREFIX "unaware of model 0x%x"
387 " contact lenb@kernel.org",
388 boot_cpu_data.x86_model, cstate);
393 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
394 mark_tsc_unstable("TSC halts in idle"
395 " states deeper than C2");
397 dev->states[dev->state_count] = /* structure copy */
398 cpuidle_state_table[cstate];
400 dev->state_count += 1;
404 if (cpuidle_register_device(dev)) {
405 pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
407 intel_idle_cpuidle_devices_uninit();
416 static int __init intel_idle_init(void)
420 retval = intel_idle_probe();
424 retval = cpuidle_register_driver(&intel_idle_driver);
426 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
427 cpuidle_get_driver()->name);
431 retval = intel_idle_cpuidle_devices_init();
433 cpuidle_unregister_driver(&intel_idle_driver);
440 static void __exit intel_idle_exit(void)
442 intel_idle_cpuidle_devices_uninit();
443 cpuidle_unregister_driver(&intel_idle_driver);
448 module_init(intel_idle_init);
449 module_exit(intel_idle_exit);
451 module_param(max_cstate, int, 0444);
453 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
454 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
455 MODULE_LICENSE("GPL");