2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2010, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
53 /* un-comment DEBUG to enable pr_debug() statements */
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/clockchips.h>
59 #include <linux/hrtimer.h> /* ktime_get_real() */
60 #include <trace/events/power.h>
61 #include <linux/sched.h>
62 #include <asm/mwait.h>
64 #define INTEL_IDLE_VERSION "0.4"
65 #define PREFIX "intel_idle: "
67 static struct cpuidle_driver intel_idle_driver = {
71 /* intel_idle.max_cstate=0 disables driver */
72 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
74 static unsigned int mwait_substates;
76 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
77 static unsigned int lapic_timer_reliable_states;
79 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
80 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
82 static struct cpuidle_state *cpuidle_state_table;
85 * States are indexed by the cstate number,
86 * which is also the index into the MWAIT hint array.
89 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
94 .driver_data = (void *) 0x00,
95 .flags = CPUIDLE_FLAG_TIME_VALID,
98 .target_residency = 6,
99 .enter = &intel_idle },
102 .desc = "MWAIT 0x10",
103 .driver_data = (void *) 0x10,
104 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
107 .target_residency = 80,
108 .enter = &intel_idle },
111 .desc = "MWAIT 0x20",
112 .driver_data = (void *) 0x20,
113 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
116 .target_residency = 800,
117 .enter = &intel_idle },
120 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
124 .desc = "MWAIT 0x00",
125 .driver_data = (void *) 0x00,
126 .flags = CPUIDLE_FLAG_TIME_VALID,
129 .target_residency = 4,
130 .enter = &intel_idle },
133 .desc = "MWAIT 0x10",
134 .driver_data = (void *) 0x10,
135 .flags = CPUIDLE_FLAG_TIME_VALID,
138 .target_residency = 80,
139 .enter = &intel_idle },
143 .desc = "MWAIT 0x30",
144 .driver_data = (void *) 0x30,
145 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
148 .target_residency = 400,
149 .enter = &intel_idle },
153 .desc = "MWAIT 0x52",
154 .driver_data = (void *) 0x52,
155 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
158 .target_residency = 560,
159 .enter = &intel_idle },
164 * @dev: cpuidle_device
165 * @state: cpuidle state
168 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
170 unsigned long ecx = 1; /* break on interrupt flag */
171 unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
173 ktime_t kt_before, kt_after;
175 int cpu = smp_processor_id();
177 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
182 * If the state flag indicates that the TLB will be flushed or if this
183 * is the deepest c-state supported, do a voluntary leave mm to avoid
184 * costly and mostly unnecessary wakeups for flushing the user TLB's
185 * associated with the active mm.
187 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED ||
188 (&dev->states[dev->state_count - 1] == state))
191 if (!(lapic_timer_reliable_states & (1 << (cstate))))
192 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
194 kt_before = ktime_get_real();
196 stop_critical_timings();
198 trace_power_start(POWER_CSTATE, (eax >> 4) + 1, cpu);
200 if (!need_resched()) {
202 __monitor((void *)¤t_thread_info()->flags, 0, 0);
208 start_critical_timings();
210 kt_after = ktime_get_real();
211 usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
215 if (!(lapic_timer_reliable_states & (1 << (cstate))))
216 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
224 static int intel_idle_probe(void)
226 unsigned int eax, ebx, ecx;
228 if (max_cstate == 0) {
229 pr_debug(PREFIX "disabled\n");
233 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
236 if (!boot_cpu_has(X86_FEATURE_MWAIT))
239 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
242 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
244 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
245 !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
248 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
250 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
251 lapic_timer_reliable_states = 0xFFFFFFFF;
253 if (boot_cpu_data.x86 != 6) /* family 6 */
256 switch (boot_cpu_data.x86_model) {
258 case 0x1A: /* Core i7, Xeon 5500 series */
259 case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
260 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
261 case 0x2E: /* Nehalem-EX Xeon */
262 case 0x2F: /* Westmere-EX Xeon */
263 lapic_timer_reliable_states = (1 << 1); /* C1 */
265 case 0x25: /* Westmere */
266 case 0x2C: /* Westmere */
267 cpuidle_state_table = nehalem_cstates;
270 case 0x1C: /* 28 - Atom Processor */
271 case 0x26: /* 38 - Lincroft Atom Processor */
272 lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
273 cpuidle_state_table = atom_cstates;
276 case 0x17: /* 23 - Core 2 Duo */
277 lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
281 pr_debug(PREFIX "does not run on family %d model %d\n",
282 boot_cpu_data.x86, boot_cpu_data.x86_model);
286 pr_debug(PREFIX "v" INTEL_IDLE_VERSION
287 " model 0x%X\n", boot_cpu_data.x86_model);
289 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
290 lapic_timer_reliable_states);
295 * intel_idle_cpuidle_devices_uninit()
296 * unregister, free cpuidle_devices
298 static void intel_idle_cpuidle_devices_uninit(void)
301 struct cpuidle_device *dev;
303 for_each_online_cpu(i) {
304 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
305 cpuidle_unregister_device(dev);
308 free_percpu(intel_idle_cpuidle_devices);
312 * intel_idle_cpuidle_devices_init()
313 * allocate, initialize, register cpuidle_devices
315 static int intel_idle_cpuidle_devices_init(void)
318 struct cpuidle_device *dev;
320 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
321 if (intel_idle_cpuidle_devices == NULL)
324 for_each_online_cpu(i) {
325 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
327 dev->state_count = 1;
329 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
332 if (cstate > max_cstate) {
333 printk(PREFIX "max_cstate %d reached\n",
338 /* does the state exist in CPUID.MWAIT? */
339 num_substates = (mwait_substates >> ((cstate) * 4))
340 & MWAIT_SUBSTATE_MASK;
341 if (num_substates == 0)
343 /* is the state not enabled? */
344 if (cpuidle_state_table[cstate].enter == NULL) {
345 /* does the driver not know about the state? */
346 if (*cpuidle_state_table[cstate].name == '\0')
347 pr_debug(PREFIX "unaware of model 0x%x"
349 " contact lenb@kernel.org",
350 boot_cpu_data.x86_model, cstate);
355 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
356 mark_tsc_unstable("TSC halts in idle"
357 " states deeper than C2");
359 dev->states[dev->state_count] = /* structure copy */
360 cpuidle_state_table[cstate];
362 dev->state_count += 1;
366 if (cpuidle_register_device(dev)) {
367 pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
369 intel_idle_cpuidle_devices_uninit();
378 static int __init intel_idle_init(void)
382 retval = intel_idle_probe();
386 retval = cpuidle_register_driver(&intel_idle_driver);
388 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
389 cpuidle_get_driver()->name);
393 retval = intel_idle_cpuidle_devices_init();
395 cpuidle_unregister_driver(&intel_idle_driver);
402 static void __exit intel_idle_exit(void)
404 intel_idle_cpuidle_devices_uninit();
405 cpuidle_unregister_driver(&intel_idle_driver);
410 module_init(intel_idle_init);
411 module_exit(intel_idle_exit);
413 module_param(max_cstate, int, 0444);
415 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
416 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
417 MODULE_LICENSE("GPL");