2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2013, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
53 /* un-comment DEBUG to enable pr_debug() statements */
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/clockchips.h>
59 #include <trace/events/power.h>
60 #include <linux/sched.h>
61 #include <linux/notifier.h>
62 #include <linux/cpu.h>
63 #include <linux/module.h>
64 #include <asm/cpu_device_id.h>
65 #include <asm/mwait.h>
68 #define INTEL_IDLE_VERSION "0.4"
69 #define PREFIX "intel_idle: "
71 static struct cpuidle_driver intel_idle_driver = {
75 /* intel_idle.max_cstate=0 disables driver */
76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
78 static unsigned int mwait_substates;
80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
81 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
82 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
85 struct cpuidle_state *state_table;
88 * Hardware C-state auto-demotion may not always be optimal.
89 * Indicate which enable bits to clear here.
91 unsigned long auto_demotion_disable_flags;
92 bool byt_auto_demotion_disable_flag;
93 bool disable_promotion_to_c1e;
96 static const struct idle_cpu *icpu;
97 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
98 static int intel_idle(struct cpuidle_device *dev,
99 struct cpuidle_driver *drv, int index);
100 static int intel_idle_cpu_init(int cpu);
102 static struct cpuidle_state *cpuidle_state_table;
105 * Set this flag for states where the HW flushes the TLB for us
106 * and so we don't need cross-calls to keep it consistent.
107 * If this flag is set, SW flushes the TLB, so even if the
108 * HW doesn't do the flushing, this flag is safe to use.
110 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
113 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
114 * the C-state (top nibble) and sub-state (bottom nibble)
115 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
117 * We store the hint at the top of our "flags" for each state.
119 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
120 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
123 * States are indexed by the cstate number,
124 * which is also the index into the MWAIT hint array.
125 * Thus C0 is a dummy.
127 static struct cpuidle_state nehalem_cstates[] = {
130 .desc = "MWAIT 0x00",
131 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
133 .target_residency = 6,
134 .enter = &intel_idle },
137 .desc = "MWAIT 0x01",
138 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
140 .target_residency = 20,
141 .enter = &intel_idle },
144 .desc = "MWAIT 0x10",
145 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
147 .target_residency = 80,
148 .enter = &intel_idle },
151 .desc = "MWAIT 0x20",
152 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
154 .target_residency = 800,
155 .enter = &intel_idle },
160 static struct cpuidle_state snb_cstates[] = {
163 .desc = "MWAIT 0x00",
164 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
166 .target_residency = 2,
167 .enter = &intel_idle },
170 .desc = "MWAIT 0x01",
171 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
173 .target_residency = 20,
174 .enter = &intel_idle },
177 .desc = "MWAIT 0x10",
178 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
180 .target_residency = 211,
181 .enter = &intel_idle },
184 .desc = "MWAIT 0x20",
185 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
187 .target_residency = 345,
188 .enter = &intel_idle },
191 .desc = "MWAIT 0x30",
192 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
194 .target_residency = 345,
195 .enter = &intel_idle },
200 static struct cpuidle_state byt_cstates[] = {
203 .desc = "MWAIT 0x00",
204 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
206 .target_residency = 1,
207 .enter = &intel_idle },
210 .desc = "MWAIT 0x01",
211 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
213 .target_residency = 30,
214 .enter = &intel_idle },
217 .desc = "MWAIT 0x58",
218 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
220 .target_residency = 275,
221 .enter = &intel_idle },
224 .desc = "MWAIT 0x52",
225 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
227 .target_residency = 560,
228 .enter = &intel_idle },
231 .desc = "MWAIT 0x60",
232 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
233 .exit_latency = 1200,
234 .target_residency = 1500,
235 .enter = &intel_idle },
238 .desc = "MWAIT 0x64",
239 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
240 .exit_latency = 10000,
241 .target_residency = 20000,
242 .enter = &intel_idle },
247 static struct cpuidle_state ivb_cstates[] = {
250 .desc = "MWAIT 0x00",
251 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
253 .target_residency = 1,
254 .enter = &intel_idle },
257 .desc = "MWAIT 0x01",
258 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
260 .target_residency = 20,
261 .enter = &intel_idle },
264 .desc = "MWAIT 0x10",
265 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
267 .target_residency = 156,
268 .enter = &intel_idle },
271 .desc = "MWAIT 0x20",
272 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
274 .target_residency = 300,
275 .enter = &intel_idle },
278 .desc = "MWAIT 0x30",
279 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
281 .target_residency = 300,
282 .enter = &intel_idle },
287 static struct cpuidle_state ivt_cstates[] = {
290 .desc = "MWAIT 0x00",
291 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
293 .target_residency = 1,
294 .enter = &intel_idle },
297 .desc = "MWAIT 0x01",
298 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
300 .target_residency = 80,
301 .enter = &intel_idle },
304 .desc = "MWAIT 0x10",
305 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
307 .target_residency = 156,
308 .enter = &intel_idle },
311 .desc = "MWAIT 0x20",
312 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
314 .target_residency = 300,
315 .enter = &intel_idle },
320 static struct cpuidle_state ivt_cstates_4s[] = {
323 .desc = "MWAIT 0x00",
324 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
326 .target_residency = 1,
327 .enter = &intel_idle },
329 .name = "C1E-IVT-4S",
330 .desc = "MWAIT 0x01",
331 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
333 .target_residency = 250,
334 .enter = &intel_idle },
337 .desc = "MWAIT 0x10",
338 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
340 .target_residency = 300,
341 .enter = &intel_idle },
344 .desc = "MWAIT 0x20",
345 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
347 .target_residency = 400,
348 .enter = &intel_idle },
353 static struct cpuidle_state ivt_cstates_8s[] = {
356 .desc = "MWAIT 0x00",
357 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
359 .target_residency = 1,
360 .enter = &intel_idle },
362 .name = "C1E-IVT-8S",
363 .desc = "MWAIT 0x01",
364 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
366 .target_residency = 500,
367 .enter = &intel_idle },
370 .desc = "MWAIT 0x10",
371 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
373 .target_residency = 600,
374 .enter = &intel_idle },
377 .desc = "MWAIT 0x20",
378 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
380 .target_residency = 700,
381 .enter = &intel_idle },
386 static struct cpuidle_state hsw_cstates[] = {
389 .desc = "MWAIT 0x00",
390 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
392 .target_residency = 2,
393 .enter = &intel_idle },
396 .desc = "MWAIT 0x01",
397 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
399 .target_residency = 20,
400 .enter = &intel_idle },
403 .desc = "MWAIT 0x10",
404 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
406 .target_residency = 100,
407 .enter = &intel_idle },
410 .desc = "MWAIT 0x20",
411 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
413 .target_residency = 400,
414 .enter = &intel_idle },
417 .desc = "MWAIT 0x32",
418 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
420 .target_residency = 500,
421 .enter = &intel_idle },
424 .desc = "MWAIT 0x40",
425 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
427 .target_residency = 900,
428 .enter = &intel_idle },
431 .desc = "MWAIT 0x50",
432 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
434 .target_residency = 1800,
435 .enter = &intel_idle },
438 .desc = "MWAIT 0x60",
439 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
440 .exit_latency = 2600,
441 .target_residency = 7700,
442 .enter = &intel_idle },
447 static struct cpuidle_state atom_cstates[] = {
450 .desc = "MWAIT 0x00",
451 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
453 .target_residency = 20,
454 .enter = &intel_idle },
457 .desc = "MWAIT 0x10",
458 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
460 .target_residency = 80,
461 .enter = &intel_idle },
464 .desc = "MWAIT 0x30",
465 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
467 .target_residency = 400,
468 .enter = &intel_idle },
471 .desc = "MWAIT 0x52",
472 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
474 .target_residency = 560,
475 .enter = &intel_idle },
479 static struct cpuidle_state avn_cstates[] = {
482 .desc = "MWAIT 0x00",
483 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
485 .target_residency = 2,
486 .enter = &intel_idle },
489 .desc = "MWAIT 0x51",
490 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
492 .target_residency = 45,
493 .enter = &intel_idle },
500 * @dev: cpuidle_device
501 * @drv: cpuidle driver
502 * @index: index of cpuidle state
504 * Must be called under local_irq_disable().
506 static int intel_idle(struct cpuidle_device *dev,
507 struct cpuidle_driver *drv, int index)
509 unsigned long ecx = 1; /* break on interrupt flag */
510 struct cpuidle_state *state = &drv->states[index];
511 unsigned long eax = flg2MWAIT(state->flags);
513 int cpu = smp_processor_id();
515 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
518 * leave_mm() to avoid costly and often unnecessary wakeups
519 * for flushing the user TLB's associated with the active mm.
521 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
524 if (!(lapic_timer_reliable_states & (1 << (cstate))))
525 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
527 mwait_idle_with_hints(eax, ecx);
529 if (!(lapic_timer_reliable_states & (1 << (cstate))))
530 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
535 static void __setup_broadcast_timer(void *arg)
537 unsigned long reason = (unsigned long)arg;
538 int cpu = smp_processor_id();
541 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
543 clockevents_notify(reason, &cpu);
546 static int cpu_hotplug_notify(struct notifier_block *n,
547 unsigned long action, void *hcpu)
549 int hotcpu = (unsigned long)hcpu;
550 struct cpuidle_device *dev;
552 switch (action & ~CPU_TASKS_FROZEN) {
555 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
556 smp_call_function_single(hotcpu, __setup_broadcast_timer,
560 * Some systems can hotplug a cpu at runtime after
561 * the kernel has booted, we have to initialize the
562 * driver in this case
564 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
565 if (!dev->registered)
566 intel_idle_cpu_init(hotcpu);
573 static struct notifier_block cpu_hotplug_notifier = {
574 .notifier_call = cpu_hotplug_notify,
577 static void auto_demotion_disable(void *dummy)
579 unsigned long long msr_bits;
581 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
582 msr_bits &= ~(icpu->auto_demotion_disable_flags);
583 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
585 static void c1e_promotion_disable(void *dummy)
587 unsigned long long msr_bits;
589 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
591 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
594 static const struct idle_cpu idle_cpu_nehalem = {
595 .state_table = nehalem_cstates,
596 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
597 .disable_promotion_to_c1e = true,
600 static const struct idle_cpu idle_cpu_atom = {
601 .state_table = atom_cstates,
604 static const struct idle_cpu idle_cpu_lincroft = {
605 .state_table = atom_cstates,
606 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
609 static const struct idle_cpu idle_cpu_snb = {
610 .state_table = snb_cstates,
611 .disable_promotion_to_c1e = true,
614 static const struct idle_cpu idle_cpu_byt = {
615 .state_table = byt_cstates,
616 .disable_promotion_to_c1e = true,
617 .byt_auto_demotion_disable_flag = true,
620 static const struct idle_cpu idle_cpu_ivb = {
621 .state_table = ivb_cstates,
622 .disable_promotion_to_c1e = true,
625 static const struct idle_cpu idle_cpu_ivt = {
626 .state_table = ivt_cstates,
627 .disable_promotion_to_c1e = true,
630 static const struct idle_cpu idle_cpu_hsw = {
631 .state_table = hsw_cstates,
632 .disable_promotion_to_c1e = true,
635 static const struct idle_cpu idle_cpu_avn = {
636 .state_table = avn_cstates,
637 .disable_promotion_to_c1e = true,
640 #define ICPU(model, cpu) \
641 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
643 static const struct x86_cpu_id intel_idle_ids[] = {
644 ICPU(0x1a, idle_cpu_nehalem),
645 ICPU(0x1e, idle_cpu_nehalem),
646 ICPU(0x1f, idle_cpu_nehalem),
647 ICPU(0x25, idle_cpu_nehalem),
648 ICPU(0x2c, idle_cpu_nehalem),
649 ICPU(0x2e, idle_cpu_nehalem),
650 ICPU(0x1c, idle_cpu_atom),
651 ICPU(0x26, idle_cpu_lincroft),
652 ICPU(0x2f, idle_cpu_nehalem),
653 ICPU(0x2a, idle_cpu_snb),
654 ICPU(0x2d, idle_cpu_snb),
655 ICPU(0x36, idle_cpu_atom),
656 ICPU(0x37, idle_cpu_byt),
657 ICPU(0x3a, idle_cpu_ivb),
658 ICPU(0x3e, idle_cpu_ivt),
659 ICPU(0x3c, idle_cpu_hsw),
660 ICPU(0x3f, idle_cpu_hsw),
661 ICPU(0x45, idle_cpu_hsw),
662 ICPU(0x46, idle_cpu_hsw),
663 ICPU(0x4D, idle_cpu_avn),
666 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
671 static int __init intel_idle_probe(void)
673 unsigned int eax, ebx, ecx;
674 const struct x86_cpu_id *id;
676 if (max_cstate == 0) {
677 pr_debug(PREFIX "disabled\n");
681 id = x86_match_cpu(intel_idle_ids);
683 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
684 boot_cpu_data.x86 == 6)
685 pr_debug(PREFIX "does not run on family %d model %d\n",
686 boot_cpu_data.x86, boot_cpu_data.x86_model);
690 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
693 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
695 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
696 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
700 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
702 icpu = (const struct idle_cpu *)id->driver_data;
703 cpuidle_state_table = icpu->state_table;
705 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
706 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
708 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
710 pr_debug(PREFIX "v" INTEL_IDLE_VERSION
711 " model 0x%X\n", boot_cpu_data.x86_model);
713 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
714 lapic_timer_reliable_states);
719 * intel_idle_cpuidle_devices_uninit()
720 * unregister, free cpuidle_devices
722 static void intel_idle_cpuidle_devices_uninit(void)
725 struct cpuidle_device *dev;
727 for_each_online_cpu(i) {
728 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
729 cpuidle_unregister_device(dev);
732 free_percpu(intel_idle_cpuidle_devices);
737 * intel_idle_state_table_update()
739 * Update the default state_table for this CPU-id
741 * Currently used to access tuned IVT multi-socket targets
742 * Assumption: num_sockets == (max_package_num + 1)
744 void intel_idle_state_table_update(void)
746 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
747 if (boot_cpu_data.x86_model == 0x3e) { /* IVT */
748 int cpu, package_num, num_sockets = 1;
750 for_each_online_cpu(cpu) {
751 package_num = topology_physical_package_id(cpu);
752 if (package_num + 1 > num_sockets) {
753 num_sockets = package_num + 1;
755 if (num_sockets > 4) {
756 cpuidle_state_table = ivt_cstates_8s;
763 cpuidle_state_table = ivt_cstates_4s;
764 /* else, 1 and 2 socket systems use default ivt_cstates */
770 * intel_idle_cpuidle_driver_init()
771 * allocate, initialize cpuidle_states
773 static int __init intel_idle_cpuidle_driver_init(void)
776 struct cpuidle_driver *drv = &intel_idle_driver;
778 intel_idle_state_table_update();
780 drv->state_count = 1;
782 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
783 int num_substates, mwait_hint, mwait_cstate;
785 if (cpuidle_state_table[cstate].enter == NULL)
788 if (cstate + 1 > max_cstate) {
789 printk(PREFIX "max_cstate %d reached\n",
794 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
795 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
797 /* number of sub-states for this state in CPUID.MWAIT */
798 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
799 & MWAIT_SUBSTATE_MASK;
801 /* if NO sub-states for this state in CPUID, skip it */
802 if (num_substates == 0)
805 if (((mwait_cstate + 1) > 2) &&
806 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
807 mark_tsc_unstable("TSC halts in idle"
808 " states deeper than C2");
810 drv->states[drv->state_count] = /* structure copy */
811 cpuidle_state_table[cstate];
813 drv->state_count += 1;
816 if (icpu->auto_demotion_disable_flags)
817 on_each_cpu(auto_demotion_disable, NULL, 1);
819 if (icpu->byt_auto_demotion_disable_flag) {
820 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
821 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
824 if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */
825 on_each_cpu(c1e_promotion_disable, NULL, 1);
832 * intel_idle_cpu_init()
833 * allocate, initialize, register cpuidle_devices
834 * @cpu: cpu/core to initialize
836 static int intel_idle_cpu_init(int cpu)
838 struct cpuidle_device *dev;
840 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
844 if (cpuidle_register_device(dev)) {
845 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
846 intel_idle_cpuidle_devices_uninit();
850 if (icpu->auto_demotion_disable_flags)
851 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
853 if (icpu->disable_promotion_to_c1e)
854 smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1);
859 static int __init intel_idle_init(void)
863 /* Do not load intel_idle at all for now if idle= is passed */
864 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
867 retval = intel_idle_probe();
871 intel_idle_cpuidle_driver_init();
872 retval = cpuidle_register_driver(&intel_idle_driver);
874 struct cpuidle_driver *drv = cpuidle_get_driver();
875 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
876 drv ? drv->name : "none");
880 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
881 if (intel_idle_cpuidle_devices == NULL)
884 cpu_notifier_register_begin();
886 for_each_online_cpu(i) {
887 retval = intel_idle_cpu_init(i);
889 cpu_notifier_register_done();
890 cpuidle_unregister_driver(&intel_idle_driver);
894 __register_cpu_notifier(&cpu_hotplug_notifier);
896 cpu_notifier_register_done();
901 static void __exit intel_idle_exit(void)
903 intel_idle_cpuidle_devices_uninit();
904 cpuidle_unregister_driver(&intel_idle_driver);
906 cpu_notifier_register_begin();
908 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
909 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
910 __unregister_cpu_notifier(&cpu_hotplug_notifier);
912 cpu_notifier_register_done();
917 module_init(intel_idle_init);
918 module_exit(intel_idle_exit);
920 module_param(max_cstate, int, 0444);
922 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
923 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
924 MODULE_LICENSE("GPL");